ST STM32F301 6 Series Reference Manual page 256

Analog-to-digital converters (ADC)
12.5.6 ADC sample time register 2 (ADCx_SMPR2, x=1)
Address offset: 0x18
Reset value: 0x0000 0000
31 30 29
Res. Res. Res.
15 14 13
SMP15_0 SMP14[2:0]
rw rw rw
Bits 31:27 Reserved, must be kept at reset value.
Bits 26:0 SMPx[2:0]: Channel x sampling time selection
These bits are written by software to select the sampling time individually for each channel.
During sampling cycles, the channel selection bits must remain unchanged.
000: 1.5 ADC clock cycles
001: 2.5 ADC clock cycles
010: 4.5 ADC clock cycles
011: 7.5 ADC clock cycles
100: 19.5 ADC clock cycles
101: 61.5 ADC clock cycles
110: 181.5 ADC clock cycles
111: 601.5 ADC clock cycles
Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0
12.5.7 ADC watchdog threshold register 1 (ADCx_TR1, x=1)
Address offset: 0x20
Reset value: 0x0FFF 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:28 Reserved, must be kept at reset value.
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28 27 26 25
Res. Res. SMP18[2:0]
rw rw
12 11 10 9
SMP13[2:0]
rw rw rw rw
(which ensures that no conversion is ongoing).
28 27 26 25
12 11 10 9
rw rw rw
24 23 22
SMP17[2:0]
rw rw rw
8 7 6
SMP12[2:0]
rw rw rw
24 23 22
HT1[11:0]
8 7 6
LT1[11:0]
rw rw rw
RM0366 Rev 5
21 20 19 18
SMP16[2:0]
rw rw rw rw
5 4 3 2
SMP11[2:0]
rw rw rw rw
21 20 19 18
5 4 3 2
rw rw rw rw
RM0366
17 16
SMP15[2:1]
rw rw
1 0
SMP10[2:0]
rw rw
17 16
1 0
rw rw