ST STM32F301 6 Series Reference Manual page 154

Direct memory access controller (DMA)
Peripheral request signals
SPI2_RX
USART1_TX
I2C2_TX
TIM1_CH4
TIM1_TRIG
TIM1_COM
USART2_RX
I2C1_TX
TIM1_CH3
TIM16_CH1
(1)
TIM16_UP
1. DMA request mapped on this DMA channel only if the corresponding remapping bit is set in
1 (SYSCFG_CFGR1).
154/874
Figure 20. DMA request mapping
ADC1
TIM2_CH3
TIM17_CH1
TIM17_UP
I2C3_TX
USART3_TX
TIM1_CH1
TIM2_UP
I2C3_RX
SPI3_TX
USART3_RX
TIM1_CH2
(1)
TIM6_UP
(1)
DAC1_CH1
TIM16_CH1
TIM16_UP
SPI2_TX
USART1_RX
I2C2_RX
TIM1_UP
TIM2_CH1
TIM15_CH1
TIM15_UP
TIM15_TRIG
TIM15_COM
USART2_TX
I2C1_RX
TIM2_CH2
TIM2_CH4
(1)
TIM17_CH1
(1)
TIM17_UP
DMA
HW request 1
SW trigger 1
(MEM2MEM bit)
HW request 2
SW trigger 2
(
MEM2MEM bit)
HW request 3
SW trigger 3
(
MEM2MEM bit)
HW request 4
SW trigger 4
(
MEM2MEM bit)
HW request 5
SW trigger 5
(
MEM2MEM bit)
HW request 6
6
SW trigger
(
MEM2MEM bit)
HW request 7
SW trigger 7
(
MEM2MEM bit)
RM0366 Rev 5
Fixed hardware priority
High priority
Channel 1
Channel 2
Internal
Channel 3
request
Channel 4
Channel 5
Channel 6
Channel 7
Low priority
MS34224V1
SYSCFG configuration register
RM0366
DMA