ST STM32F301 6 Series Reference Manual page 427

RM0366
ETR
TIMx_ETR
XOR
TI1
TIMx_CH1
TI2
TIMx_CH2
TI3
TIMx_CH3
TI4
TIMx_CH4
Notes:
Preload registers transferred
Reg
to active registers on U event
according to control bit
Event
Interrupt & DMA output
Figure 149. General-purpose timer block diagram
Internal clock (CK_INT)
From RCC
Polarity selection & edge
detector & prescaler
ITR0
ITR1
ITR2
ITR3
TI1F_ED
CK_PSC
TI1FP1
IC1
Input filter &
TI1FP2
edge detector
TRC
TI2FP1
Input filter &
IC2
TI2FP2
edge detector
TRC
TI3FP3
IC3
Input filter &
TI3FP4
edge detector
TRC
TI4FP3
Input filter &
IC4
TI4FP4
edge detector
TRC
ETRF
ETRP
Input filter
TRG
ITR
TRC
TRGI
TI1FP1
TI2FP2
U
Auto-reload register
Stop, clear or up/down
PSC CK_CNT
+/-
CNT counter
prescaler
CC1I
U
IC1PS
Capture/Compare 1 register
Prescaler
CC2I
U
IC2PS
Capture/Compare 2 register
Prescaler
CC3I
U
IC3PS
Capture/Compare 3 register
Prescaler
CC4I
U
IC4PS
Capture/Compare 4 register
Prescaler
ETRF
RM0366 Rev 5
General-purpose timer (TIM2)
Trigger
controller
TRGO
to other timers
to peripherals
Slave
Reset, enable, count
controller
mode
Encoder
interface
UI
U
CC1I
OC1REF
Output
control
CC2I
Output
OC2REF
control
CC3I
OC3REF
Output
control
CC4I
Output
OC4
OC4REF
control
OC1
TIMx_CH1
OC2
TIMx_CH2
OC3
TIMx_CH3
TIMx_CH4
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