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ST STM32F423 Reference Manual

ST STM32F423 Reference Manual

Advanced arm-based 32-bit mcus

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RM0430

Reference manual

®

STM32F413/423 advanced Arm

-based 32-bit MCUs

Introduction

This reference manual targets application developers. It provides complete information on

how to use the memory and the peripherals of the STM32F413/423 microcontrollers.

The STM32F413/423 is a line of microcontrollers with different memory sizes, packages and

peripherals.

For ordering information, mechanical and electrical device characteristics refer to the

datasheet.

®

®

®

For information on the Arm

Cortex

-M4 with FPU core, refer to the Cortex

-M4 Technical

Reference Manual.

Related documents

Available from STMicroelectronics web site www.st.com:

• STM32F413/423xG/xH datasheet

®

• PM0214 "STM32F3 and STM32F4 Series Cortex

-M4 with FPU-M4 programming

®

®

manual" for information on the Arm

Cortex

-M4 with FPU.

May 2018

RM0430 Rev 8

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Summary of Contents for ST STM32F423

Page 1 For information on the Arm Cortex -M4 with FPU core, refer to the Cortex -M4 Technical Reference Manual. Related documents Available from STMicroelectronics web site www.st.com: • STM32F413/423xG/xH datasheet ® • PM0214 “STM32F3 and STM32F4 Series Cortex -M4 with FPU-M4 programming ®...
Page 2: Table Of Contents
Contents RM0430 Contents Documentation conventions ....... . . 52 General information ......... 52 List of abbreviations for registers .
Page 3 RM0430 Contents 3.5.3 Erase ........... 72 3.5.4 Programming .
Page 4: Syscfg External Interrupt Configuration Register
Contents RM0430 5.2.2 Brownout reset (BOR) ........98 5.2.3 Programmable voltage detector (PVD) .
Page 5 RM0430 Contents 6.3.4 RCC clock interrupt register (RCC_CIR) ..... . . 136 6.3.5 RCC AHB1 peripheral reset register (RCC_AHB1RSTR) ..138 6.3.6 RCC AHB2 peripheral reset register (RCC_AHB2RSTR) for STM32F413xx .
Page 6 Contents RM0430 GPIO introduction ......... . 184 GPIO main features .
Page 7 RM0430 Contents I/O compensation cell ........204 SYSCFG registers .
Page 8 Contents RM0430 9.3.17 Summary of the possible DMA configurations ....231 9.3.18 Stream configuration procedure ......232 9.3.19 Error management .
Page 9 RM0430 Contents Flexible static memory controller (FSMC) ..... 264 11.1 FSMC main features ........264 11.2 FMC block diagram .
Page 10 Contents RM0430 12.5 QUADSPI registers ........323 12.5.1 QUADSPI control register (QUADSPI_CR) .
Page 11 RM0430 Contents 13.8.2 Managing a sequence of conversions without using the DMA ..347 13.8.3 Conversions without DMA and without overrun detection ..348 13.9 Temperature sensor ........348 13.10 Battery charge monitoring .
Page 12 Contents RM0430 14.3.9 Triangle-wave generation ........372 14.4 Dual DAC channel conversion .
Page 13 RM0430 Contents 15.1 Introduction ..........388 15.2 DFSDM main features .
Page 14 Contents RM0430 15.8.5 DFSDM filter x injected channel group selection register (DFSDM_FLTxJCHGR) ........433 15.8.6 DFSDM filter x control register (DFSDM_FLTxFCR) .
Page 15 RM0430 Contents 16.7.3 Data collection ......... . . 457 16.8 RNG registers .
Page 16 Contents RM0430 17.4.5 TIM1&TIM8 status register (TIMx_SR) ......514 17.4.6 TIM1&TIM8 event generation register (TIMx_EGR) ....515 17.4.7 TIM1&TIM8 capture/compare mode register 1 (TIMx_CCMR1) .
Page 17 RM0430 Contents 18.3.16 Debug mode ..........571 18.4 TIM2 to TIM5 registers .
Page 18 Contents RM0430 19.3.8 Output compare mode ........609 19.3.9 PWM mode .
Page 19 RM0430 Contents 20.1 Introduction ..........642 20.2 TIM6/7 main features .
Page 20 Contents RM0430 21.4.14 Encoder mode ......... . . 664 21.4.15 Debug mode .
Page 21 RM0430 Contents 23.6.1 Control register (WWDG_CR) ....... 688 23.6.2 Configuration register (WWDG_CFR) ......689 23.6.3 Status register (WWDG_SR) .
Page 22 Contents RM0430 24.7.7 AES key register 2 (AES_KEYR2) ......737 24.7.8 AES key register 3 (AES_KEYR3) ......738 24.7.9 AES initialization vector register 0 (AES_IVR0) .
Page 23 RM0430 Contents 25.6.2 RTC date register (RTC_DR) ....... . 761 25.6.3 RTC control register (RTC_CR) .
Page 24 Contents RM0430 26.4.11 SMBus initialization ........818 26.4.12 SMBus: FMPI2C_TIMEOUTR register configuration examples .
Page 25 RM0430 Contents 27.5 C debug mode ......... . . 869 27.6 C registers .
Page 26 Contents RM0430 28.6.1 Status register (USART_SR) ....... . 924 28.6.2 Data register (USART_DR) .
Page 27 RM0430 Contents 29.6.3 Supported audio protocols ........961 29.6.4 Clock generator .
Page 28 Contents RM0430 30.10 Internal FIFOs ..........997 30.11 AC’97 link controller .
Page 29 RM0430 Contents 31.4.3 Operating voltage range validation ......1043 31.4.4 Card identification process ....... . 1043 31.4.5 Block write .
Page 30 Contents RM0430 31.8.9 SDIO data control register (SDIO_DCTRL) ....1073 31.8.10 SDIO data counter register (SDIO_DCOUNT) ....1076 31.8.11 SDIO status register (SDIO_STA) .
Page 31 RM0430 Contents 32.9.1 Register access protection ....... . 1106 32.9.2 CAN control and status registers .
Page 32 Contents RM0430 33.10 Dynamic update of the OTG_HFIR register ..... .1149 33.11 USB data FIFOs ......... . .1149 33.11.1 Peripheral FIFO architecture .
Page 33 RM0430 Contents 33.15.21 OTG_Host periodic transmit FIFO/queue status register (OTG_HPTXSTS) ........1191 33.15.22 OTG host all channels interrupt register (OTG_HAINT) .
Page 34 Contents RM0430 33.15.45 OTG device IN endpoint x transfer size register (OTG_DIEPTSIZx) (x = 1..5, where x = endpoint number) ......1217 33.15.46 OTG device control OUT endpoint 0 control register (OTG_DOEPCTL0) .
Page 35 RM0430 Contents ® 34.6.3 Cortex -M4 with FPU TAP ....... . . 1291 ®...
Page 36 Contents RM0430 34.17.6 Synchronous mode ........1311 34.17.7 Asynchronous mode .
Page 37 RM0430 List of tables List of tables Table 1. Register boundary addresses ..........59 Table 2.
Page 38 List of tables RM0430 Table 49. NOR Flash/PSRAM: example of supported memories and transactions ... . . 272 Table 50. FSMC_BCRx bit fields ........... 275 Table 51.
Page 39 RM0430 List of tables Table 99. RNG interrupt requests ........... 456 Table 100.
Page 40 List of tables RM0430 Table 149. Examples of TIMEOUTA settings for various FMPI2CCLK frequencies (max t = 50 µs) ............820 IDLE Table 150.
Page 41 RM0430 List of tables Table 190. Receive FIFO status flags ..........1040 Table 191.
Page 42 List of tables RM0430 Table 242. Main ITM registers ........... . . 1301 Table 243.
Page 43 RM0430 List of figures List of figures Figure 1. System architecture ............55 Figure 2.
Page 44 List of figures RM0430 Figure 49. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) ... 293 Figure 50. Synchronous multiplexed write mode waveforms - PSRAM (CRAM)....295 Figure 51.
Page 45 RM0430 List of figures Figure 99. Counter timing diagram, internal clock divided by N......471 Figure 100.
Page 46 List of figures RM0430 Figure 151. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 ....544 Figure 152. Counter timing diagram, internal clock divided by N......544 Figure 153.
Page 47 RM0430 List of figures Figure 201. Control circuit in reset mode ..........614 Figure 202.
Page 48 List of figures RM0430 Figure 250. 128-bit block construction with respect to data swap ......725 Figure 251.
Page 49 RM0430 List of figures Figure 302. Break detection in LIN mode vs. Framing error detection......912 Figure 303.
Page 50 List of figures RM0430 Figure 351. Functional block diagram ..........989 Figure 352.
Page 51 RM0430 List of figures Figure 403. Interrupt hierarchy............1155 Figure 404.
Page 52: Documentation Conventions
Documentation conventions RM0430 Documentation conventions General information ®(a) ® The STM32F413/423 devices have an Arm Cortex -M4 with FPU core List of abbreviations for registers The following abbreviations are used in register descriptions: read/write (rw) Software can read and write to this bit. read-only (r) Software can only read this bit.
Page 53: Glossary
RM0430 Documentation conventions Glossary This section gives a brief definition of acronyms and abbreviations used in this document: • Word: data of 32-bit length. • Half-word: data of 16-bit length. • Byte: data of 8-bit length. • IAP (in-application programming): IAP is the ability to re-program the Flash memory of a microcontroller while the user program is running.
Page 54: System And Memory Overview
System and memory overview RM0430 System and memory overview System architecture In STM32F413/423, the main system consists of 32-bit multilayer AHB bus matrix that interconnects: • Six masters: ® – Cortex -M4 with FPU core I-bus, D-bus and S-bus – DMA1 memory bus –...
Page 55: I-Bus
RM0430 System and memory overview Figure 1. System architecture 2.1.1 I-bus ® This bus connects the Instruction bus of the Cortex -M4 with FPU core to the BusMatrix. This bus is used by the core to fetch instructions. The target of this bus is a memory containing code (internal Flash memory/SRAM1/SRAM2).
Page 56: Dma Peripheral Bus
System and memory overview RM0430 2.1.5 DMA peripheral bus This bus connects the DMA peripheral master bus interface to the BusMatrix. This bus is used by the DMA to access AHB peripherals or to perform memory-to-memory transfers. The targets of this bus are the AHB and APB peripherals plus data memories: Flash memory and internal SRAM1/SRAM2.
Page 57: Memory Organization
RM0430 Memory organization 2.2.1 Introduction Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space. The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word’s least significant byte and the highest numbered byte the most significant.
Page 58: Memory Map And Register Boundary Addresses
RM0430 2.2.2 Memory map and register boundary addresses Figure 2. Memory map All the memory map areas that are not allocated to on-chip memories and peripherals are considered “Reserved”. For the detailed mapping of available memory and register areas, refer to the following table. 58/1324 RM0430 Rev 8...
Page 59: Table 1. Register Boundary Addresses
RM0430 The following table gives the boundary addresses of the peripherals available in the devices. Table 1. Register boundary addresses Boundary address Peripheral 0xE010 0000 - 0xFFFF FFFF Reserved ® Cortex 0xE000 0000 - 0xE00F FFFF Cortex-M4 internal peripherals 0xA000 2000 - 0xDFFF FFFF Reserved 0xA000 1000 - 0xA000 1FFF QuadSPI control register...
Page 60 RM0430 Table 1. Register boundary addresses (continued) Boundary address Peripheral 0x4001 6800 - 0x4001 FFFF Reserved 0x4001 6400 - 0x4001 67FF DFSDM2 0x4001 6000 - 0x4001 63FF DFSDM1 0x4001 5C00 - 0x4001 5FFF Reserved 0x4001 5800 - 0x4001 5BFF SAI1 0x4001 5400 - 0x4001 57FF Reserved 0x4001 5000 - 0x4001 53FF...
Page 61 RM0430 Table 1. Register boundary addresses (continued) Boundary address Peripheral 0x4000 8000 - 0x4000 FFFF Reserved 0x4000 7C00 - 0x4000 7FFF UART8 0x4000 7800 - 0x4000 7BFF UART7 0x4000 7400 - 0x4000 77FF 0x4000 7000 - 0x4000 73FF 0x4000 6C00 - 0x4000 6FFF CAN3 0x4000 6800 - 0x4000 6BFF CAN2...
Page 62: Embedded Sram
RM0430 Embedded SRAM STM32F413/423 devices feature 320 Kbytes of system SRAM. The embedded SRAM can be accessed as bytes, half-words (16 bits) or full words (32 bits). Read and write operations are performed at CPU speed with 0 wait state. The embedded SRAM is divided into two blocks: •...
Page 63: Boot Configuration
RM0430 A mapping formula shows how to reference each word in the alias region to a corresponding bit in the bit-band region. The mapping formula is: bit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number × 4) where: – bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit –...
Page 64: Table 3. Embedded Bootloader Interfaces
CAN and USB OTG FS require an external clock (HSE) multiple of 1 MHz (ranging from 4 to 26 MHz). The embedded bootloader code is located in system memory. It is programmed by ST during production. For additional information, refer to application note AN2606.
Page 65: Table 4. Memory Mapping Vs. Boot Mode/Physical Remap In Stm32F413/423
RM0430 Table 4. Memory mapping vs. Boot mode/physical remap in STM32F413/423 Boot/Remap in main Boot/Remap in Boot/Remap in Addresses Flash memory embedded SRAM System memory 0x2000 0000 - 0x2003 FFFF SRAM (256 KB) SRAM (256KB) SRAM (256KB) 0x1FFF 0000 - 0x1FFF 77FF System memory System memory System memory...
Page 66: Embedded Flash Memory Interface
Embedded Flash memory interface RM0430 Embedded Flash memory interface Introduction The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms. The Flash memory interface accelerates code execution with a system of instruction prefetch and cache lines.
Page 67: Embedded Flash Memory
RM0430 Embedded Flash memory interface Embedded Flash memory The Flash memory has the following main features: • Capacity up to 1.5 Mbyte • 128 bits wide data read • Byte, half-word, word and double word write • Sector and mass erase •...
Page 68: Read Interface
Embedded Flash memory interface RM0430 Table 5. Flash module organization (continued) Block Name Block base addresses Size OTP area 0x1FFF 7800 - 0x1FFF 7A0F 528 byte Option bytes 0x1FFF C000 - 0x1FFF C00F 16 byte Read interface 3.4.1 Relation between CPU clock frequency and Flash memory read time To correctly read data from Flash memory, the number of wait states (LATENCY) must be correctly programmed in the Flash access control register (FLASH_ACR) according to the frequency of the CPU clock (HCLK) and the supply voltage of the device.
Page 69: Adaptive Real-Time Memory Accelerator (Art Accelerator™)
RM0430 Embedded Flash memory interface Increasing the CPU frequency Program the new number of wait states to the LATENCY bits in the FLASH_ACR register Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register Modify the CPU clock source by writing the SW bits in the RCC_CFGR register If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR...
Page 70: Figure 4. Sequential 32-Bit Instruction Execution
Embedded Flash memory interface RM0430 Figure 4 shows the execution of sequential 32-bit instructions with and without prefetch when 3 WSs are needed to access the Flash memory. Figure 4. Sequential 32-bit instruction execution 70/1324 RM0430 Rev 8...
Page 71: Erase And Program Operations
RM0430 Embedded Flash memory interface When the code is not sequential (branch), the instruction may not be present in the currently used instruction line or in the prefetched instruction line. In this case (miss), the penalty in terms of number of cycles is at least equal to the number of wait states. Instruction cache memory To limit the time lost due to jumps, it is possible to retain 64 lines of 128 bits in an instruction cache memory.
Page 72: Program/Erase Parallelism
Embedded Flash memory interface RM0430 Note: The FLASH_CR register is not accessible in write mode when the BSY bit in the FLASH_SR register is set. Any attempt to write to it with the BSY bit set will cause the AHB bus to stall until the BSY bit is cleared.
Page 73: Programming
RM0430 Embedded Flash memory interface Mass Erase To perform Mass Erase, the following sequence is recommended: Check that no Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register Set the MER bit in the FLASH_CR register Set the STRT bit in the FLASH_CR register Wait for the BSY bit to be cleared Note:...
Page 74: Interrupts
Embedded Flash memory interface RM0430 Programming and caches If a Flash memory write access concerns some data in the data cache, the Flash write access modifies the data in the Flash memory and the data in the cache. If an erase operation in Flash memory also concerns data in the data or instruction cache, you have to make sure that these data are rewritten before they are accessed during code execution.
Page 75: Table 10. Description Of The Option Bytes
RM0430 Embedded Flash memory interface Table 10. Description of the option bytes Option bytes (word, address 0x1FFF C000) RDP: Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0xAA: Level 0, no protection Bits 15:8 0xCC: Level 2, chip protection (debug and boot from RAM features disabled) Others: Level 1, read protection of memories (debug features limited)
Page 76: Programming User Option Bytes
Embedded Flash memory interface RM0430 Table 10. Description of the option bytes nWRP15_14: Non Write Protection of sector 15 and 14 If SPRMOD is reset (default value): 0: Write protection active on sector 15 and 14. Bit 14 1: Write protection not active on sector 15 and 14. If SPRMOD is set (active): 0: PCROP protection not active on sector 15 and 14.
Page 77 RM0430 Embedded Flash memory interface Flash memory are possible in all boot configurations (Flash user boot, debug or boot from RAM). • Level 1: read protection enabled It is the default read protection level after option byte erase. The read protection Level 1 is activated by writing any value (except for 0xAA and 0xCC used to set Level 0 and Level 2, respectively) into the RDP option byte.
Page 78: Write Protections
Embedded Flash memory interface RM0430 Table 11. Access versus read protection level Debug features, Boot from RAM or Booting from Flash memory Protection from System memory bootloader Memory area Level Read Write Erase Read Write Erase Level 1 Main Flash Memory Level 2 Level 1 Option Bytes...
Page 79: Proprietary Code Readout Protection (Pcrop)
RM0430 Embedded Flash memory interface If an erase/program operation to a write-protected part of the Flash memory is attempted (sector protected by write protection bit, OTP part locked or part of the Flash memory that can never be written like the ICP), the write protection error flag (WRPERR) is set in the FLASH_SR register.
Page 80: Figure 6. Pcrop Levels
Embedded Flash memory interface RM0430 Figure 6. PCROP levels The deactivation of the SPRMOD and/or the unprotection of PCROPed user sectors can only occur when, at the same time, the RDP level changes from 1 to 0. If this condition is not respected, the user option byte modification is canceled and the write error WRPERR flag is set.
Page 81: One-Time Programmable Bytes
RM0430 Embedded Flash memory interface One-time programmable bytes Table 12 shows the organization of the one-time programmable (OTP) part of the OTP area. Table 12. OTP area organization Block [128:96] [95:64] [63:32] [31:0] Address byte 0 OTP0 OTP0 OTP0 OTP0 0x1FFF 7800 OTP0 OTP0...
Page 82: Flash Interface Registers
Embedded Flash memory interface RM0430 Flash interface registers 3.8.1 Flash access control register (FLASH_ACR) The Flash access control register is used to enable/disable the acceleration features and control the Flash memory access time according to CPU frequency. Address offset: 0x00 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Res.
Page 83: Flash Key Register (Flash_Keyr)
RM0430 Embedded Flash memory interface 3.8.2 Flash key register (FLASH_KEYR) The Flash key register is used to allow access to the Flash control register and so, to allow program and erase operations. Address offset: 0x04 Reset value: 0x0000 0000 Access: no wait state, word access KEY[31:16] KEY[15:0] Bits 31:0 FKEYR: FPEC key...
Page 84: Flash Status Register (Flash_Sr)
Embedded Flash memory interface RM0430 3.8.4 Flash status register (FLASH_SR) The Flash status register gives information on ongoing program and erase operations. Address offset: 0x0C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Res. Res. Res.
Page 85: Flash Control Register (Flash_Cr)
RM0430 Embedded Flash memory interface Bits 3:2 Reserved, must be kept cleared. Bit 1 OPERR: Operation error Set by hardware when a flash operation (programming / erase /read) request is detected and can not be run because of parallelism, alignment, or write protection error. This bit is set only if error interrupts are enabled (ERRIE = 1).
Page 86: Flash Option Control Register (Flash_Optcr)
Embedded Flash memory interface RM0430 Bits 9:8 PSIZE: Program size These bits select the program parallelism. 00 program x8 01 program x16 10 program x32 11 program x64 Bit 7 Reserved, must be kept cleared. Bits 6:3 SNB: Sector number These bits select the sector to erase.
Page 87 RM0430 Embedded Flash memory interface Bit 31 SPRMOD: Selection of Protection Mode of nWPRi bits 0: PCROP disabled, nWPRi bits used for Write Protection on sector i 1: PCROP enabled, nWPRi bits used for PCROP Protection on sector i Bit 30 nWRP14_15: Not write protect This bit contains the value of the write-protection option byte of sectors 14 and 15.
Page 88 Embedded Flash memory interface RM0430 Bits 3:2 BOR_LEV: BOR reset Level These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level. By default, BOR is off. When the supply voltage (V drops below the selected BOR level, a device reset is generated.
Page 89: Flash Interface Register Map
RM0430 Embedded Flash memory interface 3.8.7 Flash interface register map Table 13. Flash register map and reset values Offset Register FLASH_ACR LATENCY 0x00 Reset value FLASH_KEYR KEY[31:16] KEY[15:0] 0x04 Reset value 0 0 0 FLASH_ OPTKEYR[31:16] OPTKEYR[15:0] OPTKEYR 0x08 Reset value 0 0 0 FLASH_SR 0x0C...
Page 90: Crc Calculation Unit
CRC calculation unit RM0430 CRC calculation unit CRC introduction The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity.
Page 91: Crc Registers
RM0430 CRC calculation unit Each write operation into the data register creates a combination of the previous CRC value and the new one (CRC computation is done on the whole 32-bit data word, and not byte per byte). The write operation is stalled until the end of the CRC computation, thus allowing back-to- back write accesses or consecutive write and read accesses.
Page 92: Independent Data Register (Crc_Idr)
CRC calculation unit RM0430 4.4.2 Independent data register (CRC_IDR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. IDR[7:0] Bits 31:8 Reserved, must be kept at reset value.
Page 93: Crc Register Map
RM0430 CRC calculation unit 4.4.4 CRC register map Table 14. CRC calculation unit register map and reset values Offset Register CRC_DR Data register 0x00 Reset value 0xFFFF FFFF CRC_IDR Independent data register 0x04 Reset value 0x0000 CRC_CR 0x08 Reset value RM0430 Rev 8 93/1324...
Page 94: Power Controller (Pwr)
Power controller (PWR) RM0430 Power controller (PWR) Power supplies There are two main power supply schemes: • VDD = 1.7 to 3.6 V: external power supply for I/Os with the internal regulator disabled, provided externally through VDD pins. Requires the use of an external power supply supervisor connected to the VDD and PDR_ON pins.
Page 95: Independent A/D Converter Supply And Reference Voltage
RM0430 Power controller (PWR) Figure 8. Power supply overview 1. V and V must be connected to V and V , respectively. 5.1.1 Independent A/D converter supply and reference voltage To improve conversion accuracy, the ADC has an independent power supply which can be separately filtered and shielded from noise on the PCB.
Page 96 Power controller (PWR) RM0430 To allow the RTC to operate even when the main digital supply (V ) is turned off, the V pin powers the following blocks: • The RTC • The LSE oscillator • PC13 to PC15 I/Os The switch to the V supply is controlled by the power-down reset embedded in the Reset block.
Page 97: Voltage Regulator
RM0430 Power controller (PWR) Backup domain access After reset, the backup domain (RTC registers, and RTC backup register) is protected against possible unwanted write accesses. To enable access to the backup domain, proceed as follows: • Access to the RTC and RTC backup registers Enable the power interface clock by setting the PWREN bits in the RCC_APB1ENR register (see Section 6.3.14: RCC AHB3 peripheral clock enable register...
Page 98: Power Supply Supervisor
Power controller (PWR) RM0430 Note: For more details, refer to the voltage regulator section in the STM32F413/423 datasheet. Power supply supervisor 5.2.1 Power-on reset (POR)/power-down reset (PDR) The device has an integrated POR/PDR circuitry that allows proper operation starting from 1.8 V. To use the device below 1.8 V, the internal power supervisor must be switched off using the PDR_ON pin (please refer to section Power supply supervisor of the STM32F413/423 datasheet).
Page 99: Programmable Voltage Detector (Pvd)
RM0430 Power controller (PWR) When the supply voltage (V ) drops below the selected V threshold, a device reset is generated. The BOR can be disabled by programming the device option bytes. In this case, the power-on and power-down is then monitored by the POR/ PDR or by an external power supervisor if the PDR is switched off through the PDR_ON pin (see Section 5.2.1: Power-on reset (POR)/power-down reset...
Page 100: Low-Power Modes
Power controller (PWR) RM0430 Figure 11. PVD thresholds Low-power modes By default, the microcontroller is in Run mode after a system or a power-on reset. In Run mode the CPU is clocked by HCLK and the program code is executed. Several low-power modes are available to save power when the CPU does not need to be kept running, for example when waiting for an external event.
Page 101 RM0430 Power controller (PWR) Exiting low-power mode The MCU exits from Sleep and Stop modes low-power mode depending on the way the low- power mode was entered: • If the WFI instruction or Return from ISR was used to enter the low-power mode, any peripheral interrupt acknowledged by the NVIC can wake up the device.
Page 102: Slowing Down System Clocks
Power controller (PWR) RM0430 Only enabled NVIC interrupts with sufficient priority will wakeup and interrupt the MCU. Table 15. Low-power mode summary Effect on Effect on 1.2 V Mode name Entry Wakeup Voltage regulator domain clocks domain clocks WFI or Return Sleep and Any interrupt CPU CLK OFF...
Page 103: Sleep Mode
RM0430 Power controller (PWR) 5.3.3 Sleep mode Entering Sleep mode The Sleep mode is entered according to Entering low-power mode, when the SLEEPDEEP ® bit in the Cortex -M4 with FPU System Control register is cleared. Refer to Table 16 Table 17 for details on how to enter Sleep mode.
Page 104: Batch Acquisition Mode
Power controller (PWR) RM0430 Table 17. Sleep-on-exit entry and exit (continued) Sleep-on-exit Description Mode exit Interrupt: refer to Table 40: Vector table for STM32F413/423 Wakeup latency None 5.3.4 Batch acquisition mode Entering BAM The BAM is entered according to Section : Entering low-power mode, when the ®...
Page 105: Stop Mode
RM0430 Power controller (PWR) Table 19. BAM-on-exit entry and exit Sleep-on-exit Description Set the Flash memory in low-power mode: – FISSR/FMSSR and FPDS bits of the PWR_CR register WFI (wait for interrupt) while: Mode entry – SLEEPDEEP = 0 and –...
Page 106: Table 20. Stop Operating Modes
Power controller (PWR) RM0430 Table 20. Stop operating modes Stop mode MRLV bit LPLV bit FPDS bit LPDS bit Wakeup latency STOP MR HSI RC startup time HSI RC startup time + STOP MRFPD Flash wakeup time from Deep Power Down mode HSI RC startup time + STOP LP regulator wakeup time from LP...
Page 107: Table 21. Stop Mode Entry And Exit
RM0430 Power controller (PWR) Section 23.3 Section 23: Window watchdog (WWDG). • Real-time clock (RTC): this is configured by the RTCEN bit in the Section 6.3.23: RCC Backup domain control register (RCC_BDCR) • Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Section 6.3.24: RCC clock control &...
Page 108: Standby Mode
Power controller (PWR) RM0430 Table 21. Stop mode entry and exit Stop mode Description If WFI or Return from ISR was used for entry: Any EXTI lines configured in Interrupt mode (the corresponding EXTI Interrupt vector must be enabled in the NVIC). The interrupt source can be external interrupts or peripherals with wakeup capability.
Page 109: Programming The Rtc Alternate Functions To Wake Up The Device From The Stop And Standby Modes
RM0430 Power controller (PWR) Refer to Table 22 for more details on how to exit Standby mode. Table 22. Standby mode entry and exit Standby mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: ® – SLEEPDEEP is set in Cortex -M4 with FPU System Control register, –...
Page 110 Power controller (PWR) RM0430 These RTC alternate functions can wake up the system from the Stop and Standby low- power modes. The system can also wake up from low-power modes without depending on an external interrupt (Auto-wakeup mode), by using the RTC alarm or the RTC wakeup events. The RTC provides a programmable time base for waking up from the Stop or Standby mode at regular intervals.
Page 111 RM0430 Power controller (PWR) Configure the RTC to detect the tamper or time stamp event • To wake up the device from the Standby mode with an RTC wakeup event, it is necessary to: Enable the RTC wakeup interrupt in the RTC_CR register Configure the RTC to generate the RTC wakeup event Safe RTC alternate function wakeup flag clearing sequence If the selected RTC alternate function is set before the PWR wakeup flag (WUTF) is cleared,...
Page 112: Power Control Registers
Power controller (PWR) RM0430 Power control registers 5.4.1 PWR power control register (PWR_CR) Address offset: 0x00 Reset value: 0x0000 8000 (reset by wakeup from Standby mode) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FISSR FMSSR Res. Res. Res.
Page 113 RM0430 Power controller (PWR) Bit 12 Reserved, must be kept at reset value. Bit 11 MRLVDS: Main regulator Low Voltage in Deep Sleep 0: Main regulator in Voltage scale 3 when the device is in Stop mode. 1: Main regulator in Low Voltage and Flash memory in Deep Sleep mode when the device is in Stop mode.
Page 114: Pwr Power Control/Status Register (Pwr_Csr)
Power controller (PWR) RM0430 Bit 1 PDDS: Power-down deepsleep This bit is set and cleared by software. It works together with the LPDS bit. 0: Enter Stop mode when the CPU enters deepsleep. The regulator status depends on the LPDS bit. 1: Enter Standby mode when the CPU enters deepsleep.
Page 115 RM0430 Power controller (PWR) Bit 7 EWUP2: Enable WKUP2 pin (PC0) This bit is set and cleared by software. 0: WKUP2 pin is used for general purpose I/O. An event on the WKUP2 pin does not wakeup the device from Standby mode. 1: WKUP2 pin is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP2 pin wakes-up the system from Standby mode).
Page 116: Pwr Register Map
Power controller (PWR) RM0430 PWR register map The following table summarizes the PWR registers. Table 23. PWR - register map and reset values Offset Register PWR_CR PLS[2:0] 0x000 Reset value PWR_CSR 0x004 Reset value Refer to Section 2.2.2 on page 58 for the register boundary addresses.
Page 117: Reset And Clock Control (Rcc) For Stm32F413/423
RM0430 Reset and clock control (RCC) for STM32F413/423 Reset and clock control (RCC) for STM32F413/423 Reset There are three types of reset, defined as system Reset, power Reset and backup domain Reset. 6.1.1 System reset A system reset sets all registers to their reset values except the reset flags in the clock controller CSR register and the registers in the Backup domain.
Page 118: Power Reset
In this case, whenever a Stop mode entry sequence is successfully executed, the device is reset instead of entering the Stop mode. For further information on the user option bytes, refer to the STM32F413/423 Flash programming manual available from your ST sales office. 6.1.2 Power reset...
Page 119: Backup Domain Reset
RM0430 Reset and clock control (RCC) for STM32F413/423 6.1.3 Backup domain reset The backup domain reset sets all RTC registers and the RCC_BDCR register to their reset values. A backup domain reset is generated when one of the following events occurs: Software reset, triggered by setting the BDRST bit in the RCC Backup domain control register...
Page 120: Figure 13. Clock Tree
Reset and clock control (RCC) for STM32F413/423 RM0430 Figure 13. Clock tree 1. For full details about the internal and external clock source characteristics, refer to the Electrical characteristics section in the device datasheet. 120/1324 RM0430 Rev 8...
Page 121: Hse Clock
RM0430 Reset and clock control (RCC) for STM32F413/423 The clock controller provides a high degree of flexibility to the application in the choice of the external crystal or the oscillator to run the core and peripherals at the highest frequency and, guarantee the appropriate frequency for peripherals that need a specific clock like USB OTG FS, I2S and SDIO.
Page 122: Hsi Clock
Reset and clock control (RCC) for STM32F413/423 RM0430 Figure 14. HSE/ LSE clock sources Hardware configuration OSC_OUT External clock (HI-Z) External source OSC_IN OSC_OUT Crystal/ceramic resonators Load capacitors External source (HSE bypass) In this mode, an external clock source must be provided. You select this mode by setting the HSEBYP and HSEON bits in the RCC clock control register (RCC_CR).
Page 123: Pll Configuration
Calibration RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at T = 25 °C. After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the...
Page 124: Lsi Clock
Reset and clock control (RCC) for STM32F413/423 RM0430 The LSE oscillator is switched on and off using the LSEON bit in RCC Backup domain control register (RCC_BDCR). The LSERDY flag in the RCC Backup domain control register (RCC_BDCR) indicates if the LSE crystal is stable or not.
Page 125: Rtc/Awu Clock
RM0430 Reset and clock control (RCC) for STM32F413/423 CSS interrupt in the NMI ISR by setting the CSSC bit in the Clock interrupt register (RCC_CIR). If the HSE oscillator is used directly or indirectly as the system clock (indirectly meaning that it is directly used as PLL input clock, and that PLL clock is the system clock) and a failure is detected, then the system clock switches to the HSI oscillator and the HSE oscillator is disabled.
Page 126: Clock-Out Capability
Reset and clock control (RCC) for STM32F413/423 RM0430 6.2.10 Clock-out capability Two microcontroller clock output (MCO) pins are available: • MCO1 You can output four different clock sources onto the MCO1 pin (PA8) using the configurable prescaler (from 1 to 5): –...
Page 127: Figure 15. Frequency Measurement With Tim5 In Input Capture Mode
RM0430 Reset and clock control (RCC) for STM32F413/423 The basic concept consists in providing a relative measurement (e.g. HSI/LSE ratio): the precision is therefore tightly linked to the ratio between the two clock sources. The greater the ratio, the better the measurement. It is also possible to measure the LSI frequency: this is useful for applications that do not have a crystal.
Page 128: Figure 16. Frequency Measurement With Tim11 In Input Capture Mode
Reset and clock control (RCC) for STM32F413/423 RM0430 Internal/external clock measurement using TIM11 channel1 TIM11 has an input multiplexer which allows choosing whether the input capture is triggered by the I/O or by an internal clock. This selection is performed through TI1_RMP [1:0] bits in the TIM11_OR register.
Page 129: Rcc Registers
RM0430 Reset and clock control (RCC) for STM32F413/423 RCC registers Refer to Section 1.2: List of abbreviations for registers for a list of abbreviations used in register descriptions. 6.3.1 RCC clock control register (RCC_CR) Address offset: 0x00 Reset value: 0x0000 XX81 where X is undefined. Access: no wait state, word, half-word and byte access PLLI2S PLLI2S...
Page 130 Reset and clock control (RCC) for STM32F413/423 RM0430 Bit 18 HSEBYP: HSE clock bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled.
Page 131: Rcc Pll Configuration Register (Rcc_Pllcfgr)
RM0430 Reset and clock control (RCC) for STM32F413/423 6.3.2 RCC PLL configuration register (RCC_PLLCFGR) Address offset: 0x04 Reset value: 0x2400 3010 Access: no wait state, word, half-word and byte access. This register is used to configure the PLL clock outputs according to the formulas: •...
Page 132 Reset and clock control (RCC) for STM32F413/423 RM0430 Bit 22 PLLSRC: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source Set and cleared by software to select PLL and PLLI2S clock source. This bit can be written only when PLL and PLLI2S are disabled. 0: HSI clock selected as PLL and PLLI2S clock entry 1: HSE oscillator clock selected as PLL and PLLI2S clock entry Bits 21:18 Reserved, must be kept at reset value.
Page 133: Rcc Clock Configuration Register (Rcc_Cfgr)
RM0430 Reset and clock control (RCC) for STM32F413/423 Bits 5:0 PLLM[5:0]: Division factor for the main PLL (PLL) input clock Set and cleared by software to divide the PLL and PLLI2S input clock before the VCO. These bits can be written only when the PLL and PLLI2S are disabled. Caution: The software has to set these bits correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz.
Page 134 Reset and clock control (RCC) for STM32F413/423 RM0430 Bits 29:27 MCO2PRE[1:0]: MCO2 prescaler Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset before enabling the external oscillators and the PLLs.
Page 135 RM0430 Reset and clock control (RCC) for STM32F413/423 Bits 12:10 PPRE1[2:0]: APB Low speed prescaler (APB1) Set and cleared by software to control APB low-speed clock division factor. Caution: The software has to set these bits correctly not to exceed 50 MHz on this domain. The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after PPRE1 write.
Page 136: Rcc Clock Interrupt Register (Rcc_Cir)
Reset and clock control (RCC) for STM32F413/423 RM0430 6.3.4 RCC clock interrupt register (RCC_CIR) Address offset: 0x0C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access PLLI2S Res. Res. Res. Res. Res. Res. Res. Res. CSSC Res.
Page 137 RM0430 Reset and clock control (RCC) for STM32F413/423 Bits 15:14 Reserved, must be kept at reset value. Bit 13 PLLI2SRDYIE: PLLI2S ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLLI2S lock. 0: PLLI2S lock interrupt disabled 1: PLLI2S lock interrupt enabled Bit 12 PLLRDYIE: Main PLL (PLL) ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL lock.
Page 138: Rcc Ahb1 Peripheral Reset Register (Rcc_Ahb1Rstr)
Reset and clock control (RCC) for STM32F413/423 RM0430 Bit 3 HSERDYF: HSE ready interrupt flag Set by hardware when External High Speed clock becomes stable and HSERDYDIE is set. Cleared by software setting the HSERDYC bit. 0: No clock ready interrupt caused by the HSE oscillator 1: Clock ready interrupt caused by the HSE oscillator Bit 2 HSIRDYF: HSI ready interrupt flag Set by hardware when the Internal High Speed clock becomes stable and HSIRDYDIE is...
Page 139 RM0430 Reset and clock control (RCC) for STM32F413/423 Bit 12 CRCRST: CRC reset Set and cleared by software. 0: does not reset CRC 1: resets CRC Bits 11:8 Reserved, must be kept at reset value. Bit 7 GPIOHRST: IO port H reset Set and cleared by software.
Page 140: Rcc Ahb2 Peripheral Reset Register (Rcc_Ahb2Rstr)
Reset and clock control (RCC) for STM32F413/423 RM0430 6.3.6 RCC AHB2 peripheral reset register (RCC_AHB2RSTR) for STM32F413xx Address offset: 0x14 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res. Res.
Page 141: Rcc Ahb2 Peripheral Reset Register (Rcc_Ahb2Rstr)
RM0430 Reset and clock control (RCC) for STM32F413/423 6.3.7 RCC AHB2 peripheral reset register (RCC_AHB2RSTR) for STM32F423xx Address offset: 0x14 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res. Res.
Page 142: Rcc Ahb3 Peripheral Reset Register (Rcc_Ahb3Rstr)
Reset and clock control (RCC) for STM32F413/423 RM0430 6.3.8 RCC AHB3 peripheral reset register (RCC_AHB3RSTR) Address offset: 0x18 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 143 RM0430 Reset and clock control (RCC) for STM32F413/423 Bit 31 UART8RST: UART 8 reset Set and reset by software. 0: does not reset UART 8 1: resets the UART 8 Bit 30 UART7RST: UART 7 reset Set and reset by software. 0: does not reset UART 7 1: resets the UART 7 Bit 29 DACRST: DAC reset...
Page 144 Reset and clock control (RCC) for STM32F413/423 RM0430 Bit 20 UART5RST: UART5 reset Set and reset by software. 0: does not reset UART5 1: resets UART5 Bit 19 UART4RST: UART4 reset Set and reset by software. 0: does not reset UART4 1: resets UART4 Bit 18 USART3RST: USART3 reset Set and cleared by software.
Page 145 RM0430 Reset and clock control (RCC) for STM32F413/423 Bit 6 TIM12RST: TIM12 reset Set and cleared by software. 0: does not reset TIM12 1: resets TIM12 Bit 5 TIM7RST: TIM7 reset Set and cleared by software. 0: does not reset TIM7 1: resets TIM7 Bit 4 TIM6RST: TIM6 reset Set and cleared by software.
Page 146: Rcc Apb2 Peripheral Reset Register (Rcc_Apb2Rstr)
Reset and clock control (RCC) for STM32F413/423 RM0430 6.3.10 RCC APB2 peripheral reset register (RCC_APB2RSTR) Address offset: 0x24 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. SPI5 TIM11 TIM10 TIM9 DFSDM2 DFSDM1 SAI1 Res. Res. Res.
Page 147 RM0430 Reset and clock control (RCC) for STM32F413/423 Bit 15 Reserved, must be kept at reset value. Bit 14 SYSCFGRST: System configuration controller reset Set and cleared by software. 0: does not reset the System configuration controller 1: resets the System configuration controller Bit 13 SPI4RST: SPI4 reset Set and reset by software.
Page 148 Reset and clock control (RCC) for STM32F413/423 RM0430 Bits 3:2 Reserved, must be kept at reset value. Bit 1 TIM8RST: TIM8 reset Set and cleared by software. 0: does not reset TIM8 1: resets TIM8 Bit 0 TIM1RST: TIM1 reset Set and cleared by software.
Page 149: Rcc Ahb1 Peripheral Clock Enable Register (Rcc_Ahb1Enr)
RM0430 Reset and clock control (RCC) for STM32F413/423 6.3.11 RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) Address offset: 0x30 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 150 Reset and clock control (RCC) for STM32F413/423 RM0430 Bit 3 GPIODEN: IO port D clock enable Set and cleared by software. 0: IO port D clock disabled 1: IO port D clock enabled Bit 2 GPIOCEN: IO port C clock enable Set and cleared by software.
Page 151: Rcc Ahb2 Peripheral Clock Enable Register (Rcc_Ahb2Enr)
RM0430 Reset and clock control (RCC) for STM32F413/423 6.3.12 RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) for STM32F413xx Address offset: 0x34 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. Res. Res. Res. Res. Res. Res. Res.
Page 152: Rcc Ahb2 Peripheral Clock Enable Register (Rcc_Ahb2Enr)
Reset and clock control (RCC) for STM32F413/423 RM0430 6.3.13 RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) for STM32F423xx Address offset: 0x34 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. Res. Res. Res. Res. Res. Res. Res.
Page 153: Rcc Ahb3 Peripheral Clock Enable Register (Rcc_Ahb3Enr)
RM0430 Reset and clock control (RCC) for STM32F413/423 6.3.14 RCC AHB3 peripheral clock enable register (RCC_AHB3ENR) Address offset: 0x38 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 154 Reset and clock control (RCC) for STM32F413/423 RM0430 Bit 31 UART8EN: UART8 clock enable Set and reset by software. 0: UART8 clock disabled 1: UART8 clock enable Bit 30 UART7EN: UART7 clock enable Set and reset by software. 0: UART7 clock disabled 1: UART7 clock enable Bit 29 DACEN: DAC clock enable Set and reset by software.
Page 155 RM0430 Reset and clock control (RCC) for STM32F413/423 Bit 20 UART5EN: UART 5 clock enable Set and RESET by software. 0: UART 5 clock disabled 1: UART 5 clock enabled Bit 19 UART4EN: UART 4 clock enable Set and cleared by software. 0: UART 4 clock disabled 1: UART 4 clock enabled Bit 18 USART3EN: USART3 clock enable...
Page 156 Reset and clock control (RCC) for STM32F413/423 RM0430 Bit 6 TIM12EN: TIM12 reset Set and cleared by software. 0: does not reset TIM12 1: resets TIM12 Bit 5 TIM7EN: TIM7 reset Set and cleared by software. 0: does not reset TIM7 1: resets TIM7 Bit 4 TIM6EN: TIM6 reset Set and cleared by software.
Page 157: Rcc Apb2 Peripheral Clock Enable Register (Rcc_Apb2Enr)
RM0430 Reset and clock control (RCC) for STM32F413/423 6.3.16 RCC APB2 peripheral clock enable register (RCC_APB2ENR) Address offset: 0x44 Reset value: 0x0000 8000 Access: no wait state, word, half-word and byte access. TIM11 TIM10 TIM9 DFSDM2 DFSDM1 SAI1 SPI5 Res. Res.
Page 158 Reset and clock control (RCC) for STM32F413/423 RM0430 Bit 16 TIM9EN: TIM9 clock enable Set and cleared by software. 0: TIM9 clock disabled 1: TIM9 clock enabled Bit 15 EXITEN: Extit Apb sysctrl pfree clock enable Set and cleared by software. 0: Extit Apb sysctrl pfree clock disabled 1: Extit Apb sysctrl pfree clock enabled Bit 14 SYSCFGEN: System configuration controller clock enable...
Page 159 RM0430 Reset and clock control (RCC) for STM32F413/423 Bits 3:2 Reserved, must be kept at reset value. Bit 1 TIM8EN: TIM8 clock enable Set and cleared by software. 0: TIM8 clock disabled 1: TIM8 clock enabled Bit 0 TIM1EN: TIM1 clock enable Set and cleared by software.
Page 160: Rcc Ahb1 Peripheral Clock Enable In Low Power Mode Register (Rcc_Ahb1Lpenr)
Reset and clock control (RCC) for STM32F413/423 RM0430 6.3.17 RCC AHB1 peripheral clock enable in low power mode register (RCC_AHB1LPENR) Address offset: 0x50 Reset value: 0x0063 90FF Access: no wait state, word, half-word and byte access. DMA2 DMA1 SRAM2 SRAM1 Res.
Page 161 RM0430 Reset and clock control (RCC) for STM32F413/423 Bit 7 GPIOHLPEN: IO port H clock enable during sleep mode Set and reset by software. 0: IO port H clock disabled during sleep mode 1: IO port H clock enabled during sleep mode Bit 6 GPIOGLPEN: IO port G clock enable during Sleep mode Set and cleared by software.
Page 162: Rcc Ahb2 Peripheral Clock Enable In Low Power Mode Register (Rcc_Ahb2Lpenr) For Stm32F413Xx
Reset and clock control (RCC) for STM32F413/423 RM0430 6.3.18 RCC AHB2 peripheral clock enable in low power mode register (RCC_AHB2LPENR) for STM32F413xx Address offset: 0x54 Reset value: 0x0000 00C0 Access: no wait state, word, half-word and byte access. Res. Res. Res.
Page 163: Rcc Ahb2 Peripheral Clock Enable In Low Power Mode Register (Rcc_Ahb2Lpenr) For Stm32F423Xx
RM0430 Reset and clock control (RCC) for STM32F413/423 6.3.19 RCC AHB2 peripheral clock enable in low power mode register (RCC_AHB2LPENR) for STM32F423xx Address offset: 0x54 Reset value: 0x0000 00D0 Access: no wait state, word, half-word and byte access. Res. Res. Res.
Page 164 Reset and clock control (RCC) for STM32F413/423 RM0430 Bits 31:2 Reserved, must be kept at reset value. Bit 1 QSPILPEN: QUADSPI memory controller module clock enable during Sleep mode Set and cleared by software. 0: QUADSPI module clock disabled during Sleep mode 1: QUADSPI module clock enabled during Sleep mode Bit 0 FSMCLPEN: Flexible memory controller module clock enable during Sleep mode Set and cleared by software.
Page 165: Rcc Apb1 Peripheral Clock Enable In Low Power Mode Register (Rcc_Apb1Lpenr)
RM0430 Reset and clock control (RCC) for STM32F413/423 6.3.21 RCC APB1 peripheral clock enable in low power mode register (RCC_APB1LPENR) Address offset: 0x60 Reset value: 0xFFFF CFFF Access: no wait state, word, half-word and byte access. CAN2 CAN1 I2C3 I2C2 I2C1 USART3 USART2...
Page 166 Reset and clock control (RCC) for STM32F413/423 RM0430 Bit 23 I2C3LPEN: I2C3 clock enable during Sleep mode Set and cleared by software. 0: I2C3 clock disabled during Sleep mode 1: I2C3 clock enabled during Sleep mode Bit 22 I2C2LPEN: I2C2 clock enable during Sleep mode Set and cleared by software.
Page 167 RM0430 Reset and clock control (RCC) for STM32F413/423 Bit 9 LPTIMER1LPEN: TIM14 clock enable during Sleep mode Set and cleared by software. 0: LPTimer 1 clock disabled during Sleep mode 1: LPTimer 1 clock enabled during Sleep mode Bit 8 TIM14LPEN: TIM14 clock enable during Sleep mode Set and cleared by software.
Page 168: Rcc Apb2 Peripheral Clock Enabled In Low Power Mode Register (Rcc_Apb2Lpenr)
Reset and clock control (RCC) for STM32F413/423 RM0430 6.3.22 RCC APB2 peripheral clock enabled in low power mode register (RCC_APB2LPENR) Address offset: 0x64 Reset value: 0x0317 F9F3h Access: no wait state, word, half-word and byte access. SPI5 TIM11 TIM10 TIM9 DFSDM2 DFSDM1 SAI1...
Page 169 RM0430 Reset and clock control (RCC) for STM32F413/423 Bit 16 TIM9LPEN: TIM9 clock enable during sleep mode Set and cleared by software. 0: TIM9 clock disabled during Sleep mode 1: TIM9 clock enabled during Sleep mode Bit 15 EXTITLPEN: EXTIT APB and SYSCTRL PFREE clock enable during Sleep mode Set and cleared by software.
Page 170 Reset and clock control (RCC) for STM32F413/423 RM0430 Bits 3:2 Reserved, must be kept at reset value. Bit 1 TIM8LPEN: TIM8 clock enable during Sleep mode Set and cleared by software. 0: TIM8 clock disabled during Sleep mode 1: TIM8 clock enabled during Sleep mode Bit 0 TIM1LPEN: TIM1 clock enable during Sleep mode Set and cleared by software.
Page 171: Rcc Backup Domain Control Register (Rcc_Bdcr)
RM0430 Reset and clock control (RCC) for STM32F413/423 6.3.23 RCC Backup domain control register (RCC_BDCR) Address offset: 0x70 Reset value: 0x0000 0000, reset by Backup domain reset. Access: 0 wait state 3, word, half-word and byte access ≤ ≤ Wait states are inserted in case of successive accesses to this register. The LSEON, LSEBYP, RTCSEL and RTCEN bits in the RCC Backup domain control register (RCC_BDCR)
Page 172: Rcc Clock Control & Status Register (Rcc_Csr)
Reset and clock control (RCC) for STM32F413/423 RM0430 Bit 2 LSEBYP: External low-speed oscillator bypass Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the LSE clock is disabled. 0: LSE oscillator not bypassed 1: LSE oscillator bypassed Bit 1 LSERDY: External low-speed oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable.
Page 173 RM0430 Reset and clock control (RCC) for STM32F413/423 Bit 28 SFTRSTF: Software reset flag Set by hardware when a software reset occurs. Cleared by writing to the RMVF bit. 0: No software reset occurred 1: Software reset occurred Bit 27 PORRSTF: POR/PDR reset flag Set by hardware when a POR/PDR reset occurs.
Page 174: Rcc Spread Spectrum Clock Generation Register (Rcc_Sscgr)
Reset and clock control (RCC) for STM32F413/423 RM0430 6.3.25 RCC spread spectrum clock generation register (RCC_SSCGR) Address offset: 0x80 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. The spread spectrum clock generation is available only for the main PLL. The RCC_SSCGR register must be written either before the main PLL is enabled or after the main PLL disabled.
Page 175: Rcc Plli2S Configuration Register (Rcc_Plli2Scfgr)
RM0430 Reset and clock control (RCC) for STM32F413/423 6.3.26 RCC PLLI2S configuration register (RCC_PLLI2SCFGR) Address offset: 0x84 Reset value: 0x2400 3010 Access: no wait state, word, half-word and byte access. This register is used to configure the PLLI2S clock outputs according to the formulas: •...
Page 176 Reset and clock control (RCC) for STM32F413/423 RM0430 Bit 22 PLLI2SSRC: PLLI2S entry clock source Set and cleared by software to select PLLI2S clock source. This bit can be written only when PLLI2S is disabled. 0: HSE or HSI depending on PLLSRC of PLLCFGR 1: external AFI clock (CK_I2S_EXT) selected as PLL clock entry Bits 21:15 Reserved, must be kept at reset value.
Page 177: Rcc Dedicated Clocks Configuration Register (Rcc_Dckcfgr)
RM0430 Reset and clock control (RCC) for STM32F413/423 6.3.27 RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR) Address offset: 0x8C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. CKDFSD Res. Res. I2S2RC[1:0] I2S1RC[1:0] TIMPRE SAI1BSRC SAI1ASRC Res. Res.
Page 178 Reset and clock control (RCC) for STM32F413/423 RM0430 Bits 23:22 SAII1BSRC: SAI1 B clock selection Set and reset by software. 00: PLLI2S_R divided (R2) as SAI1 B clock 01: I2S_CLIN as SAI1 B clock 00: PLL_R divided (R1) as SAI1 B clock 11: HS_CK as SAI1 B clock Bits 21:20 SAII1ASRC: SAI1 A clock selection Set and reset by software.
Page 179: Rcc Clocks Gated Enable Register (Ckgatenr)
RM0430 Reset and clock control (RCC) for STM32F413/423 6.3.28 RCC clocks gated enable register (CKGATENR) Address offset: 0x90 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. This register allows to enable or disable the clock gating for the specified IPs. Res.
Page 180: Rcc Dedicated Clocks Configuration Register (Rcc_Dckcfgr2)
Reset and clock control (RCC) for STM32F413/423 RM0430 6.3.29 RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR2) Address offset: 0x94 Reset value: 0x0000 0000 This register allows to enable or disable the clock gating for the specified IPs. LPTIMER1 SDIO CK48M I2CFMP1 Res.
Page 181: Rcc Register Map
RM0430 Reset and clock control (RCC) for STM32F413/423 6.3.30 RCC register map Table 24 gives the register map and reset values Table 24. RCC register map and reset values for STM32F413/423 Addr. Register offset name RCC_ 0x00 HSICAL[7:0] HSITRIM[4:0] RCC_ 0x04 PLLR[2:0] PLLQ[3:0]...
Page 182 Reset and clock control (RCC) for STM32F413/423 RM0430 Table 24. RCC register map and reset values for STM32F413/423 (continued) Addr. Register offset name RCC_ 0x38 AHB3ENR 0x3C Reserved RCC_ 0x40 APB1ENR RCC_ 0x44 APB2ENR 0x48 Reserved 0x4C Reserved RCC_ 0x50 AHB1LPENR RCC_ 0x54...
Page 183 RM0430 Reset and clock control (RCC) for STM32F413/423 Table 24. RCC register map and reset values for STM32F413/423 (continued) Addr. Register offset name RCC_ 0x80 INCSTEP[14:0] MODPER[11:0] SSCGR RCC_ 0x84 PLLI2SN[8:0]] PLLI2SM[5:0] PLLI2SCFGR 0x88 Reserved RCC_ 0x8C PLLDIVR[4:0]] PLLI2SDIVR[4:0]] DCKCFGR 0x90 CKGATENR RCC_...
Page 184: General-Purpose I/Os (Gpio)
General-purpose I/Os (GPIO) RM0430 General-purpose I/Os (GPIO) GPIO introduction Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers (GPIOx_IDR and GPIOx_ODR), a 32-bit set/reset register (GPIOx_BSRR), a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function selection register (GPIOx_AFRH and GPIOx_AFRL).
Page 185: Table 25. Port Bit Configuration Table
RM0430 General-purpose I/Os (GPIO) Figure 17 show the basic structure of a 5 V tolerant I/O port bit. Table 25 gives the possible port bit configurations. Figure 17. Basic structure of a five-volt tolerant I/O port bit 1. V is a potential specific to five-volt tolerant I/Os and different from V DD_FT Table 25.
Page 186: General-Purpose I/O (Gpio)
General-purpose I/Os (GPIO) RM0430 Table 25. Port bit configuration table (continued) MODER(i) OSPEEDR(i) PUPDR(i) OTYPER(i) I/O configuration [1:0] [B:A] [1:0] PP + PU PP + PD Reserved SPEED [B:A] OD + PU OD + PD Reserved Input Floating Input Input Reserved (input floating) Input/output Analog...
Page 187: I/O Pin Multiplexer And Mapping
RM0430 General-purpose I/Os (GPIO) 7.3.2 I/O pin multiplexer and mapping The microcontroller I/O pins are connected to onboard peripherals/modules through a multiplexer that allows only one peripheral’s alternate function (AF) connected to an I/O pin at a time. In this way, there can be no conflict between peripherals sharing the same I/O pin. Each I/O pin has a multiplexer with sixteen alternate function inputs (AF0 to AF15) that can be configured through the GPIOx_AFRL (for pin 0 to 7) and GPIOx_AFRH (for pin 8 to 15) registers:...
Page 188: Table 26. Flexible Swj-Dp Pin Assignment
General-purpose I/Os (GPIO) RM0430 Table 26. Flexible SWJ-DP pin assignment SWJ I/O pin assigned PA13 / PA14 / Available debug ports PA15 / PB3 / PB4/ JTMS/ JTCK/ JTDI JTDO NJTRST SWDIO SWCLK Full SWJ (JTAG-DP + SW-DP) - Reset state Full SWJ (JTAG-DP + SW-DP) but without NJTRST JTAG-DP Disabled and SW-DP Enabled...
Page 189: Figure 18. Selecting An Alternate Function On Stm32F413/423
RM0430 General-purpose I/Os (GPIO) Figure 18. Selecting an alternate function on STM32F413/423 RM0430 Rev 8 189/1324...
Page 190: I/O Port Control Registers
General-purpose I/Os (GPIO) RM0430 7.3.3 I/O port control registers Each of the GPIOs has four 32-bit memory-mapped control registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os. The GPIOx_MODER register is used to select the I/O direction (input, output, AF, analog). The GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type (push-pull or open-drain) and speed (the I/O speed pins are directly connected to the corresponding GPIOx_OSPEEDR register bits whatever the I/O direction).
Page 191: I/O Alternate Function Input/Output
RM0430 General-purpose I/Os (GPIO) The LOCK sequence (refer to Section 7.4.8: GPIO port configuration lock register (GPIOx_LCKR) (x = A...H)) can only be performed using a word (32-bit long) access to the GPIOx_LCKR register due to the fact that GPIOx_LCKR bit 16 has to be set at the same time as the [15:0] bits.
Page 192: Output Configuration
General-purpose I/Os (GPIO) RM0430 Figure 19. Input floating/pull up/pull down configurations 7.3.10 Output configuration When the I/O port is programmed as output: • The output buffer is enabled: – Open drain mode: A “0” in the Output register activates the N-MOS whereas a “1” in the Output register leaves the port in Hi-Z (the P-MOS is never activated) –...
Page 193: Alternate Function Configuration
RM0430 General-purpose I/Os (GPIO) Figure 20. Output configuration 7.3.11 Alternate function configuration When the I/O port is programmed as alternate function: • The output buffer can be configured as open-drain or push-pull • The output buffer is driven by the signal coming from the peripheral (transmitter enable and data) •...
Page 194: Analog Configuration
General-purpose I/Os (GPIO) RM0430 7.3.12 Analog configuration When the I/O port is programmed as analog configuration: • The output buffer is disabled • The Schmitt trigger input is deactivated, providing zero consumption for every analog value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0). •...
Page 195: Selection Of Rtc Additional Functions
RM0430 General-purpose I/Os (GPIO) 7.3.15 Selection of RTC additional functions The STM32F4xx feature one GPIO pin RTC_AF1 that can be used for the detection of a tamper or time stamp event, or RTC_ALARM, or RTC_CALIB RTC outputs. • The RTC_AF1 (PC13) can be used for the following purposes: RTC_ALARM output: this output can be RTC Alarm A, RTC Alarm B or RTC Wakeup depending on the OSEL[1:0] bits in the RTC_CR register •...
Page 196: Gpio Registers
General-purpose I/Os (GPIO) RM0430 GPIO registers This section gives a detailed description of the GPIO registers. For a summary of register bits, register address offsets and reset values, refer to Table The GPIO registers can be accessed by byte (8 bits), half-words (16 bits) or words (32 bits). 7.4.1 GPIO port mode register (GPIOx_MODER) (x = A...H) Address offset: 0x00...
Page 197: Gpio Port Output Speed Register (Gpiox_Ospeedr)
RM0430 General-purpose I/Os (GPIO) 7.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A...H) Address offset: 0x08 Reset values: • 0x0C00 0000 for port A • 0x0000 00C0 for port B • 0x0000 0000 for other ports OSPEEDR15 OSPEEDR14 OSPEEDR13 OSPEEDR12 OSPEEDR11 OSPEEDR10...
Page 198: Gpio Port Input Data Register (Gpiox_Idr) (X = A
General-purpose I/Os (GPIO) RM0430 7.4.5 GPIO port input data register (GPIOx_IDR) (x = A...H) Address offset: 0x10 Reset value: 0x0000 XXXX (where X means undefined) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 199: Gpio Port Configuration Lock Register (Gpiox_Lckr)
RM0430 General-purpose I/Os (GPIO) Bits 31:16 BRy: Port x reset bit y (y = 0..15) These bits are write-only and can be accessed in word, half-word or byte mode. A read to these bits returns the value 0x0000. 0: No action on the corresponding ODRx bit 1: Resets the corresponding ODRx bit Note: If both BSx and BRx are set, BSx has priority.
Page 200: Gpio Alternate Function Low Register (Gpiox_Afrl) (X = A
General-purpose I/Os (GPIO) RM0430 Bits 31:17 Reserved, must be kept at reset value. Bit 16 LCKK[16]: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. 0: Port configuration lock key not active 1: Port configuration lock key active.
Page 201: (X = A
RM0430 General-purpose I/Os (GPIO) 7.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A...H) Address offset: 0x24 Reset value: 0x0000 0000 AFRH15[3:0] AFRH14[3:0] AFRH13[3:0] AFRH12[3:0] AFRH11[3:0] AFRH10[3:0] AFRH9[3:0] AFRH8[3:0] Bits 31:0 AFRHy: Alternate function selection for port x bit y (y = 8..15) These bits are written by software to configure alternate function I/Os AFRHy selection: 0000: AF0...
Page 202 General-purpose I/Os (GPIO) RM0430 Table 28. GPIO register map and reset values (continued) Offset Register GPIOx_ OTYPER 0x04 (where x = A...H) Reset value GPIOx_ OSPEEDR (where x = 0x08 C...H) Reset value GPIOA_ OSPEEDER 0x08 Reset value GPIOB_ OSPEEDR 0x08 Reset value GPIOA_PUPDR...
Page 203 RM0430 General-purpose I/Os (GPIO) Table 28. GPIO register map and reset values (continued) Offset Register GPIOx_LCKR (where x = A...H) 0x1C Reset value GPIOx_AFRL AFRL7[3:0] AFRL6[3:0] AFRL5[3:0] AFRL4[3:0] AFRL3[3:0] AFRL2[3:0] AFRL1[3:0] AFRL0[3:0] (where x = A...H) 0x20 Reset value GPIOx_AFRH AFRH15[3:0] AFRH14[3:0] AFRH13[3:0] AFRH12[3:0] AFRH11[3:0] AFRH10[3:0] AFRH9[3:0] AFRH8[3:0]...
Page 204: System Configuration Controller (Syscfg)
System configuration controller (SYSCFG) RM0430 System configuration controller (SYSCFG) The system configuration controller is mainly used to remap the memory accessible in the code area and manage the external interrupt line connection to the GPIOs. I/O compensation cell By default the I/O compensation cell is not used. However when the I/O output buffer speed is configured in 50 MHz or 100 MHz mode, it is recommended to use the compensation cell for slew rate control on I/O t commutation to reduce the I/O noise on power...
Page 205: Syscfg Peripheral Mode Configuration Register (Syscfg_Pmc)
RM0430 System configuration controller (SYSCFG) Bits 31:2 Reserved, must be kept at reset value. Bits 1:0 MEM_MODE: Memory mapping selection Set and cleared by software. This bit controls the memory internal mapping at address 0x0000 0000. After reset these bits take the value selected by the Boot pins.
Page 206: Syscfg External Interrupt Configuration Register 1
System configuration controller (SYSCFG) RM0430 8.2.3 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0] Bits 31:16 Reserved, must be kept at reset value.
Page 207: Syscfg External Interrupt Configuration Register 3
RM0430 System configuration controller (SYSCFG) Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 4 to 7) These bits are written by software to select the source input for the EXTIx external interrupt. 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin...
Page 208: (Syscfg_Exticr4)
System configuration controller (SYSCFG) RM0430 8.2.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) Address offset: 0x14 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0] Bits 31:16 Reserved, must be kept at reset value.
Page 209: Compensation Cell Control Register (Syscfg_Cmpcr)
RM0430 System configuration controller (SYSCFG) Bit 2 PVDL: PVD lock This bit is set by software. It can be cleared only by a system reset. It enables and locks the PVD connection to TIM1/8 Break input. It also locks (write protection) the PVDE and PVDS[2:0] bits of PWR_CR register.
Page 210: Syscfg Configuration Register (Syscfg_Cfgr)
System configuration controller (SYSCFG) RM0430 8.2.9 SYSCFG configuration register (SYSCFG_CFGR) Address offset: 0x2C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 211 RM0430 System configuration controller (SYSCFG) Bit 16 DFSDM2_CK37SEL: Distribution of the DFSDM2 bitstream clock gated by TIM3 OC1 (DM3 demultiplexer on Figure 81: Multi-channel delay block for pulse skipping) 0: The gated clock is distributed to CkIn3 (DM3 = 0) 1: The gated clock is distributed to CkIn7 (DM3 = 1) Bit 15 DFSDM2_CK26SEL: Distribution of the DFSDM2 bitstream clock gated by TIM3 OC2...
Page 212 System configuration controller (SYSCFG) RM0430 Bit 4 DFSDM1_CK02SEL: Distribution of the DFSDM1 bitstream clock gated by TIM4 OC2 (DM2 demultiplexer on Figure 81: Multi-channel delay block for pulse skipping) 0: The gated clock is distributed to CkIn0 (DM2 = 0) 1: The gated clock is distributed to CkIn2 (DM2 = 1) Bit 3 DFSDM1_D2SEL: Source selection for DatIn2 of DFSDM1 (M8 multiplexer on...
Page 213: Syscfg Register Map
RM0430 System configuration controller (SYSCFG) 8.2.11 SYSCFG register map The following table gives the SYSCFG register map and the reset values. Table 29. SYSCFG register map and reset values Offset Register SYSCFG_ MEMRMP 0x00 Reset value SYSCFG_PMC 0x04 Reset value SYSCFG_EXTICR1 EXTI3[3:0] EXTI2[3:0]...
Page 214: Direct Memory Access Controller (Dma)
Direct memory access controller (DMA) RM0430 Direct memory access controller (DMA) DMA introduction Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory and between memory and memory. Data can be quickly moved by DMA without any CPU action.
Page 215 RM0430 Direct memory access controller (DMA) – DMA flow controller: the number of data items to be transferred is software- programmable from 1 to 65535 – Peripheral flow controller: the number of data items to be transferred is unknown and controlled by the source or the destination peripheral that signals the end of the transfer by hardware •...
Page 216: Dma Functional Description
Direct memory access controller (DMA) RM0430 DMA functional description 9.3.1 DMA block diagram Figure 23 shows the block diagram of a DMA. Figure 23. DMA block diagram 9.3.2 DMA overview The DMA controller performs direct memory transfer: as an AHB master, it can take the control of the AHB bus matrix to initiate AHB transactions.
Page 217: Dma Transactions
RM0430 Direct memory access controller (DMA) 9.3.3 DMA transactions A DMA transaction consists of a sequence of a given number of data transfers. The number of data items to be transferred and their width (8-bit, 16-bit or 32-bit) are software- programmable.
Page 218: Table 30. Dma1 Request Mapping
Direct memory access controller (DMA) RM0430 Table 30. DMA1 request mapping Peripheral Stream 0 Stream 1 Stream 2 Stream 3 Stream 4 Stream 5 Stream 6 Stream 7 requests Channel 0 SPI3_RX I2C1_TX SPI3_RX SPI2_RX SPI2_TX SPI3_TX SPI3_TX Channel 1 I2C1_RX I2C3_RX TIM7_UP...
Page 219: Arbiter
RM0430 Direct memory access controller (DMA) 9.3.5 Arbiter An arbiter manages the 8 DMA stream requests based on their priority for each of the two AHB master ports (memory and peripheral ports) and launches the peripheral/memory access sequences. Priorities are managed in two stages: •...
Page 220: Figure 25. Peripheral-To-Memory Mode
Direct memory access controller (DMA) RM0430 When the data width (programmed in the PSIZE or MSIZE bits in the DMA_SxCR register) is a half-word or a word, respectively, the peripheral or memory address written into the DMA_SxPAR or DMA_SxM0AR/M1AR registers has to be aligned on a word or half-word address boundary, respectively.
Page 221: Figure 26. Memory-To-Peripheral Mode
RM0430 Direct memory access controller (DMA) Each time a peripheral request occurs, the contents of the FIFO are drained and stored into the destination. When the level of the FIFO is lower than or equal to the predefined threshold level, the FIFO is fully reloaded with data from the memory. The transfer stops once the DMA_SxNDTR register reaches zero, when the peripheral requests the end of transfers (in case of a peripheral flow controller) or when the EN bit in the DMA_SxCR register is cleared by software.
Page 222: Pointer Incrementation
Direct memory access controller (DMA) RM0430 The stream has access to the AHB source or destination port only if the arbitration of the corresponding stream is won. This arbitration is performed using the priority defined for each stream using the PL[1:0] bits in the DMA_SxCR register. Note: When memory-to-memory mode is used, the circular and direct modes are not allowed.
Page 223: Circular Mode
RM0430 Direct memory access controller (DMA) 9.3.9 Circular mode The circular mode is available to handle circular buffers and continuous data flows (e.g. ADC scan mode). This feature can be enabled using the CIRC bit in the DMA_SxCR register. When the circular mode is activated, the number of data items to be transferred is automatically reloaded with the initial value programmed during the stream configuration phase, and the DMA requests continue to be served.
Page 224: Programmable Data Width, Packing/Unpacking, Endianness
Direct memory access controller (DMA) RM0430 memory 0 to 1 (or from 1 to 0) depending on the value of CT in the DMA_SxCR register in accordance with one of the two above conditions. For all the other modes (except the double-buffer mode), the memory address registers are write-protected as soon as the stream is enabled.
Page 225: Table 34. Packing/Unpacking And Endian Behavior (Bit Pinc = Minc = 1)
RM0430 Direct memory access controller (DMA) Table 34. Packing/unpacking and endian behavior (bit PINC = MINC = 1) Number Peripheral port address / byte lane of data Memory Memory port Peripheral memory peripheral items to transfer address / byte transfer port port PINCOS = 1...
Page 226: Single And Burst Transfers
Direct memory access controller (DMA) RM0430 9.3.12 Single and burst transfers The DMA controller can generate single transfers or incremental burst transfers of 4, 8 or 16 beats. The size of the burst is configured by software independently for the two AHB ports by using the MBURST[1:0] and PBURST[1:0] bits in the DMA_SxCR register.
Page 227: Table 36. Fifo Threshold Configurations
RM0430 Direct memory access controller (DMA) Figure 28. FIFO structure FIFO threshold and burst configuration Caution is required when choosing the FIFO threshold (bits FTH[1:0] of the DMA_SxFCR register) and the size of the memory burst (MBURST[1:0] of the DMA_SxCR register): The content pointed by the FIFO threshold must exactly match an integer number of memory burst transfers.
Page 228 Direct memory access controller (DMA) RM0430 Table 36. FIFO threshold configurations (continued) MSIZE FIFO level MBURST = INCR4 MBURST = INCR8 MBURST = INCR16 Forbidden 1 burst of 4 beats Forbidden Half-word Forbidden Full 2 bursts of 4 beats 1 burst of 8 beats Forbidden Forbidden Word...
Page 229: Dma Transfer Completion
RM0430 Direct memory access controller (DMA) value. The software may read the DMA_SxNDTR register to determine the memory area that contains the good data (start address and last address). If the number of remaining data items in the FIFO is lower than a burst size (if the MBURST bits in DMA_SxCR register are set to configure the stream to manage burst on the AHB memory port), single transactions are generated to complete the FIFO flush.
Page 230: Dma Transfer Suspension
Direct memory access controller (DMA) RM0430 9.3.15 DMA transfer suspension At any time, a DMA transfer can be suspended to be restarted later on or to be definitively disabled before the end of the DMA transfer. There are two cases: •...
Page 231: Summary Of The Possible Dma Configurations
RM0430 Direct memory access controller (DMA) triggered in the case of a peripheral-to-memory DMA transfer. The TCIFx flag of the corresponding stream is set in the status register to indicate the DMA completion. To know the number of data items transferred during the DMA transfer, read the DMA_SxNDTR register and apply the following formula: –...
Page 232: Stream Configuration Procedure
Direct memory access controller (DMA) RM0430 9.3.18 Stream configuration procedure The following sequence must be followed to configure a DMA stream x (where x is the stream number): If the stream is enabled, disable it by resetting the EN bit in the DMA_SxCR register, then read this bit in order to confirm that there is no ongoing stream operation.
Page 233: Error Management
RM0430 Direct memory access controller (DMA) 9.3.19 Error management The DMA controller can detect the following errors: • Transfer error: the transfer error interrupt flag (TEIFx) is set when: – a bus error occurs during a DMA read or a write access –...
Page 234: Dma Interrupts
Direct memory access controller (DMA) RM0430 DMA interrupts For each DMA stream, an interrupt can be produced on the following events: • Half-transfer reached • Transfer complete • Transfer error • FIFO error (overrun, underrun or FIFO level error) • Direct mode error Separate interrupt enable control bits are available for flexibility as shown in Table...
Page 235: Dma Registers
RM0430 Direct memory access controller (DMA) DMA registers The DMA registers have to be accessed by words (32 bits). 9.5.1 DMA low interrupt status register (DMA_LISR) Address offset: 0x00 Reset value: 0x0000 0000 Res. Res. Res. Res. TCIF3 HTIF3 TEIF3 DMEIF3 Res.
Page 236: Dma High Interrupt Status Register (Dma_Hisr)
Direct memory access controller (DMA) RM0430 9.5.2 DMA high interrupt status register (DMA_HISR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. TCIF7 HTIF7 TEIF7 DMEIF7 Res. FEIF7 TCIF6 HTIF6 TEIF6 DMEIF6 Res. FEIF6 Res. Res. Res. Res. TCIF5 HTIF5 TEIF5...
Page 237: Dma Low Interrupt Flag Clear Register (Dma_Lifcr)
RM0430 Direct memory access controller (DMA) 9.5.3 DMA low interrupt flag clear register (DMA_LIFCR) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. CTCIF3 CHTIF3 CTEIF3 CDMEIF3 Res. CFEIF3 CTCIF2 CHTIF2 CTEIF2 CDMEIF2 Res. CFEIF2 Res. Res. Res. Res.
Page 238: Dma Stream X Configuration Register (Dma_Sxcr)
Direct memory access controller (DMA) RM0430 Bits 24, 18, 8, 2 CDMEIF[7:4]: stream x clear direct mode error interrupt flag (x = 7..4) Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_HISR register. Bits 23, 17, 7, 1 Reserved, must be kept at reset value. Bits 22, 16, 6, 0 CFEIF[7:4]: stream x clear FIFO error interrupt flag (x = 7..4) Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_HISR register.
Page 239 RM0430 Direct memory access controller (DMA) Bits 22:21 PBURST[1:0]: peripheral burst transfer configuration These bits are set and cleared by software. 00: single transfer 01: INCR4 (incremental burst of 4 beats) 10: INCR8 (incremental burst of 8 beats) 11: INCR16 (incremental burst of 16 beats) These bits are protected and can be written only if EN is ‘0’.
Page 240 Direct memory access controller (DMA) RM0430 Bits 12:11 PSIZE[1:0]: peripheral data size These bits are set and cleared by software. 00: byte (8-bit) 01: half-word (16-bit) 10: word (32-bit) 11: reserved These bits are protected and can be written only if EN is ‘0’. Bit 10 MINC: memory increment mode This bit is set and cleared by software.
Page 241: Dma Stream X Number Of Data Register (Dma_Sxndtr)
RM0430 Direct memory access controller (DMA) Bit 2 TEIE: transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled Bit 1 DMEIE: direct mode error interrupt enable This bit is set and cleared by software. 0: DME interrupt disabled 1: DME interrupt enabled Bit 0 EN: stream enable / flag stream ready when read low...
Page 242: Dma Stream X Peripheral Address Register (Dma_Sxpar)
Direct memory access controller (DMA) RM0430 9.5.7 DMA stream x peripheral address register (DMA_SxPAR) Address offset: 0x18 + 0x18 * x, (x = 0 to 7) Reset value: 0x0000 0000 PAR[31:16] PAR[15:0] Bits 31:0 PAR[31:0]: peripheral address Base address of the peripheral data register from/to which the data is read/written. These bits are write-protected and can be written only when bit EN = '0' in the DMA_SxCR register.
Page 243: Dma Stream X Fifo Control Register (Dma_Sxfcr)
RM0430 Direct memory access controller (DMA) Bits 31:0 M1A[31:0]: memory 1 address (used in case of double-buffer mode) Base address of memory area 1 from/to which the data is read/written. This register is used only for the double-buffer mode. These bits are write-protected. They can be written only if: –...
Page 244 Direct memory access controller (DMA) RM0430 Bits 1:0 FTH[1:0]: FIFO threshold selection These bits are set and cleared by software. 00: 1/4 full FIFO 01: 1/2 full FIFO 10: 3/4 full FIFO 11: full FIFO These bits are not used in the direct mode when the DMIS value is zero. These bits are protected and can be written only if EN is ‘0’.
Page 245: Dma Register Map
RM0430 Direct memory access controller (DMA) 9.5.11 DMA register map Table 39 summarizes the DMA registers. Table 39. DMA register map and reset values Offset Register name DMA_LISR 0x0000 Reset value DMA_HISR 0x0004 Reset value DMA_LIFCR 0x0008 Reset value DMA_HIFCR 0x000C Reset value DMA_S0CR...
Page 246 Direct memory access controller (DMA) RM0430 Table 39. DMA register map and reset values (continued) Offset Register name DMA_S1M0AR M0A[31:0] 0x0034 Reset value DMA_S1M1AR M1A[31:0] 0x0038 Reset value DMA_S1FCR FS[2:0] 0x003C Reset value DMA_S2CR 0x0040 Reset value DMA_S2NDTR NDT[15:0] 0x0044 Reset value DMA_S2PAR PA[31:0]...
Page 247 RM0430 Direct memory access controller (DMA) Table 39. DMA register map and reset values (continued) Offset Register name DMA_S3FCR FS[2:0] 0x006C Reset value DMA_S4CR 0x0070 Reset value DMA_S4NDTR NDT[15:0] 0x0074 Reset value DMA_S4PAR PA[31:0] 0x0078 Reset value DMA_S4M0AR M0A[31:0] 0x007C Reset value DMA_S4M1AR M1A[31:0]...
Page 248 Direct memory access controller (DMA) RM0430 Table 39. DMA register map and reset values (continued) Offset Register name DMA_S6NDTR NDT[15:0] 0x00A4 Reset value DMA_S6PAR PA[31:0] 0x00A8 Reset value DMA_S6M0AR M0A[31:0] 0x00AC Reset value DMA_S6M1AR M1A[31:0] 0x00B0 Reset value DMA_S6FCR FS[2:0] 0x00B4 Reset value DMA_S7CR...
Page 249: Interrupts And Events
RM0430 Interrupts and events Interrupts and events 10.1 Nested vectored interrupt controller (NVIC) 10.1.1 NVIC features The nested vector interrupt controller NVIC includes the following features: ® • 52 maskable interrupt channels (not including the 16 interrupt lines of Cortex -M4 with FPU) •...
Page 250: Table 40. Vector Table For Stm32F413/423
Interrupts and events RM0430 Table 40. Vector table for STM32F413/423 Type of Acronym Description Address priority Reserved 0x0000 0000 fixed Reset Reset 0x0000 0004 Non maskable interrupt, Clock Security fixed 0x0000 0008 System fixed HardFault All class of fault 0x0000 000C settable MemManage Memory management...
Page 251 RM0430 Interrupts and events Table 40. Vector table for STM32F413/423 (continued) Type of Acronym Description Address priority settable DMA1_Stream4 DMA1 Stream4 global interrupt 0x0000 007C settable DMA1_Stream5 DMA1 Stream5 global interrupt 0x0000 0080 settable DMA1_Stream6 DMA1 Stream6 global interrupt 0x0000 0084 settable ADC1 global interrupt 0x0000 0088...
Page 252 Interrupts and events RM0430 Table 40. Vector table for STM32F413/423 (continued) Type of Acronym Description Address priority EXTI Line 17 interrupt / EXTI17 / settable 0x0000 00E4 RTC Alarms (A and B) through EXTI line RTC Alarm interrupt EXTI Line 18 interrupt / USB On-The-Go FS settable EXTI18 / OTG_FS_WKUP 0x0000 00E8...
Page 253 RM0430 Interrupts and events Table 40. Vector table for STM32F413/423 (continued) Type of Acronym Description Address priority settable OTG_FS USB On The Go FS global interrupt 0x0000 014C settable DMA2_Stream5 DMA2 Stream5 global interrupt 0x0000 0150 settable DMA2_Stream6 DMA2 Stream6 global interrupt 0x0000 0154 settable DMA2_Stream7...
Page 254: Exti Main Features
Interrupts and events RM0430 10.2.1 EXTI main features The main features of the EXTI controller are the following: • independent trigger and mask on each interrupt/event line • dedicated status bit for each interrupt line • generation of up to 23 software event/interrupt requests •...
Page 255 RM0430 Interrupts and events IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared. • or configuring an external or internal EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bit corresponding to the event line is not set.
Page 256: Functional Description
Interrupts and events RM0430 10.2.4 Functional description To generate the interrupt, the interrupt line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the interrupt request by writing a ‘1’ to the corresponding bit in the interrupt mask register. When the selected edge occurs on the external interrupt line, an interrupt request is generated.
Page 257: External Interrupt/Event Line Mapping
RM0430 Interrupts and events 10.2.5 External interrupt/event line mapping Up to STM32F413/423 are connected to the 16 external interrupt/event lines in the following manner: Figure 30. External interrupt/event GPIO mapping The five other EXTI lines are connected as follows: • EXTI line 16 is connected to the PVD output •...
Page 258: Exti Registers
Interrupts and events RM0430 10.3 registers EXTI Refer to Section 1.2: List of abbreviations for registers for a list of abbreviations used in register descriptions. 10.3.1 Interrupt mask register (EXTI_IMR) Address offset: 0x00 Reset value: 0x0000 0000 Res. Res. Res. Res.
Page 259: Rising Trigger Selection Register (Exti_Rtsr)
RM0430 Interrupts and events 10.3.3 Rising trigger selection register (EXTI_RTSR) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. TR23 TR22 TR21 Res. Res. TR18 TR17 TR16 TR15 TR14 TR13 TR12 TR11 TR10 Bits 31:24 Reserved, must be kept at reset value. Bits 23:21 TR[23:21]: Rising trigger event configuration bit of line x 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line...
Page 260: Falling Trigger Selection Register (Exti_Ftsr)
Interrupts and events RM0430 10.3.4 Falling trigger selection register (EXTI_FTSR) Address offset: 0x0C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. TR23 TR22 TR21 Res. Res. TR18 TR17 TR16 TR15 TR14 TR13 TR12 TR11 TR10 Bits 31:24 Reserved, must be kept at reset value. Bits 23:21 TR[23:21]: Falling trigger event configuration bit of line x 0: Falling trigger disabled (for Event and Interrupt) for input line 1: Falling trigger enabled (for Event and Interrupt) for input line.
Page 261: Software Interrupt Event Register (Exti_Swier)
RM0430 Interrupts and events 10.3.5 Software interrupt event register (EXTI_SWIER) Address offset: 0x10 Reset value: 0x0000 0000 SWIER SWIER SWIER SWIER SWIER SWIER Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER...
Page 262: Pending Register (Exti_Pr)
Interrupts and events RM0430 10.3.6 Pending register (EXTI_PR) Address offset: 0x14 Reset value: undefined Res. Res. Res. Res. Res. Res. Res. Res. PR23 PR22 PR21 Res. Res. PR18 PR17 PR16 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 PR15 PR14 PR13 PR12 PR11 PR10 rc_w1...
Page 263: Exti Register Map
RM0430 Interrupts and events 10.3.7 EXTI register map Table 41 gives the EXTI register map and the reset values. Table 41. External interrupt/event controller register map and reset values Offset Register EXTI_IMR MR[18:0] [23:21] 0x00 Reset value EXTI_EMR MR[18:0] [23:21] 0x04 Reset value EXTI_RTSR...
Page 264: Flexible Static Memory Controller (Fsmc)
Flexible static memory controller (FSMC) RM0430 Flexible static memory controller (FSMC) The Flexible static memory controller (FSMC) includes one memory controller: • The NOR/PSRAM memory controller 11.1 FSMC main features The FSMC functional block makes the interface with: synchronous and asynchronous static memories.
Page 265: Fmc Block Diagram
RM0430 Flexible static memory controller (FSMC) 11.2 FMC block diagram The FSMC consists of the following main blocks: • The AHB interface (including the FSMC configuration registers) • The NOR Flash/PSRAM/SRAM controller The block diagram is shown in the figure below. Figure 31.
Page 266: Ahb Interface
Flexible static memory controller (FSMC) RM0430 11.3 AHB interface The AHB slave interface allows internal CPUs and other bus master peripherals to access the external memories. AHB transactions are translated into the external device protocol. In particular, if the selected external memory is 16- or 8-bit wide, 32-bit wide transactions on the AHB are split into consecutive 16- or 8-bit accesses.
Page 267: External Device Address Mapping
RM0430 Flexible static memory controller (FSMC) transactions are allowed (the controller reads the entire 16-bit memory word and uses only the required byte). Wrap support for NOR Flash/PSRAM Wrap burst mode for synchronous memories is not supported. The memories must be configured in Linear burst mode of undefined length.
Page 268: Nor Flash/Psram Controller
Flexible static memory controller (FSMC) RM0430 The HADDR[25:0] bits contain the external memory address. Since HADDR is a byte address whereas the memory is addressed at word level, the address actually issued to the memory varies according to the memory data width, as shown in the following table. Table 43.
Page 269: External Memory Interface Signals
RM0430 Flexible static memory controller (FSMC) and synchronous accesses depending on the CCKEN bit configuration in the FSMC_BCR1 register: • If the CCLKEN bit is reset, the FSMC generates the clock (CLK) only during synchronous accesses (Read/write transactions). • If the CCLKEN bit is set, the FSMC generates a continuous clock during asynchronous and synchronous accesses.
Page 270: Table 45. Non-Multiplexed I/O Nor Flash Memory
Flexible static memory controller (FSMC) RM0430 NOR Flash memory, non-multiplexed I/Os Table 45. Non-multiplexed I/O NOR Flash memory FSMC signal name Function Clock (for synchronous access) A[25:0] Address bus D[15:0] Bidirectional data bus NE[x] Chip select, x = 1..4 Output enable Write enable Latch enable (this signal is called address NL(=NADV)
Page 271: Supported Memories And Transactions
RM0430 Flexible static memory controller (FSMC) Table 47. Non-multiplexed I/Os PSRAM/SRAM (continued) FSMC signal Function name NE[x] Chip select, x = 1..4 (called NCE by PSRAM (CellularRAM™ i.e. CRAM)) Output enable Write enable NL(= NADV) Address valid only for PSRAM input (memory signal name: NADV) NWAIT PSRAM wait input signal to the FSMC NBL[1:0]...
Page 272: Table 49. Nor Flash/Psram: Example Of Supported Memories And Transactions
Flexible static memory controller (FSMC) RM0430 Table 49. NOR Flash/PSRAM: example of supported memories and transactions Allowed/ Memory Device Mode data Comments data size size allowed Asynchronous Asynchronous Asynchronous Asynchronous NOR Flash Asynchronous Split into 2 FSMC accesses (muxed I/Os Asynchronous Split into 2 FSMC accesses and nonmuxed...
Page 273: General Timing Rules
RM0430 Flexible static memory controller (FSMC) 11.5.3 General timing rules Signals synchronization • All controller output signals change on the rising edge of the internal clock (HCLK) • In Synchronous mode (read or write), all output signals change on the rising edge of HCLK.
Page 274: Figure 33. Mode1 Read Access Waveforms
Flexible static memory controller (FSMC) RM0430 Mode 1 - SRAM/PSRAM (CRAM) The next figures show the read and write transactions for the supported modes followed by the required configuration of FSMC_BCRx, and FSMC_BTRx/FSMC_BWTRx registers. Figure 33. Mode1 read access waveforms Figure 34.
Page 275: Table 50. Fsmc_Bcrx Bit Fields
RM0430 Flexible static memory controller (FSMC) The one HCLK cycle at the end of the write transaction helps guarantee the address and data hold time after the NWE rising edge. Due to the presence of this HCLK cycle, the DATAST value must be greater than zero (DATAST > 0). Table 50.
Page 276: Figure 35. Modea Read Access Waveforms
Flexible static memory controller (FSMC) RM0430 Mode A - SRAM/PSRAM (CRAM) OE toggling Figure 35. ModeA read access waveforms 1. NBL[1:0] are driven low during the read access Figure 36. ModeA write access waveforms 276/1324 RM0430 Rev 8...
Page 277: Table 52. Fsmc_Bcrx Bit Fields
RM0430 Flexible static memory controller (FSMC) The differences compared with Mode1 are the toggling of NOE and the independent read and write timings. Table 52. FSMC_BCRx bit fields Bit number Bit name Value to set 31:22 Reserved 0x000 WFDIS As needed CCLKEN As needed CBURSTRW...
Page 278: Table 54. Fsmc_Bwtrx Bit Fields
Flexible static memory controller (FSMC) RM0430 Table 54. FSMC_BWTRx bit fields Bit number Bit name Value to set 31:30 Reserved 29:28 ACCMOD 27:24 DATLAT Don’t care 23:20 CLKDIV Don’t care 19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK). Duration of the second access phase (DATAST HCLK cycles) for write 15:8 DATAST...
Page 279: Figure 38. Mode2 Write Access Waveforms
RM0430 Flexible static memory controller (FSMC) Figure 38. Mode2 write access waveforms Figure 39. ModeB write access waveforms The differences with Mode1 are the toggling of NWE and the independent read and write timings when extended mode is set (Mode B). RM0430 Rev 8 279/1324...
Page 280: Table 55. Fsmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0430 Table 55. FSMC_BCRx bit fields Bit number Bit name Value to set 31:22 Reserved 0x000 WFDIS As needed CCLKEN As needed CBURSTRW 0x0 (no effect in Asynchronous mode) 18:16 CPSIZE 0x0 (no effect in Asynchronous mode) ASYNCWAIT Set to 1 if the memory supports this feature.
Page 281: Table 57. Fsmc_Bwtrx Bit Fields
RM0430 Flexible static memory controller (FSMC) Table 57. FSMC_BWTRx bit fields Bit number Bit name Value to set 31:30 Reserved 29:28 ACCMOD 0x1 if Extended mode is set 27:24 DATLAT Don’t care 23:20 CLKDIV Don’t care 19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK). Duration of the access second phase (DATAST HCLK cycles) for 15:8 DATAST...
Page 282: Table 58. Fsmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0430 Figure 41. ModeC write access waveforms The differences compared with Mode1 are the toggling of NOE and the independent read and write timings. Table 58. FSMC_BCRx bit fields Bit number Bit name Value to set 31:22 Reserved 0x000...
Page 283: Table 59. Fsmc_Btrx Bit Fields
RM0430 Flexible static memory controller (FSMC) Table 58. FSMC_BCRx bit fields (continued) Bit number Bit name Value to set MTYP 0x02 (NOR Flash memory) MUXEN MBKEN Table 59. FSMC_BTRx bit fields Bit number Bit name Value to set 31:30 Reserved 29:28 ACCMOD 27:24...
Page 284: Figure 42. Moded Read Access Waveforms
Flexible static memory controller (FSMC) RM0430 Mode D - asynchronous access with extended address Figure 42. ModeD read access waveforms Figure 43. ModeD write access waveforms 284/1324 RM0430 Rev 8...
Page 285: Table 61. Fsmc_Bcrx Bit Fields
RM0430 Flexible static memory controller (FSMC) The differences with Mode1 are the toggling of NOE that goes on toggling after NADV changes and the independent read and write timings. Table 61. FSMC_BCRx bit fields Bit number Bit name Value to set 31:22 Reserved 0x000...
Page 286: Table 63. Fsmc_Bwtrx Bit Fields
Flexible static memory controller (FSMC) RM0430 Table 63. FSMC_BWTRx bit fields Bit number Bit name Value to set 31:30 Reserved 29:28 ACCMOD 27:24 DATLAT Don’t care 23:20 CLKDIV Don’t care 19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK). Duration of the second access phase (DATAST + 1 HCLK cycles) for 15:8 DATAST...
Page 287: Table 64. Fsmc_Bcrx Bit Fields
RM0430 Flexible static memory controller (FSMC) Figure 45. Muxed write access waveforms The difference with ModeD is the drive of the lower address byte(s) on the data bus. Table 64. FSMC_BCRx bit fields Bit number Bit name Value to set 31:22 Reserved 0x000...
Page 288: Table 65. Fsmc_Btrx Bit Fields
Flexible static memory controller (FSMC) RM0430 Table 64. FSMC_BCRx bit fields (continued) Bit number Bit name Value to set MTYP 0x2 (NOR Flash memory) or 0x1(PSRAM) MUXEN MBKEN Table 65. FSMC_BTRx bit fields Bit number Bit name Value to set 31:30 Reserved 29:28...
Page 289: Figure 46. Asynchronous Wait During A Read Access Waveforms
RM0430 Flexible static memory controller (FSMC) The memory asserts the WAIT signal aligned to NOE/NWE which toggles: DATAST ≥ × HCLK max_wait_assertion_time The memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling): > max_wait_assertion_time address_phase hold_phase then: ≥...
Page 290: Synchronous Transactions
Flexible static memory controller (FSMC) RM0430 Figure 47. Asynchronous wait during a write access waveforms 1. NWAIT polarity depends on WAITPOL bit setting in FSMC_BCRx register. 11.5.5 Synchronous transactions The memory clock, FSMC_CLK, is a submultiple of HCLK. It depends on the value of CLKDIV and the MWID/ AHB data size, following the formula given below: FSMC_CLK divider ratio max CLKDIV...
Page 291 RM0430 Flexible static memory controller (FSMC) Caution: Some NOR Flash memories include the NADV Low cycle in the data latency count, so that the exact relation between the NOR Flash latency and the FSMC DATLAT parameter can be either: • NOR Flash latency = (DATLAT + 2) CLK clock cycles •...
Page 292: Figure 48. Wait Configuration Waveforms
Flexible static memory controller (FSMC) RM0430 Figure 48. Wait configuration waveforms 292/1324 RM0430 Rev 8...
Page 293: Table 66. Fsmc_Bcrx Bit Fields
RM0430 Flexible static memory controller (FSMC) Figure 49. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) 1. Byte lane outputs (NBL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM) access, they are held low. Table 66.
Page 294: Table 67. Fsmc_Btrx Bit Fields
Flexible static memory controller (FSMC) RM0430 Table 66. FSMC_BCRx bit fields (continued) Bit number Bit name Value to set WAITPOL To be set according to memory BURSTEN Reserved FACCEN Set according to memory support (NOR Flash memory) MWID As needed MTYP 0x1 or 0x2 MUXEN...
Page 295: Table 68. Fsmc_Bcrx Bit Fields
RM0430 Flexible static memory controller (FSMC) Figure 50. Synchronous multiplexed write mode waveforms - PSRAM (CRAM) 1. The memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed to 0. 2. Byte Lane (NBL) outputs are not shown, they are held low while NEx is active. Table 68.
Page 296: Table 69. Fsmc_Btrx Bit Fields
Flexible static memory controller (FSMC) RM0430 Table 68. FSMC_BCRx bit fields (continued) Bit number Bit name Value to set WREN WAITCFG Reserved WAITPOL to be set according to memory BURSTEN no effect on synchronous write Reserved FACCEN Set according to memory support MWID As needed MTYP...
Page 297: Nor/Psram Controller Registers
RM0430 Flexible static memory controller (FSMC) 11.5.6 NOR/PSRAM controller registers SRAM/NOR-Flash chip-select control register for bank x (FSMC_BCRx) (x = 1 to 4) Address offset: 8 * (x – 1), (x = 1 to 4) Reset value: Bank 1: 0x0000 30DB Reset value: Bank 2: 0x0000 30D2 Reset value: Bank 3: 0x0000 30D2 Reset value: Bank 4: 0x0000 30D2...
Page 298 Flexible static memory controller (FSMC) RM0430 Bit 19 CBURSTRW: Write burst enable. For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FSMC_BCRx register.
Page 299 RM0430 Flexible static memory controller (FSMC) Bit 10 Reserved, must be kept at reset value. Bit 9 WAITPOL: Wait signal polarity bit. Defines the polarity of the wait signal from memory used for either in Synchronous or Asynchronous mode: 0: NWAIT active low (default after reset), 1: NWAIT active high.
Page 300 Flexible static memory controller (FSMC) RM0430 Res. Res. ACCMOD[1:0] DATLAT[3:0] CLKDIV[3:0] BUSTURN[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0] Bits 31:30 Reserved, must be kept at reset value. Bits 29:28 ACCMOD[1:0]: Access mode Specifies the asynchronous access modes as shown in the timing diagrams. These bits are taken into account only when the EXTMOD bit in the FSMC_BCRx register is 1.
Page 301 RM0430 Flexible static memory controller (FSMC) Bits 19:16 BUSTURN[3:0]: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read (and read-to- write) transaction. This delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time needed by the memory to free the data bus after a read access (tEHQZ).
Page 302 Flexible static memory controller (FSMC) RM0430 Bits 7:4 ADDHLD[3:0]: Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure 33 Figure 45), used in mode D or multiplexed accesses: 0000: Reserved 0001: ADDHLD phase duration =1 ×...
Page 303 RM0430 Flexible static memory controller (FSMC) Bits 29:28 ACCMOD[1:0]: Access mode. Specifies the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FSMC_BCRx register is 1. 00: Access mode A 01: Access mode B 10: Access mode C 11: Access mode D...
Page 304 Flexible static memory controller (FSMC) RM0430 Bits 3:0 ADDSET[3:0]: Address setup phase duration. These bits are written by software to define the duration of the address setup phase in HCLK cycles (refer to Figure 33 Figure 45), used in asynchronous accesses: 0000: ADDSET phase duration = 0 ×...
Page 305: Fsmc Register Map
RM0430 Flexible static memory controller (FSMC) 11.6 FSMC register map Table 70. FSMC register map Offset Register CPSIZE MWID MTYP FSMC_BCR1 [2:0] [1:0] [1:0] 0x00 Reset value CPSIZE MWID MTYP FSMC_BCR2 [2:0] [1:0] [1:0] 0x08 Reset value CPSIZE MWID MTYP FSMC_BCR3 [2:0] [1:0]...
Page 306 Flexible static memory controller (FSMC) RM0430 Table 70. FSMC register map (continued) Offset Register FSMC_BWTR3 BUSTURN[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0] 0x114 Reset value FSMC_BWTR4 BUSTURN[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0] 0x11C Reset value Refer to Section 2.2.2 on page 58 for the register boundary addresses. 306/1324 RM0430 Rev 8...
Page 307: Quad-Spi Interface (Quadspi)
RM0430 Quad-SPI interface (QUADSPI) Quad-SPI interface (QUADSPI) 12.1 Introduction The QUADSPI is a specialized communication interface targeting single, dual or quad SPI Flash memories. It can operate in any of the three following modes: • indirect mode: all the operations are performed using the QUADSPI registers •...
Page 308: Quadspi Pins
Quad-SPI interface (QUADSPI) RM0430 Figure 52. QUADSPI block diagram when dual-flash mode is enabled 12.3.2 QUADSPI pins Table 71 lists the QUADSPI pins, six for interfacing with a single Flash memory, or 10 to 11 for interfacing with two Flash memories (FLASH 1 and FLASH 2) in dual-flash mode. Table 71.
Page 309: Quadspi Command Sequence
RM0430 Quad-SPI interface (QUADSPI) 12.3.3 QUADSPI command sequence The QUADSPI communicates with the Flash memory using commands. Each command can include 5 phases: instruction, address, alternate byte, dummy, data. Any of these phases can be configured to be skipped, but at least one of the instruction, address, alternate byte, or data phase must be present.
Page 310 Quad-SPI interface (QUADSPI) RM0430 Alternate-bytes phase In the alternate-bytes phase, 1-4 bytes are sent to the Flash memory, generally to control the mode of operation. The number of alternate bytes to be sent is configured in the ABSIZE[1:0] field of QUADSPI_CCR[17:16] register. The bytes to be sent are specified in the QUADSPI_ABR register.
Page 311: Quadspi Signal Interface Protocol Modes
RM0430 Quad-SPI interface (QUADSPI) mode). This can be configured using the ABMODE[1:0] field of QUADSPI_CCR[15:14] register. When DMODE = 00, the data phase is skipped, and the command sequence finishes immediately by raising nCS. This configuration must only be used in only indirect write mode.
Page 312: Figure 54. An Example Of A Ddr Command In Quad Mode
Quad-SPI interface (QUADSPI) RM0430 SDR mode By default, the DDRM bit (QUADSPI_CCR[31]) is 0 and the QUADSPI operates in single data rate (SDR) mode. In SDR mode, when the QUADSPI is driving the IO0/SO, IO1, IO2, IO3 signals, these signals transition only with the falling edge of CLK. When receiving data in SDR mode, the QUADSPI assumes that the Flash memories also send the data using CLK’s falling edge.
Page 313: Quadspi Indirect Mode
RM0430 Quad-SPI interface (QUADSPI) The Flash memory size, as specified in FSIZE[4:0] (QUADSPI_DCR[20:16]), should reflect the total Flash memory capacity, which is double the size of one individual component. If address X is even, then the byte which the QUADSPI gives for address X is the byte at the address X/2 of FLASH 1, and the byte which the QUADSPI gives for address X+1 is the byte at the address X/2 of FLASH 2.
Page 314 Quad-SPI interface (QUADSPI) RM0430 is set when the limit of the external SPI memory is reached according to the Flash memory size defined in the QUADSPI_CR. Triggering the start of a command Essentially, a command starts as soon as firmware gives the last information that is necessary for this command.
Page 315: Quadspi Status Flag Polling Mode
RM0430 Quad-SPI interface (QUADSPI) 12.3.6 QUADSPI status flag polling mode In automatic-polling mode, the QUADSPI periodically starts a command to read a defined number of status bytes (up to 4). The received bytes can be masked to isolate some status bits and an interrupt can be generated when the selected bits have a defined value.
Page 316: Quadspi Flash Memory Configuration
Quad-SPI interface (QUADSPI) RM0430 By default, the QUADSPI never stops its prefetch operation, keeping the previous read operation active with nCS maintained low, even if no access to the Flash memory occurs for a long time. Since Flash memories tend to consume more when nCS is held low, the application might want to activate the timeout counter (TCEN = 1, bit 3 of QUADSPI_CR) so that nCS is released after a period of TIMEOUT[15:0] (QUADSPI_LPTR) cycles have elapsed without any access since when the FIFO becomes full with prefetch data.
Page 317: Quadspi Usage
RM0430 Quad-SPI interface (QUADSPI) The QUADSPI IP is configured using the QUADSPI_CR. The user shall configure the clock prescaler division factor and the sample shifting settings for the incoming data. DDR mode can be set through the DDRM bit. Once enabled, the address and the alternate bytes are sent on both clock edges and the data are sent/received on both clock edges.
Page 318 Quad-SPI interface (QUADSPI) RM0430 When writing the control register (QUADSPI_CR) the user specifies the following settings: • The enable bit (EN) set to ‘1’ • The DMA enable bit (DMAEN) for transferring data to/from RAM • Timeout counter enable bit (TCEN) •...
Page 319: Sending The Instruction Only Once
RM0430 Quad-SPI interface (QUADSPI) In case of match, the status match flag is set and an interrupt is generated if enabled, and the QUADSPI can be automatically stopped if the AMPS bit is set. In any case, the latest retrieved value is available in the QUADSPI_DR. Memory-mapped mode In memory-mapped mode, the external Flash memory is seen as internal memory but with some latency during accesses.
Page 320: Quadspi Busy Bit And Abort Functionality
Quad-SPI interface (QUADSPI) RM0430 12.3.14 QUADSPI busy bit and abort functionality Once the QUADSPI starts an operation with the Flash memory, the BUSY bit is automatically set in the QUADSPI_SR. In indirect mode, the BUSY bit is reset once the QUADSPI has completed the requested command sequence and the FIFO is empty.
Page 321: Figure 57. Ncs When Ckmode = 1 In Ddr Mode (T = Clk Period)
RM0430 Quad-SPI interface (QUADSPI) When CKMODE = 1 (“mode3”) and DDRM = 1 (DDR mode), nCS falls one CLK cycle before an operation first rising CLK edge, and nCS rises one CLK cycle after the operation final active rising CLK edge, as shown in Figure 57.
Page 322: Quadspi Interrupts
Quad-SPI interface (QUADSPI) RM0430 12.4 QUADSPI interrupts An interrupt can be produced on the following events: • Timeout • Status match • FIFO threshold • Transfer complete • Transfer error Separate interrupt enable bits are available for flexibility. Table 72. QUADSPI interrupt requests Interrupt event Event flag Enable control bit...
Page 323: Quadspi Registers
RM0430 Quad-SPI interface (QUADSPI) 12.5 QUADSPI registers 12.5.1 QUADSPI control register (QUADSPI_CR) Address offset: 0x0000 Reset value: 0x0000 0000 PRESCALER[7:0] APMS Res. TOIE SMIE FTIE TCIE TEIE Res. Res. Res. FTHRES[4:0] FSEL Res. SSHIFT TCEN DMAEN ABORT Bits 31:24 PRESCALER[7:0]: Clock prescaler This field defines the scaler factor for generating CLK based on the AHB clock (value+1).
Page 324 Quad-SPI interface (QUADSPI) RM0430 Bit 18 FTIE: FIFO threshold interrupt enable This bit enables the FIFO threshold interrupt. 0: Interrupt disabled 1: Interrupt enabled Bit 17 TCIE: Transfer complete interrupt enable This bit enables the transfer complete interrupt. 0: Interrupt disabled 1: Interrupt enabled Bit 16 TEIE: Transfer error interrupt enable This bit enables the transfer error interrupt.
Page 325 RM0430 Quad-SPI interface (QUADSPI) Bit 4 SSHIFT: Sample shift By default, the QUADSPI samples data 1/2 of a CLK cycle after the data is driven by the Flash memory. This bit allows the data is to be sampled later in order to account for external signal delays.
Page 326: Quadspi Device Configuration Register (Quadspi_Dcr)
Quad-SPI interface (QUADSPI) RM0430 12.5.2 QUADSPI device configuration register (QUADSPI_DCR) Address offset: 0x0004 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FSIZE[4:0] Res. Res. Res. Res. Res. CSHT[2:0] Res. Res. Res. Res. Res. Res.
Page 327: Quadspi Status Register (Quadspi_Sr)
RM0430 Quad-SPI interface (QUADSPI) 12.5.3 QUADSPI status register (QUADSPI_SR) Address offset: 0x0008 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FLEVEL[5:0] Res. Res. BUSY Bits 31:14 Reserved, must be kept at reset value. Bits 13:8 FLEVEL[5:0]: FIFO level This field gives the number of valid bytes which are being held in the FIFO.
Page 328: Quadspi Flag Clear Register (Quadspi_Fcr)
Quad-SPI interface (QUADSPI) RM0430 12.5.4 QUADSPI flag clear register (QUADSPI_FCR) Address offset: 0x000C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 329: Quadspi Communication Configuration Register (Quadspi_Ccr)
RM0430 Quad-SPI interface (QUADSPI) Bits 31:0 DL[31:0]: Data length Number of data to be retrieved (value+1) in indirect and status-polling modes. A value no greater than 3 (indicating 4 bytes) should be used for status-polling mode. All 1s in indirect mode means undefined length, where QUADSPI will continue until the end of memory, as defined by FSIZE.
Page 330 Quad-SPI interface (QUADSPI) RM0430 Bit 28 SIOO: Send instruction only once mode Section 12.3.12: Sending the instruction only once on page 319. This bit has no effect when IMODE = 00. 0: Send instruction on every transaction 1: Send instruction only for the first command This field can be written only when BUSY = 0.
Page 331: Quadspi Address Register (Quadspi_Ar)
RM0430 Quad-SPI interface (QUADSPI) Bits 13:12 ADSIZE[1:0]: Address size This bit defines address size: 00: 8-bit address 01: 16-bit address 10: 24-bit address 11: 32-bit address This field can be written only when BUSY = 0. Bits 11:10 ADMODE[1:0]: Address mode This field defines the address phase mode of operation: 00: No address 01: Address on a single line...
Page 332: Quadspi Alternate Bytes Registers (Quadspi_Abr)
Quad-SPI interface (QUADSPI) RM0430 12.5.8 QUADSPI alternate bytes registers (QUADSPI_ABR) Address offset: 0x001C Reset value: 0x0000 0000 ALTERNATE[31:16] ALTERNATE[15:0] Bits 31:0 ALTERNATE[31:0]: Alternate Bytes Optional data to be send to the external SPI device right after the address. This field can be written only when BUSY = 0. 12.5.9 QUADSPI data register (QUADSPI_DR) Address offset: 0x0020...
Page 333: Quadspi Polling Status Mask Register (Quadspi
RM0430 Quad-SPI interface (QUADSPI) 12.5.10 QUADSPI polling status mask register (QUADSPI _PSMKR) Address offset: 0x0024 Reset value: 0x0000 0000 MASK[31:16] MASK[15:0] Bits 31:0 MASK[31:0]: Status mask Mask to be applied to the status bytes received in polling mode. For bit n: 0: Bit n of the data received in automatic polling mode is masked and its value is not considered in the matching logic 1: Bit n of the data received in automatic polling mode is unmasked and its value is...
Page 334: Quadspi Polling Interval Register (Quadspi
Quad-SPI interface (QUADSPI) RM0430 12.5.12 QUADSPI polling interval register (QUADSPI _PIR) Address offset: 0x002C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. INTERVAL[15:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 INTERVAL[15:0]: Polling interval Number of CLK cycles between to read during automatic polling phases.
Page 335: Quadspi Register Map
RM0430 Quad-SPI interface (QUADSPI) 12.5.14 QUADSPI register map Table 73. QUADSPI register map and reset values Register Offset name FTHRES QUADSPI_CR PRESCALER[7:0] [4:0] 0x0000 Reset value QUADSPI_DCR FSIZE[4:0] CSHT 0x0004 Reset value QUADSPI_SR FLEVEL[6:0] 0x0008 Reset value QUADSPI_FCR 0x000C Reset value QUADSPI_DLR DL[31:0] 0x0010...
Page 336: Analog-To-Digital Converter (Adc)
Analog-to-digital converter (ADC) RM0430 Analog-to-digital converter (ADC) 13.1 ADC introduction The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 19 multiplexed channels allowing it to measure signals from 16 external sources, two internal sources, and the V channel.
Page 337: Figure 59. Single Adc Block Diagram
RM0430 Analog-to-digital converter (ADC) Figure 59. Single ADC block diagram RM0430 Rev 8 337/1324...
Page 338: Adc On-Off Control
Analog-to-digital converter (ADC) RM0430 Table 74. ADC pins Name Signal type Remarks Input, analog reference The higher/positive reference voltage for the ADC, REF+ positive 1.8 V ≤ V ≤ V REF+ Analog power supply equal to V Input, analog supply 2.4 V ≤V ≤V (3.6 V) for full speed...
Page 339: Single Conversion Mode
RM0430 Analog-to-digital converter (ADC) The total number of conversions in the injected group must be written in the L[1:0] bits in the ADC_JSQR register. If the ADC_SQRx or ADC_JSQR registers are modified during a conversion, the current conversion is reset and a new start pulse is sent to the ADC to convert the newly chosen group.
Page 340: Timing Diagram
Analog-to-digital converter (ADC) RM0430 mode (using JAUTO bit), refer to Auto-injection section) 13.3.6 Timing diagram As shown in Figure 60, the ADC needs a stabilization time of t before it starts STAB converting accurately. After the start of the ADC conversion and after 15 clock cycles, the EOC flag is set and the 16-bit ADC data register contains the result of the conversion.
Page 341: Scan Mode
RM0430 Analog-to-digital converter (ADC) Table 75. Analog watchdog channel selection ADC_CR1 register control bits (x = don’t care) Channels guarded by the analog watchdog AWDSGL bit AWDEN bit JAWDEN bit None All injected channels All regular channels All regular and injected channels Single injected channel Single...
Page 342: Discontinuous Mode
Analog-to-digital converter (ADC) RM0430 interrupted but the regular sequence is executed at the end of the injected sequence. Figure 62 shows the corresponding timing diagram. Note: When using triggered injection, one must ensure that the interval between trigger events is longer than the injection sequence.
Page 343: Data Alignment
RM0430 Analog-to-digital converter (ADC) Example: • n = 3, channels to be converted = 0, 1, 2, 3, 6, 7, 9, 10 • 1st trigger: sequence converted 0, 1, 2. An EOC event is generated at each conversion. • 2nd trigger: sequence converted 3, 6, 7. An EOC event is generated at each conversion •...
Page 344: Channel-Wise Programmable Sampling Time
Analog-to-digital converter (ADC) RM0430 Figure 63. Right alignment of 12-bit data Figure 64. Left alignment of 12-bit data Special case: when left-aligned, the data are aligned on a half-word basis except when the resolution is set to 6-bit. in that case, the data are aligned on a byte basis as shown in Figure Figure 65.
Page 345: Conversion On External Trigger And Trigger Polarity
RM0430 Analog-to-digital converter (ADC) 13.6 Conversion on external trigger and trigger polarity Conversion can be triggered by an external event (e.g. timer capture, EXTI line). If the EXTEN[1:0] control bits (for a regular conversion) or JEXTEN[1:0] bits (for an injected conversion) are different from “0b00”, then external events are able to trigger a conversion with the selected polarity.
Page 346: Fast Conversion Mode
Analog-to-digital converter (ADC) RM0430 Table 78 gives the possible external trigger for injected conversion. Table 78. External trigger for injected channels Source Connection type JEXTSEL[3:0] TIM1_CH4 event 0000 TIM1_TRGO event 0001 TIM2_CH1 event 0010 TIM2_TRGO event 0011 TIM3_CH2 event 0100 TIM3_CH4 event 0101 TIM4_CH1 event...
Page 347: Data Management
RM0430 Analog-to-digital converter (ADC) 13.8 Data management 13.8.1 Using the DMA Since converted regular channel values are stored into a unique data register, it is useful to use DMA for conversion of more than one regular channel. This avoids the loss of the data already stored in the ADC_DR register.
Page 348: Conversions Without Dma And Without Overrun Detection
Analog-to-digital converter (ADC) RM0430 13.8.3 Conversions without DMA and without overrun detection It may be useful to let the ADC convert one or more channels without reading the data each time (if there is an analog watchdog for instance). For that, the DMA must be disabled (DMA = 0) and the EOC bit must be set at the end of a sequence only (EOCS = 0).
Page 349: Battery Charge Monitoring
RM0430 Analog-to-digital converter (ADC) Reading the temperature To use the sensor: Select ADC1_IN18 input channel. Select a sampling time greater than the minimum sampling time specified in the datasheet. Set the TSVREFE bit in the ADC_CCR register to wake up the temperature sensor from power down mode Start the ADC conversion by setting the SWSTART bit (or by external trigger) Read the resulting V...
Page 350: Adc Interrupts
Analog-to-digital converter (ADC) RM0430 13.11 ADC interrupts An interrupt can be produced on the end of conversion for regular and injected groups, when the analog watchdog status bit is set and when the overrun status bit is set. Separate interrupt enable bits are available for flexibility. Two other flags are present in the ADC_SR register, but there is no interrupt associated with them: •...
Page 351: Adc Registers
RM0430 Analog-to-digital converter (ADC) 13.12 ADC registers Refer to for a list of abbreviations used in register descriptions. Section 1.2 on page 52 The peripheral registers must be written at word level (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). 13.12.1 ADC status register (ADC_SR) Address offset: 0x00...
Page 352: Adc Control Register 1 (Adc_Cr1)
Analog-to-digital converter (ADC) RM0430 13.12.2 ADC control register 1 (ADC_CR1) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. OVRIE AWDEN JAWDEN Res. Res. Res. Res. Res. Res. DISCNUM[2:0] JDISCEN DISCEN JAUTO AWDSGL SCAN JEOCIE AWDIE EOCIE AWDCH[4:0] Bits 31:27 Reserved, must be kept at reset value.
Page 353 RM0430 Analog-to-digital converter (ADC) Bit 11 DISCEN: Discontinuous mode on regular channels This bit is set and cleared by software to enable/disable Discontinuous mode on regular channels. 0: Discontinuous mode on regular channels disabled 1: Discontinuous mode on regular channels enabled Bit 10 JAUTO: Automatic injected group conversion This bit is set and cleared by software to enable/disable automatic injected group conversion after regular group conversion.
Page 354: Adc Control Register 2 (Adc_Cr2)
Analog-to-digital converter (ADC) RM0430 13.12.3 ADC control register 2 (ADC_CR2) Address offset: 0x08 Reset value: 0x0000 0000 Res. SWSTART EXTEN EXTSEL[3:0] Res. JSWSTART JEXTEN JEXTSEL[3:0] Res. Res. Res. Res. ALIGN EOCS Res. Res. Res. Res. Res. Res. CONT ADON Bit 31 Reserved, must be kept at reset value. Bit 30 SWSTART: Start conversion of regular channels This bit is set by software to start conversion and cleared by hardware as soon as the conversion starts.
Page 355 RM0430 Analog-to-digital converter (ADC) Bit 22 JSWSTART: Start conversion of injected channels This bit is set by software and cleared by hardware as soon as the conversion starts. 0: Reset state 1: Starts conversion of injected channels This bit can be set only when ADON = 1 otherwise no conversion is launched. Bits 21:20 JEXTEN: External trigger enable for injected channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group.
Page 356: Adc Sample Time Register 1 (Adc_Smpr1)
Analog-to-digital converter (ADC) RM0430 Bit 8 DMA: Direct memory access mode (for single ADC mode) This bit is set and cleared by software. Refer to the DMA controller chapter for more details. 0: DMA mode disabled 1: DMA mode enabled Bits 7:2 Reserved, must be kept at reset value.
Page 357: Adc Sample Time Register 2 (Adc_Smpr2)
RM0430 Analog-to-digital converter (ADC) 13.12.5 ADC sample time register 2 (ADC_SMPR2) Address offset: 0x10 Reset value: 0x0000 0000 Res. Res. SMP9[2:0] SMP8[2:0] SMP7[2:0] SMP6[2:0] SMP5[2:1] SMP5_0 SMP4[2:0] SMP3[2:0] SMP2[2:0] SMP1[2:0] SMP0[2:0] Bits 31:30 Reserved, must be kept at reset value. Bits 29:0 SMPx[2:0]: Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel.
Page 358: Adc Watchdog Lower Threshold Register (Adc_Ltr)
Analog-to-digital converter (ADC) RM0430 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. HT[11:0] Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 HT[11:0]: Analog watchdog higher threshold These bits are written by software to define the higher threshold for the analog watchdog.
Page 359: Adc Regular Sequence Register 2 (Adc_Sqr2)
RM0430 Analog-to-digital converter (ADC) Bits 31:24 Reserved, must be kept at reset value. Bits 23:20 L[3:0]: Regular channel sequence length These bits are written by software to define the total number of conversions in the regular channel conversion sequence. 0000: 1 conversion 0001: 2 conversions 1111: 16 conversions Bits 19:15 SQ16[4:0]: 16th conversion in regular sequence...
Page 360: Adc Regular Sequence Register 3 (Adc_Sqr3)
Analog-to-digital converter (ADC) RM0430 13.12.11 ADC regular sequence register 3 (ADC_SQR3) Address offset: 0x34 Reset value: 0x0000 0000 Res. Res. SQ6[4:0] SQ5[4:0] SQ4[4:1] SQ4_0 SQ3[4:0] SQ2[4:0] SQ1[4:0] Bits 31:30 Reserved, must be kept at reset value. Bits 29:25 SQ6[4:0]: 6th conversion in regular sequence These bits are written by software with the channel number (0..18) assigned as the 6th in the sequence to be converted.
Page 361: Adc Injected Sequence Register (Adc_Jsqr)
RM0430 Analog-to-digital converter (ADC) 13.12.12 ADC injected sequence register (ADC_JSQR) Address offset: 0x38 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. JL[1:0] JSQ4[4:1] JSQ4[0] JSQ3[4:0] JSQ2[4:0] JSQ1[4:0] Bits 31:22 Reserved, must be kept at reset value. Bits 21:20 JL[1:0]: Injected sequence length These bits are written by software to define the total number of conversions in the injected channel conversion sequence.
Page 362: Adc Regular Data Register (Adc_Dr)
Analog-to-digital converter (ADC) RM0430 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 JDATA[15:0]: Injected data These bits are read-only. They contain the conversion result from injected channel x. The data are left -or right-aligned as shown in Figure 63 Figure 13.12.14 ADC regular data register (ADC_DR)
Page 363: Adc Common Control Register (Adc_Ccr)
RM0430 Analog-to-digital converter (ADC) Bit 2 JEOC1: Injected channel end of conversion of ADC1 This bit is a copy of the JEOC bit in the ADC1_SR register. Bit 1 EOC1: End of conversion of ADC1 This bit is a copy of the EOC bit in the ADC1_SR register. Bit 0 AWD1: Analog watchdog flag of ADC1 This bit is a copy of the AWD bit in the ADC1_SR register.
Page 364: 13.12.17 Adc Register Map
Analog-to-digital converter (ADC) RM0430 13.12.17 ADC register map The following table summarizes the ADC registers. Table 80. ADC global register map Offset Register 0x000 - 0x04C ADC1 0x050 - 0x2FC Reserved 0x300 - 0x308 Common registers Table 81. ADC register map and reset values Offset Register ADC_SR...
Page 365: Table 82. Adc Register Map And Reset Values (Common Adc Registers)
RM0430 Analog-to-digital converter (ADC) Table 81. ADC register map and reset values (continued) Offset Register ADC_SQR3 Regular channel sequence SQx_x bits 0x34 Reset value ADC_JSQR JL[1:0] Injected channel sequence JSQx_x bits 0x38 Reset value ADC_JDR1 JDATA[15:0] 0x3C Reset value ADC_JDR2 JDATA[15:0] 0x40 Reset value...
Page 366: Digital-To-Analog Converter (Dac)
Digital-to-analog converter (DAC) RM0430 Digital-to-analog converter (DAC) 14.1 DAC introduction The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In 12-bit mode, the data could be left- or right-aligned.
Page 367: Table 83. Dac Pins
RM0430 Digital-to-analog converter (DAC) Figure 67. DAC channel block diagram DAC control register TSELx[2:0] bits SWTR IGx TIM2_T RGO DMAENx TIM4_T RGO TIM5_T RGO TIM6_T RGO TIM7_T RGO TIM8_T RGO EXTI_9 DM A req ue stx Control logicx TENx 12-bit DHRx MAMPx[3:0] bits trianglex...
Page 368: Dac Functional Description
Digital-to-analog converter (DAC) RM0430 14.3 DAC functional description 14.3.1 DAC channel enable Each DAC channel can be powered on by setting its corresponding ENx bit in the DAC_CR register. The DAC channel is then enabled after a startup time t WAKEUP Note: The ENx bit enables the analog DAC Channelx macrocell only.
Page 369: Dac Conversion
RM0430 Digital-to-analog converter (DAC) Figure 68. Data registers in single DAC channel mode • Dual DAC channels, there are three possibilities: – 8-bit right alignment: data for DAC channel1 to be loaded into the DAC_DHR8RD [7:0] bits (stored into the DHR1[11:4] bits) and data for DAC channel2 to be loaded into the DAC_DHR8RD [15:8] bits (stored into the DHR2[11:4] bits) –...
Page 370: Dac Output Voltage
Digital-to-analog converter (DAC) RM0430 When DAC_DORx is loaded with the DAC_DHRx contents, the analog output voltage becomes available after a time t that depends on the power supply voltage and the SETTLING analog output load. Figure 70. Timing diagram for conversion with trigger disabled TEN = 0 14.3.5 DAC output voltage Digital inputs are converted to output voltages on a linear conversion between 0 and V...
Page 371: Dma Request
RM0430 Digital-to-analog converter (DAC) If the software trigger is selected, the conversion starts once the SWTRIG bit is set. SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the DAC_DHRx register contents. Note: TSELx[2:0] bit cannot be changed when the ENx bit is set. When software trigger is selected, the transfer from the DAC_DHRx register to the DAC_DORx register takes only one APB1 clock cycle.
Page 372: Triangle-Wave Generation
Digital-to-analog converter (DAC) RM0430 Figure 71. DAC LFSR register calculation algorithm The LFSR value, that may be masked partially or totally by means of the MAMPx[3:0] bits in the DAC_CR register, is added up to the DAC_DHRx contents without overflow and this value is then stored into the DAC_DORx register.
Page 373: Dual Dac Channel Conversion
RM0430 Digital-to-analog converter (DAC) It is possible to reset triangle wave generation by resetting the WAVEx[1:0] bits. Figure 73. DAC triangle wave generation Figure 74. DAC conversion (SW trigger enabled) with triangle wave generation Note: The DAC trigger must be enabled for noise generation by setting the TENx bit in the DAC_CR register.
Page 374: Independent Trigger Without Wave Generation
Digital-to-analog converter (DAC) RM0430 14.4.1 Independent trigger without wave generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits •...
Page 375: Independent Trigger With Single Triangle Generation
RM0430 Digital-to-analog converter (DAC) 14.4.4 Independent trigger with single triangle generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits •...
Page 376: Simultaneous Trigger Without Wave Generation
Digital-to-analog converter (DAC) RM0430 14.4.7 Simultaneous trigger without wave generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits •...
Page 377: Simultaneous Trigger With Single Triangle Generation
RM0430 Digital-to-analog converter (DAC) 14.4.10 Simultaneous trigger with single triangle generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits •...
Page 378: Dac Registers
Digital-to-analog converter (DAC) RM0430 14.5 DAC registers Refer to Section 1.2: List of abbreviations for registers for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32 bits). 14.5.1 DAC control register (DAC_CR) Address offset: 0x00 Reset value: 0x0000 0000 DMAU...
Page 379 RM0430 Digital-to-analog converter (DAC) Bits 21:19 TSEL2[2:0]: DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 000: Timer 6 TRGO event 001: Timer 8 TRGO event 010: Timer 7 TRGO event 011: 5 TRGO event 100: Timer 2 TRGO event 101: Timer 4 TRGO event 110: External line9...
Page 380 Digital-to-analog converter (DAC) RM0430 Bits 11:8 MAMP1[3:0]: DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. 0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1 0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15...
Page 381: Dac Software Trigger Register (Dac_Swtrigr)
RM0430 Digital-to-analog converter (DAC) 14.5.2 DAC software trigger register (DAC_SWTRIGR) Address offset: 0x04 Reset value: 0x0000 0000 Reserved SWTRIG2 SWTRIG1 Reserved Bits 31:2 Reserved, must be kept at reset value. Bit 1 SWTRIG2: DAC channel2 software trigger This bit is set and cleared by software to enable/disable the software trigger. 0: Software trigger disabled 1: Software trigger enabled Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2...
Page 382: Dac Channel1 12-Bit Left Aligned Data Holding Register
Digital-to-analog converter (DAC) RM0430 14.5.4 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) Address offset: 0x0C Reset value: 0x0000 0000 Reserved DACC1DHR[11:0] Reserved Bits 31:16 Reserved, must be kept at reset value. Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.
Page 383: Dac Channel2 12-Bit Right Aligned Data Holding Register
RM0430 Digital-to-analog converter (DAC) 14.5.6 DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) Address offset: 0x14 Reset value: 0x0000 0000 Reserved DACC2DHR[11:0] Reserved Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.
Page 384: Dual Dac 12-Bit Right-Aligned Data Holding Register (Dac_Dhr12Rd)
Digital-to-analog converter (DAC) RM0430 14.5.9 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) Address offset: 0x20 Reset value: 0x0000 0000 DACC2DHR[11:0] Reserved DACC1DHR[11:0] Reserved Bits 31:28 Reserved, must be kept at reset value. Bits 27:16 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.
Page 385: Dual Dac 8-Bit Right Aligned Data Holding Register
RM0430 Digital-to-analog converter (DAC) 14.5.11 DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) Address offset: 0x28 Reset value: 0x0000 0000 Reserved DACC2DHR[7:0] DACC1DHR[7:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:8 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2.
Page 386: Dac Status Register (Dac_Sr)
Digital-to-analog converter (DAC) RM0430 14.5.14 DAC status register (DAC_SR) Address offset: 0x34 Reset value: 0x0000 0000 DMAUDR2 Reserved Reserved rc_w1 DMAUDR1 Reserved Reserved rc_w1 Bits 31:30 Reserved, must be kept at reset value. Bit 29 DMAUDR2: DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).
Page 387 RM0430 Digital-to-analog converter (DAC) Table 85. DAC register map (continued) Offset Register DAC_ 0x18 Reserved DACC2DHR[11:0] Reserved DHR12L2 DAC_ 0x1C Reserved DACC2DHR[7:0] DHR8R2 DAC_ 0x20 Reserved DACC2DHR[11:0] Reserved DACC1DHR[11:0] DHR12RD DAC_ 0x24 DACC2DHR[11:0] Reserved DACC1DHR[11:0] Reserved DHR12LD DAC_ 0x28 Reserved DACC2DHR[7:0] DACC1DHR[7:0] DHR8RD...
Page 388: Digital Filter For Sigma Delta Modulators (Dfsdm)
Digital filter for sigma delta modulators (DFSDM) RM0430 Digital filter for sigma delta modulators (DFSDM) 15.1 Introduction Digital filter for sigma delta modulators (DFSDM) is a high-performance module dedicated to interface external Σ∆ modulators to a microcontroller. It is featuring up to 8 external digital serial interfaces (channels) and up to 4 digital filters with flexible Sigma Delta stream digital processing options to offer up to 24-bit final ADC resolution.
Page 389: Dfsdm Main Features
RM0430 Digital filter for sigma delta modulators (DFSDM) 15.2 DFSDM main features • Up to 8 multiplexed input digital serial channels: – configurable SPI interface to connect various Σ∆ modulators – configurable Manchester coded 1 wire interface support – clock output for Σ∆ modulator(s) •...
Page 390: Dfsdm Implementation
Digital filter for sigma delta modulators (DFSDM) RM0430 15.3 DFSDM implementation This section describes the configuration implemented in DFSDMx. Table 86. DFSDMx implementation DFSDM features DFSDM1 DFSDM2 Number of channels Number of filters Input from internal ADC Supported trigger sources Pulses skipper ID registers support 1.
Page 391: Dfsdm Functional Description
RM0430 Digital filter for sigma delta modulators (DFSDM) 15.4 DFSDM functional description 15.4.1 DFSDM block diagram Figure 75. Single DFSDM block diagram RM0430 Rev 8 391/1324...
Page 392: Dfsdm Pins And Internal Signals
Digital filter for sigma delta modulators (DFSDM) RM0430 1. This example shows 4 DFSDM filters and 8 input channels (max. configuration). 15.4.2 DFSDM pins and internal signals Table 87. DFSDM external pins Name Signal Type Remarks Power supply Digital power supply. Power supply Digital ground power supply.
Page 393: Dfsdm Reset And Clocks
RM0430 Digital filter for sigma delta modulators (DFSDM) Table 90. DFSDM2 triggers connection Trigger name Trigger source dfsdm_jtrg0 TIM1_TRGO3 dfsdm_jtrg1 TIM3_TRGO3 dfsdm_jtrg2 TIM8_TRGO4 dfsdm_jtrg3 TIM10_OC1 dfsdm_jtrg4 TIM2_TRGO2 dfsdm_jtrg5 TIM4_TRGO4 dfsdm_jtrg6 TIM11_OC1 dfsdm_jtrg7 TIM6_TRGO2 dfsdm_jtrg8 TIM7_TRGO2 dfsdm_jtrg9 EXTI11 dfsdm_jtrg10 EXTI15 Table 91. DFSDM break connection Break name Break destination dfsdm_break[0]...
Page 394: Serial Channel Transceivers
Digital filter for sigma delta modulators (DFSDM) RM0430 DFSDM clocks The internal DFSDM clock f , which is used to drive the channel transceivers, DFSDMCLK digital processing blocks (digital filter, integrator) and next additional blocks (analog watchdog, short-circuit detector, extremes detector, control block) is generated by the RCC block and is derived from the system clock SYSCLK or peripheral clock PCLK2 (see DFSDMSEL bit description in ).
Page 395: Figure 76. Input Channel Pins Redirection
RM0430 Digital filter for sigma delta modulators (DFSDM) Figure 76. Input channel pins redirection Output clock generation A clock signal can be provided on CKOUT pin to drive external Σ∆ modulator clock inputs. The frequency of this CKOUT signal is derived from DFSDM clock or from audio clock (see CKOUTSRC bit in DFSDM_CH0CFGR1 register) divided by a predivider (see CKOUTDIV bits in DFSDM_CH0CFGR1 register).
Page 396 Digital filter for sigma delta modulators (DFSDM) RM0430 SPI data input format operation In SPI format, the data stream is sent in serial format through data and clock signals. Data signal is always provided from DATINy pin. A clock signal can be provided externally from CKINy pin or internally from a signal derived from the CKOUT signal source.
Page 397: Figure 77. Channel Transceiver Timing Diagrams
RM0430 Digital filter for sigma delta modulators (DFSDM) Figure 77. Channel transceiver timing diagrams RM0430 Rev 8 397/1324...
Page 398: Figure 78. Clock Absence Timing Diagram For Spi
Digital filter for sigma delta modulators (DFSDM) RM0430 Clock absence detection Channels serial clock inputs can be checked for clock absence/presence to ensure the correct operation of conversion and error reporting. Clock absence detection can be enabled or disabled on each input channel y by bit CKABEN in DFSDM_CHyCFGR1 register.
Page 399: Figure 79. Clock Absence Timing Diagram For Manchester Coding
RM0430 Digital filter for sigma delta modulators (DFSDM) The detection of a clock absence in Manchester coding (after a first successful synchronization) is based on changes comparison of coded serial data input signal with output clock generation (CKOUT signal). There must be a voltage level change on DATINy pin during 2 periods of CKOUT signal (which is controlled by CKOUTDIV bits in DFSDM_CH0CFGR1 register).
Page 400 Digital filter for sigma delta modulators (DFSDM) RM0430 Manchester/SPI code synchronization The Manchester coded stream must be synchronized the first time after enabling the channel (CHEN=1 in DFSDM_CHyCFGR1 register). The synchronization ends when a data transition from 0 to 1 or from 1 to 0 (to be able to detect valid data edge) is received. The end of the synchronization can be checked by polling CKABF[y]=0 for a given channel after it has been cleared by CLRCKABF[y] in DFSDM_FLT0ICR, following the software sequence detailed hereafter:...
Page 401: Figure 80. First Conversion For Manchester Coding (Manchester Synchronization)
RM0430 Digital filter for sigma delta modulators (DFSDM) Figure 80. First conversion for Manchester coding (Manchester synchronization) External serial clock frequency measurement The measuring of a channel serial clock input frequency provides a real data rate from an external Σ∆ modulator, which is important for application purposes. An external serial clock input frequency can be measured by a timer counting DFSDM clocks (f ) during one conversion duration.
Page 402 Digital filter for sigma delta modulators (DFSDM) RM0430 Note: When conversion is interrupted (e.g. by disabling/enabling the selected channel) the interruption time is also counted in CNVCNT[27:0]. Therefore it is recommended to not interrupt the conversion for correct conversion duration result. Conversion times: injected conversion or regular conversion with FAST = 0 (or first conversion if FAST=1):...
Page 403 RM0430 Digital filter for sigma delta modulators (DFSDM) the final output sample (and next samples) from filter will be calculated from later input data. This final sample then looks a bit in forward - because it is calculated from newer input samples than the “non-skipped”...
Page 404: Figure 81. Multi-Channel Delay Block For Pulse Skipping
Digital filter for sigma delta modulators (DFSDM) RM0430 Figure 81. Multi-channel delay block for pulse skipping 404/1324 RM0430 Rev 8...
Page 405: Figure 82. Pulses Skipper Operation
RM0430 Digital filter for sigma delta modulators (DFSDM) The DFSDM shall be configured as follow: • CHINSEL must be set to 0 for all channels (channel data are taken from pins of the same channel) • SPICKSEL must be set to 0 for all channels (in order to select external CKINy as input clock) The TIM3 and TIM4 shall be configured as follow: •...
Page 406: Table 92. Demultiplexers (Dm[6:1]) Operation
Digital filter for sigma delta modulators (DFSDM) RM0430 Table 92. Demultiplexers (DM[6:1]) operation Control Output 0 Output 1 input input Table 93. Use-cases examples for beamforming applications Use cases Multiplexer/ gate on schematic Speech recognition_1 OFF OFF OFF ON x x x x x x x x x x 0 0 x x x x x 0 0 Beamforming4_ OFF ON ON OFF 1 1 0 0 0 0 x x 1 1 1 0 x x x x x 0 1...
Page 407: Configuring The Input Serial Interface
RM0430 Digital filter for sigma delta modulators (DFSDM) 15.4.5 Configuring the input serial interface The following parameters must be configured for the input serial interface: • Output clock predivider. There is a programmable predivider to generate the output clock from DFSDM clock (2 - 256). It is defined by CKOUTDIV[7:0] bits in DFSDM_CH0CFGR1 register.
Page 408 Digital filter for sigma delta modulators (DFSDM) RM0430 address is the address of DFSDM_CHyDATINR register. Data are transferred at DMA transfer speed from memory to DFSDM parallel input. This DMA transfer is different from DMA used to read DFSDM conversion results. Both DMA can be used at the same time - first DMA (configured as memory-to-memory transfer) for input data writings and second DMA (configured as peripheral-to-memory transfer) for data results reading.
Page 409: Channel Selection
RM0430 Digital filter for sigma delta modulators (DFSDM) Figure 83. DFSDM_CHyDATINR registers operation modes and assignment The write into DFSDM_CHyDATINR register to load one or two samples must be performed after the selected input channel (channel y) is enabled for data collection (starting conversion for channel y).
Page 410: Digital Filter Configuration
Digital filter for sigma delta modulators (DFSDM) RM0430 15.4.8 Digital filter configuration DFSDM contains a Sinc type digital filter implementation. This Sinc filter performs an input digital data stream filtering, which results in decreasing the output data rate (decimation) and increasing the output data resolution. The Sinc digital filter is configurable in order to reach the required output data rates and required output data resolution.
Page 411: Integrator Unit
RM0430 Digital filter for sigma delta modulators (DFSDM) Table 94. Filter maximum output resolution (peak data values from filter output) for some FOSR values FOSR Sinc Sinc FastSinc Sinc Sinc Sinc +/- x +/- x +/- 2x +/- x +/- x +/- x +/- 4 +/- 16...
Page 412 Digital filter for sigma delta modulators (DFSDM) RM0430 Analog watchdog conversions on input channels are independent from standard conversions. In this case, the analog watchdog uses its own filters and signal processing on each input channel independently from the main injected or regular conversions. Analog watchdog conversions are performed in a continuous mode on the selected input channels in order to watch channels also when main injected or regular conversions are paused (RCIP = 0, JCIP = 0).
Page 413 RM0430 Digital filter for sigma delta modulators (DFSDM) AWHTF[7:0], AWLTF[7:0] of DFSDM_FLTxAWSR register). Each channel request is executed in 8 DFSDM clock cycles. So, the bandwidth from each channel is limited to 8 DFSDM clock cycles (if AWDCH[7:0] = 0xFF). Because the maximum input channel sampling clock frequency is the DFSDM clock frequency divided by 4, the configuration AWFOSR = 0 (analog watchdog filter is bypassed) cannot be used for analog watchdog feature at this input clock speed.
Page 414: Short-Circuit Detector
Digital filter for sigma delta modulators (DFSDM) RM0430 15.4.11 Short-circuit detector The purpose of a short-circuit detector is to signalize with a very fast response time if an analog signal reached saturated values (out of full scale ranges) and remained on this value given time.
Page 415: Data Unit Block
RM0430 Digital filter for sigma delta modulators (DFSDM) 15.4.13 Data unit block The data unit block is the last block of the whole processing path: External Σ∆ modulators - Serial transceivers - Sinc filter - Integrator - Data unit block. The output data rate depends on the serial data stream rate, and filter and integrator settings.
Page 416: Signed Data Format
Digital filter for sigma delta modulators (DFSDM) RM0430 Note: In case of filter and integrator bypass (IOSR[7:0]=0, FOSR[9:0]=0), the input data rate ) must be limited to be able to read all output data: DATAIN_RATE ≤ f DATAIN_RATE where f is the bus frequency to which the DFSDM peripheral is connected.
Page 417: Continuous And Fast Continuous Modes
RM0430 Digital filter for sigma delta modulators (DFSDM) already been issued but not yet completed. A regular conversion can be pending if it was interrupted by an injected conversion or if it was started while an injected conversion was in progress.
Page 418: Power Optimization In Run Mode
Digital filter for sigma delta modulators (DFSDM) RM0430 An injected conversion cannot be launched if another injected conversion is pending or already in progress: any request to launch an injected conversion (either by JSWSTART or by a trigger) is ignored as long as bit JCIP is ‘1’ (in the DFSDM_FLTxISR register). Similarly, a regular conversion cannot be launched if another regular conversion is pending or already in progress: any request to launch a regular conversion (using RSWSTART) is ignored as long as bit RCIP is ‘1’...
Page 419: Table 96. Dfsdm Interrupt Requests
RM0430 Digital filter for sigma delta modulators (DFSDM) – enabled by JOVRIE bit in DFSDM_FLTxCR2 register – indicated in JOVRF bit in DFSDM_FLTxISR register – cleared by writing ‘1’ into CLRJOVRF bit in DFSDM_FLTxICR register • Data overrun interrupt for regular conversions: –...
Page 420: Dfsdm Dma Transfer
Digital filter for sigma delta modulators (DFSDM) RM0430 Table 96. DFSDM interrupt requests (continued) Event/Interrupt clearing Interrupt enable Interrupt event Event flag method control bit Regular data overrun ROVRF writing CLRROVRF = 1 ROVRIE AWDF, writing CLRAWHTF[7:0] = 1 AWDIE, Analog watchdog AWHTF[7:0], writing CLRAWLTF[7:0] = 1...
Page 421 RM0430 Digital filter for sigma delta modulators (DFSDM) Bit 31 DFSDMEN: Global enable for DFSDM interface 0: DFSDM interface disabled 1: DFSDM interface enabled If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1).
Page 422 Digital filter for sigma delta modulators (DFSDM) RM0430 Bits 13:12 DATMPX[1:0]: Input data multiplexer for channel y 0: Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected. 1: Reserved 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting.
Page 423: Dfsdm Channel Y Configuration Register (Dfsdm_Chycfgr2)
RM0430 Digital filter for sigma delta modulators (DFSDM) 15.7.2 DFSDM channel y configuration register (DFSDM_CHyCFGR2) This register specifies the parameters used by channel y. Address offset: 0x04 + 0x20 * y, (y = 0 to 7) Reset value: 0x0000 0000 OFFSET[23:8] OFFSET[7:0] DTRBS[4:0]...
Page 424: Dfsdm Channel Y Watchdog Filter Data Register (Dfsdm_Chywdatr)
Digital filter for sigma delta modulators (DFSDM) RM0430 Bits 31:24 Reserved, must be kept at reset value. Bits 23:22 AWFORD[1:0]: Analog watchdog Sinc filter order on channel y 0: FastSinc filter type 1: Sinc filter type 2: Sinc filter type 3: Sinc filter type FOSR...
Page 425: Dfsdm Channel Y Data Input Register (Dfsdm_Chydatinr)
RM0430 Digital filter for sigma delta modulators (DFSDM) Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 WDATA[15:0]: Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).
Page 426: Dfsdm Filter X Module Registers (X=0
Digital filter for sigma delta modulators (DFSDM) RM0430 15.8 DFSDM filter x module registers (x=0..3) 15.8.1 DFSDM filter x control register 1 (DFSDM_FLTxCR1) Address offset: 0x100 + 0x80 * x, (x = 0 to 3) Reset value: 0x0000 0000 RDMA RCON Res.
Page 427 RM0430 Digital filter for sigma delta modulators (DFSDM) Bit 21 RDMAEN: DMA channel enabled to read data for the regular conversion 0: The DMA channel is not enabled to read regular data 1: The DMA channel is enabled to read regular data This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Page 428 Digital filter for sigma delta modulators (DFSDM) RM0430 DFSDM2_FLT0 DFSDM2_FLT1 DFSDM2_FLT2 DFSDM2_FLT3 0x00 dfsdm_jtrg0 dfsdm_jtrg0 dfsdm_jtrg0 dfsdm_jtrg0 0x01 dfsdm_jtrg1 dfsdm_jtrg1 dfsdm_jtrg1 dfsdm_jtrg1 0x02 dfsdm_jtrg2 dfsdm_jtrg2 dfsdm_jtrg2 dfsdm_jtrg2 0x03 dfsdm_jtrg3 dfsdm_jtrg3 dfsdm_jtrg3 dfsdm_jtrg4 0x04 dfsdm_jtrg5 dfsdm_jtrg5 dfsdm_jtrg5 dfsdm_jtrg6 0x05 dfsdm_jtrg7 dfsdm_jtrg7 dfsdm_jtrg8 dfsdm_jtrg8 0x06...
Page 429: Dfsdm Filter X Control Register 2 (Dfsdm_Fltxcr2)
RM0430 Digital filter for sigma delta modulators (DFSDM) 15.8.2 DFSDM filter x control register 2 (DFSDM_FLTxCR2) Address offset: 0x104 + 0x80 * x, (x = 0 to 3) Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. AWDCH[7:0] CKAB ROVR...
Page 430: Dfsdm Filter X Interrupt And Status Register (Dfsdm_Fltxisr)
Digital filter for sigma delta modulators (DFSDM) RM0430 Bit 2 JOVRIE: Injected data overrun interrupt enable 0: Injected data overrun interrupt is disabled 1: Injected data overrun interrupt is enabled Please see the explanation of JOVRF in DFSDM_FLTxISR. Bit 1 REOCIE: Regular end of conversion interrupt enable 0: Regular end of conversion interrupt is disabled 1: Regular end of conversion interrupt is enabled Please see the explanation of REOCF in DFSDM_FLTxISR.
Page 431 RM0430 Digital filter for sigma delta modulators (DFSDM) Bit 13 JCIP: Injected conversion in progress status 0: No request to convert the injected channel group (neither by software nor by trigger) has been issued 1: The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to ‘1’...
Page 432: Dfsdm Filter X Interrupt Flag Clear Register (Dfsdm_Fltxicr)
Digital filter for sigma delta modulators (DFSDM) RM0430 15.8.4 DFSDM filter x interrupt flag clear register (DFSDM_FLTxICR) Address offset: 0x10C + 0x80 * x, (x = 0 to 3) Reset value: 0x0000 0000 CLRSCDF[7:0] CLRCKABF[7:0] rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1...
Page 433: Dfsdm Filter X Injected Channel Group Selection Register (Dfsdm_Fltxjchgr)
RM0430 Digital filter for sigma delta modulators (DFSDM) 15.8.5 DFSDM filter x injected channel group selection register (DFSDM_FLTxJCHGR) Address offset: 0x110 + 0x80 * x, (x = 0 to 3) Reset value: 0x0000 0001 Res. Res. Res. Res. Res. Res. Res.
Page 434: Dfsdm Filter X Data Register For Injected Group (Dfsdm_Fltxjdatar)
Digital filter for sigma delta modulators (DFSDM) RM0430 Bits 31:29 FORD[2:0]: Sinc filter order 0: FastSinc filter type 1: Sinc filter type 2: Sinc filter type 3: Sinc filter type 4: Sinc filter type 5: Sinc filter type 6-7: Reserved FOSR ⎛...
Page 435: Dfsdm Filter X Data Register For The Regular Channel (Dfsdm_Fltxrdatar)
RM0430 Digital filter for sigma delta modulators (DFSDM) Bits 31:8 JDATA[23:0]: Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF. Bits 7:3 Reserved, must be kept at reset value.
Page 436: Dfsdm Filter X Analog Watchdog High Threshold Register (Dfsdm_Fltxawhtr)
Digital filter for sigma delta modulators (DFSDM) RM0430 15.8.9 DFSDM filter x analog watchdog high threshold register (DFSDM_FLTxAWHTR) Address offset: 0x120 + 0x80 * x, (x = 0 to 3) Reset value: 0x0000 0000 AWHT[23:8] AWHT[7:0] Res. Res. Res. Res. BKAWH[3:0] Bits 31:8 AWHT[23:0]: Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog.
Page 437: Dfsdm Filter X Analog Watchdog Status Register
RM0430 Digital filter for sigma delta modulators (DFSDM) Bits 31:8 AWLT[23:0]: Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution).
Page 438: Dfsdm Filter X Analog Watchdog Clear Flag Register
Digital filter for sigma delta modulators (DFSDM) RM0430 15.8.12 DFSDM filter x analog watchdog clear flag register (DFSDM_FLTxAWCFR) Address offset: 0x12C + 0x80 * x, (x = 0 to 3) Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res.
Page 439: Dfsdm Filter X Extremes Detector Minimum Register
RM0430 Digital filter for sigma delta modulators (DFSDM) 15.8.14 DFSDM filter x extremes detector minimum register (DFSDM_FLTxEXMIN) Address offset: 0x134 + 0x80 * x, (x = 0 to 3) Reset value: 0x7FFF FF00 EXMIN[23:8] rc_r rs_r rs_r rs_r rs_r rs_r rs_r rs_r rs_r...
Page 440: Dfsdm Register Map
Digital filter for sigma delta modulators (DFSDM) RM0430 Bits 31:4 CNVCNT[27:0]: 28-bit timer counting conversion time t = CNVCNT[27:0] / f DFSDMCLK The timer has an input clock from DFSDM clock (system clock ). Conversion time DFSDMCLK measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample).
Page 441 RM0430 Digital filter for sigma delta modulators (DFSDM) Table 97. DFSDM register map and reset values (continued) Register Offset name DFSDM_ OFFSET[23:0] DTRBS[4:0] CH1CFGR2 0x24 reset value DFSDM_ AWFOSR[4:0] BKSCD[3:0] SCDT[7:0] CH1AWSCDR 0x28 reset value DFSDM_ WDATA[15:0] CH1WDATR 0x2C reset value DFSDM_ INDAT1[15:0] INDAT0[15:0]...
Page 442 Digital filter for sigma delta modulators (DFSDM) RM0430 Table 97. DFSDM register map and reset values (continued) Register Offset name DFSDM_ AWFOSR[4:0] BKSCD[3:0] SCDT[7:0] CH3AWSCDR 0x68 reset value DFSDM_ WDATA[15:0] CH3WDATR 0x6C reset value DFSDM_ INDAT1[15:0] INDAT0[15:0] CH3DATINR 0x70 reset value 0x74 - Reserved 0x7C...
Page 443 RM0430 Digital filter for sigma delta modulators (DFSDM) Table 97. DFSDM register map and reset values (continued) Register Offset name DFSDM_ WDATA[15:0] CH5WDATR 0xAC reset value DFSDM_ INDAT1[15:0] INDAT0[15:0] CH5DATINR 0xB0 reset value 0xB4 - Reserved 0xBC DFSDM_ CH6CFGR1 0xC0 reset value DFSDM_ OFFSET[23:0]...
Page 444 Digital filter for sigma delta modulators (DFSDM) RM0430 Table 97. DFSDM register map and reset values (continued) Register Offset name 0xF4 - Reserved 0xFC DFSDM_ RCH[2:0] FLT0CR1 0x100 reset value DFSDM_ AWDCH[7:0] EXCH[7:0] FLT0CR2 0x104 reset value DFSDM_ SCDF[7:0] CKABF[7:0] FLT0ISR 0x108 reset value...
Page 445 RM0430 Digital filter for sigma delta modulators (DFSDM) Table 97. DFSDM register map and reset values (continued) Register Offset name DFSDM_ EXMAX[23:0] FLT0EXMAX 0x130 reset value DFSDM_ EXMIN[23:0] FLT0EXMIN 0x134 reset value DFSDM_ CNVCNT[27:0] FLT0CNVTIMR 0x138 reset value 0x13C - Reserved 0x17C DFSDM_...
Page 446 Digital filter for sigma delta modulators (DFSDM) RM0430 Table 97. DFSDM register map and reset values (continued) Register Offset name DFSDM_ RDATA RDATA[23:0] FLT1RDATAR CH[2:0] 0x19C reset value DFSDM_ AWHT[23:0] BKAWH[3:0] FLT1AWHTR 0x1A0 reset value DFSDM_ AWLT[23:0] BKAWL[3:0] FLT1AWLTR 0x1A4 reset value DFSDM_ AWHTF[7:0]...
Page 447 RM0430 Digital filter for sigma delta modulators (DFSDM) Table 97. DFSDM register map and reset values (continued) Register Offset name DFSDM_ JCHG[7:0] FLT2JCHGR 0x210 reset value DFSDM_ FOSR[9:0] IOSR[7:0] FLT2FCR 0x214 reset value DFSDM_ JDATA[23:0] FLT2JDATAR 0x218 reset value DFSDM_ RDATA RDATA[23:0] FLT2RDATAR...
Page 448 Digital filter for sigma delta modulators (DFSDM) RM0430 Table 97. DFSDM register map and reset values (continued) Register Offset name DFSDM_ AWDCH[7:0] EXCH[7:0] FLT3CR2 0x284 reset value DFSDM_ FLT3ISR 0x288 reset value DFSDM_ FLT3ICR 0x28C reset value DFSDM_ JCHG[7:0] FLT3JCHGR 0x290 reset value DFSDM_...
Page 449 RM0430 Digital filter for sigma delta modulators (DFSDM) Table 97. DFSDM register map and reset values (continued) Register Offset name DFSDM_ EXMIN[23:0] FLT3EXMIN 0x2B4 reset value DFSDM_ CNVCNT[27:0] FLT3CNVTIMR 0x2B8 reset value 0x2BC - Reserved 0x3FC Refer to Section 2.2.2 on page 58 for the register boundary addresses.
Page 450: True Random Number Generator (Rng)
True random number generator (RNG) RM0430 True random number generator (RNG) 16.1 Introduction The RNG is a true random number generator that continuously provides 32-bit entropy samples, based on an analog noise source. It can be used by the application as a live entropy source to build a NIST compliant Deterministic Random Bit Generator (DRBG).
Page 451: Rng Functional Description
RM0430 True random number generator (RNG) 16.3 RNG functional description 16.3.1 RNG block diagram Figure 85 shows the RNG block diagram. Figure 85. RNG block diagram 16.3.2 RNG internal signals Table 98 describes a list of useful-to-know internal signals available at the RNG level, not at the STM32 product level (on pads).
Page 452: Random Number Generation
True random number generator (RNG) RM0430 16.3.3 Random number generation The true random number generator (RNG) delivers truly random data through its AHB interface at deterministic intervals. The RNG implements the entropy source model pictured Figure 86, and provides three main functions to the application: •...
Page 453 RM0430 True random number generator (RNG) Section 16.4: RNG low-power usage. • A sampling stage of these outputs clocked by a dedicated clock input (rng_clk), delivering a 2-bit raw data output. This noise source sampling is independent to the AHB interface clock frequency (rng_hclk).
Page 454: Rng Initialization
True random number generator (RNG) RM0430 Health checks This component ensures that the entire entropy source (with its noise source) starts then operates as expected, obtaining assurance that failures are caught quickly and with a high probability and reliability. The RNG implements the following health check features: Behavior tests, applied to the entropy source at run-time –...
Page 455: Rng Clocking
RM0430 True random number generator (RNG) To run the RNG in polling mode following steps are recommended: Enable the random number generation by setting the RNGEN bit to “1” in the RNG_CR register. Read the RNG_SR register and check that: –...
Page 456: Rng Low-Power Usage
True random number generator (RNG) RM0430 Noise source error detection When a noise source (or seed) error occurs, the RNG stops generating random numbers and sets to “1” both SEIS and SECS bits to indicate that a seed error occurred. If a value is available in the RNG_DR register, it must not be used as it may not have enough entropy.
Page 457: Entropy Source Validation
RM0430 True random number generator (RNG) 16.7 Entropy source validation 16.7.1 Introduction In order to assess the amount of entropy available from the RNG, STMicroelectronics has tested the peripheral against AIS-31 PTG.2 set of tests. The results can be provided on demand or the customer can reproduce the measurements using the AIS reference software.
Page 458: Rng Registers
True random number generator (RNG) RM0430 16.8 RNG registers The RNG is associated with a control register, a data register and a status register. 16.8.1 RNG control register (RNG_CR) Address offset: 0x000 Reset value: 0x0000 0000 Res. Res. Res. Res. Res.
Page 459: Rng Status Register (Rng_Sr)
RM0430 True random number generator (RNG) 16.8.2 RNG status register (RNG_SR) Address offset: 0x004 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 460: Rng Data Register (Rng_Dr)
True random number generator (RNG) RM0430 16.8.3 RNG data register (RNG_DR) Address offset: 0x008 Reset value: 0x0000 0000 The RNG_DR register is a read-only register that delivers a 32-bit random value when read. After being read this register delivers a new random value after 42 periods of RNG clock if the output FIFO is empty.
Page 461: Rng Register Map
RM0430 True random number generator (RNG) 16.8.4 RNG register map Table 100 gives the RNG register map and reset values. Table 100. RNG register map and reset map Offset Register name RNG_CR 0x000 Reset value RNG_SR 0x004 Reset value 0 0 0 RNG_DR RNDATA[31:0] 0x008...
Page 462: Advanced-Control Timers (Tim1&Tim8)
Advanced-control timers (TIM1&TIM8) RM0430 Advanced-control timers (TIM1&TIM8) 17.1 TIM1&TIM8 introduction The advanced-control timer (TIM1&TIM8) consist of a 16-bit auto-reload counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse length of input signals (input capture) or generating output waveforms (output compare, PWM, complementary PWM with dead-time insertion).
Page 463: Figure 87. Advanced-Control Timer Block Diagram
RM0430 Advanced-control timers (TIM1&TIM8) Figure 87. Advanced-control timer block diagram RM0430 Rev 8 463/1324...
Page 464: Tim1&Tim8 Functional Description
Advanced-control timers (TIM1&TIM8) RM0430 17.3 TIM1&TIM8 functional description 17.3.1 Time-base unit The main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler.
Page 465: Figure 88. Counter Timing Diagram With Prescaler Division Change From 1 To 2
RM0430 Advanced-control timers (TIM1&TIM8) Figure 88. Counter timing diagram with prescaler division change from 1 to 2 Figure 89. Counter timing diagram with prescaler division change from 1 to 4 RM0430 Rev 8 465/1324...
Page 466: Counter Modes
Advanced-control timers (TIM1&TIM8) RM0430 17.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. If the repetition counter is used, the update event (UEV) is generated after upcounting is repeated for the number of times programmed in the repetition counter register plus one (TIMx_RCR+1).
Page 467: Figure 91. Counter Timing Diagram, Internal Clock Divided By 2
RM0430 Advanced-control timers (TIM1&TIM8) Figure 91. Counter timing diagram, internal clock divided by 2 Figure 92. Counter timing diagram, internal clock divided by 4 Figure 93. Counter timing diagram, internal clock divided by N RM0430 Rev 8 467/1324...
Page 468: Figure 94. Counter Timing Diagram, Update Event When Arpe=0
Advanced-control timers (TIM1&TIM8) RM0430 Figure 94. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) Figure 95. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) 468/1324 RM0430 Rev 8...
Page 469 RM0430 Advanced-control timers (TIM1&TIM8) Downcounting mode In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event. If the repetition counter is used, the update event (UEV) is generated after downcounting is repeated for the number of times programmed in the repetition counter register plus one (TIMx_RCR+1).
Page 470: Figure 96. Counter Timing Diagram, Internal Clock Divided By 1
Advanced-control timers (TIM1&TIM8) RM0430 Figure 96. Counter timing diagram, internal clock divided by 1 Figure 97. Counter timing diagram, internal clock divided by 2 470/1324 RM0430 Rev 8...
Page 471: Figure 98. Counter Timing Diagram, Internal Clock Divided By 4
RM0430 Advanced-control timers (TIM1&TIM8) Figure 98. Counter timing diagram, internal clock divided by 4 Figure 99. Counter timing diagram, internal clock divided by N RM0430 Rev 8 471/1324...
Page 472: Figure 100. Counter Timing Diagram, Update Event When Repetition Counter Is Not Used
Advanced-control timers (TIM1&TIM8) RM0430 Figure 100. Counter timing diagram, update event when repetition counter is not used Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register) – 1, generates a counter overflow event, then counts from the auto- reload value down to 1 and generates a counter underflow event.
Page 473: Figure 101. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr = 0X6
RM0430 Advanced-control timers (TIM1&TIM8) DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): •...
Page 474: Figure 103. Counter Timing Diagram, Internal Clock Divided By 4, Timx_Arr=0X36
Advanced-control timers (TIM1&TIM8) RM0430 Figure 103. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 Center-aligned mode 2 or 3 is used with an UIF on overflow. Figure 104. Counter timing diagram, internal clock divided by N 474/1324 RM0430 Rev 8...
Page 475: Repetition Counter
RM0430 Advanced-control timers (TIM1&TIM8) Figure 105. Counter timing diagram, update event with ARPE=1 (counter underflow) Figure 106. Counter timing diagram, update event with ARPE=1 (counter overflow) 17.3.3 Repetition counter Section 17.3.1: Time-base unit describes how the update event (UEV) is generated with respect to the counter overflows/underflows.
Page 476 Advanced-control timers (TIM1&TIM8) RM0430 The repetition counter is decremented: • At each counter overflow in upcounting mode, • At each counter underflow in downcounting mode, • At each counter overflow and at each counter underflow in center-aligned mode. Although this limits the maximum number of repetition to 128 PWM cycles, it makes it possible to update the duty cycle twice per PWM period.
Page 477: Figure 107. Update Rate Examples Depending On Mode And Timx_Rcr Register Settings
RM0430 Advanced-control timers (TIM1&TIM8) Figure 107. Update rate examples depending on mode and TIMx_RCR register settings RM0430 Rev 8 477/1324...
Page 478: Clock Selection
Advanced-control timers (TIM1&TIM8) RM0430 17.3.4 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin • External clock mode2: external trigger input ETR • Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for example, you can configure Timer 1 to act as a prescaler for Timer 2.
Page 479: Figure 109. Ti2 External Clock Connection Example
RM0430 Advanced-control timers (TIM1&TIM8) Figure 109. TI2 external clock connection example For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register.
Page 480: Figure 110. Control Circuit In External Clock Mode 1
Advanced-control timers (TIM1&TIM8) RM0430 Figure 110. Control circuit in external clock mode 1 External clock source mode 2 This mode is selected by writing ECE=1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR. Figure 111 gives an overview of the external trigger input block.
Page 481: Capture/Compare Channels
RM0430 Advanced-control timers (TIM1&TIM8) As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
Page 482: Figure 113. Capture/Compare Channel (Example: Channel 1 Input Stage)
Advanced-control timers (TIM1&TIM8) RM0430 Figure 113. Capture/compare channel (example: channel 1 input stage) The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain. Figure 114. Capture/compare channel 1 main circuit 482/1324 RM0430 Rev 8...
Page 483: Figure 115. Output Stage Of Capture/Compare Channel (Channels 1 To 3)
RM0430 Advanced-control timers (TIM1&TIM8) Figure 115. Output stage of capture/compare channel (channels 1 to 3) Figure 116. Output stage of capture/compare channel (channel 4) The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register.
Page 484: Input Capture Mode
Advanced-control timers (TIM1&TIM8) RM0430 17.3.6 Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled.
Page 485: Pwm Input Mode
RM0430 Advanced-control timers (TIM1&TIM8) 17.3.7 PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. • These 2 ICx signals are active on edges with opposite polarity. •...
Page 486: Output Compare Mode
Advanced-control timers (TIM1&TIM8) RM0430 To force an output compare signal (OCXREF/OCx) to its active level, you just need to write 101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit. For example: CCxP=0 (OCx active high) =>...
Page 487: Pwm Mode
RM0430 Advanced-control timers (TIM1&TIM8) Figure 118. Output compare mode, toggle on OC1. 17.3.10 PWM mode Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
Page 488: Figure 119. Edge-Aligned Pwm Waveforms (Arr=8)
Advanced-control timers (TIM1&TIM8) RM0430 PWM edge-aligned mode • Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to Upcounting mode. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT <...
Page 489: Figure 120. Center-Aligned Pwm Waveforms (Arr=8)
RM0430 Advanced-control timers (TIM1&TIM8) Figure 120 shows some center-aligned PWM waveforms in an example where: • TIMx_ARR=8, • PWM mode is the PWM mode 1, • The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for CMS=01 in TIMx_CR1 register. Figure 120.
Page 490: Complementary Outputs And Dead-Time Insertion
Advanced-control timers (TIM1&TIM8) RM0430 Hints on using center-aligned mode: • When starting in center-aligned mode, the current up-down configuration is used. It means that the counter counts up or down depending on the value written in the DIR bit in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software.
Page 491: Figure 121. Complementary Output With Dead-Time Insertion
RM0430 Advanced-control timers (TIM1&TIM8) Figure 121. Complementary output with dead-time insertion. Figure 122. Dead-time waveforms with delay greater than the negative pulse. Figure 123. Dead-time waveforms with delay greater than the positive pulse. The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the TIMx_BDTR register.
Page 492: Using The Break Function
Advanced-control timers (TIM1&TIM8) RM0430 are to have both outputs at inactive level or both outputs active and complementary with dead-time. Note: When only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented and becomes active as soon as OCxREF is high. For example, if CCxNP=0 then OCxN=OCxRef. On the other hand, when both OCx and OCxN are enabled (CCxE=CCxNE=1) OCx becomes active when OCxREF is high whereas OCxN is complemented and becomes active when OCxREF is low.
Page 493 RM0430 Advanced-control timers (TIM1&TIM8) active level together. Note that because of the resynchronization on MOE, the dead-time duration is a bit longer than usual (around 2 ck_tim clock cycles). – If OSSI=0 then the timer releases the enable outputs else the enable outputs remain or become high as soon as one of the CCxE or CCxNE bits is high.
Page 494: Figure 124. Output Behavior In Response To A Break
Advanced-control timers (TIM1&TIM8) RM0430 Figure 124. Output behavior in response to a break. 494/1324 RM0430 Rev 8...
Page 495: Clearing The Ocxref Signal On An External Event
RM0430 Advanced-control timers (TIM1&TIM8) 17.3.13 Clearing the OCxREF signal on an external event The OCxREF signal for a given channel can be driven Low by applying a High level to the ETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to ‘1’). The OCxREF signal remains Low until the next update event, UEV, occurs.
Page 496: 6-Step Pwm Generation
Advanced-control timers (TIM1&TIM8) RM0430 17.3.14 6-step PWM generation When complementary outputs are used on a channel, preload bits are available on the OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the COM commutation event. Thus you can program in advance the configuration for the next step and change the configuration of all the channels at the same time.
Page 497: One-Pulse Mode
RM0430 Advanced-control timers (TIM1&TIM8) 17.3.15 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller.
Page 498: Encoder Interface Mode
Advanced-control timers (TIM1&TIM8) RM0430 The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The t is defined by the value written in the TIMx_CCR1 register. DELAY • The t is defined by the difference between the auto-reload value and the compare PULSE value (TIMx_ARR - TIMx_CCR1).
Page 499: Table 101. Counting Direction Versus Encoder Signals
RM0430 Advanced-control timers (TIM1&TIM8) configure TIMx_ARR before starting. in the same way, the capture, compare, prescaler, repetition counter, trigger output features continue to work as normal. Encoder mode and External clock mode 2 are not compatible and must not be selected together. In this mode, the counter is modified automatically following the speed and the direction of the incremental encoder and its content, therefore, always represents the encoder’s position.
Page 500: Figure 128. Example Of Counter Operation In Encoder Interface Mode
Advanced-control timers (TIM1&TIM8) RM0430 Figure 128. Example of counter operation in encoder interface mode. Figure 129 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=’1’). Figure 129. Example of encoder interface mode with TI1FP1 polarity inverted. The timer, when configured in Encoder Interface mode provides information on the sensor’s current position.
Page 501: Timer Input Xor Function
RM0430 Advanced-control timers (TIM1&TIM8) 17.3.17 Timer input XOR function The TI1S bit in the TIMx_CR2 register allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the three input pins TIMx_CH1, TIMx_CH2 and TIMx_CH3.
Page 502: Figure 130. Example Of Hall Sensor Interface
Advanced-control timers (TIM1&TIM8) RM0430 Figure 130 describes this example. Figure 130. Example of Hall sensor interface 502/1324 RM0430 Rev 8...
Page 503: Timx And External Trigger Synchronization
RM0430 Advanced-control timers (TIM1&TIM8) 17.3.19 TIMx and external trigger synchronization The TIMx timer can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated.
Page 504: Figure 132. Control Circuit In Gated Mode
Advanced-control timers (TIM1&TIM8) RM0430 Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: • Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000).
Page 505: Figure 133. Control Circuit In Trigger Mode
RM0430 Advanced-control timers (TIM1&TIM8) Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: • Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC2F=0000).
Page 506: Timer Synchronization
Advanced-control timers (TIM1&TIM8) RM0430 Configure the channel 1 as follows, to detect rising edges on TI: – IC1F=0000: no filter. – The capture prescaler is not used for triggering and does not need to be configured. – CC1S=01 in TIMx_CCMR1 register to select only the input capture source –...
Page 507: Tim1&Tim8 Registers
RM0430 Advanced-control timers (TIM1&TIM8) 17.4 TIM1&TIM8 registers Refer to Section 1.2: List of abbreviations for registers for a list of abbreviations used in register descriptions. The peripheral registers must be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-word (16 bits) or words (32 bits).
Page 508: Tim1&Tim8 Control Register 2 (Timx_Cr2)
Advanced-control timers (TIM1&TIM8) RM0430 Bit 3 OPM: One pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled.
Page 509 RM0430 Advanced-control timers (TIM1&TIM8) Bit 11 OIS2N: Output Idle state 2 (OC2N output) refer to OIS1N bit Bit 10 OIS2: Output Idle state 2 (OC2 output) refer to OIS1 bit Bit 9 OIS1N: Output Idle state 1 (OC1N output) 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
Page 510: Tim1&Tim8 Slave Mode Control Register (Timx_Smcr)
Advanced-control timers (TIM1&TIM8) RM0430 Bit 1 Reserved, must be kept at reset value. Bit 0 CCPC: Capture/compare preloaded control 0: CCxE, CCxNE and OCxM bits are not preloaded 1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit).
Page 511 RM0430 Advanced-control timers (TIM1&TIM8) Bits 11:8 ETF[3:0]: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
Page 512: Tim1&Tim8 Dma/Interrupt Enable Register (Timx_Dier)
Advanced-control timers (TIM1&TIM8) RM0430 Bits 2:0 SMS: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description.
Page 513 RM0430 Advanced-control timers (TIM1&TIM8) Bit 12 CC4DE: Capture/Compare 4 DMA request enable 0: CC4 DMA request disabled 1: CC4 DMA request enabled Bit 11 CC3DE: Capture/Compare 3 DMA request enable 0: CC3 DMA request disabled 1: CC3 DMA request enabled Bit 10 CC2DE: Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled 1: CC2 DMA request enabled...
Page 514: Tim1&Tim8 Status Register (Timx_Sr)
Advanced-control timers (TIM1&TIM8) RM0430 17.4.5 TIM1&TIM8 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 Res. Res. Res. CC4OF CC3OF CC2OF CC1OF Res. COMIF CC4IF CC3IF CC2IF CC1IF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:13 Reserved, must be kept at reset value.
Page 515: Tim1&Tim8 Event Generation Register (Timx_Egr)
RM0430 Advanced-control timers (TIM1&TIM8) Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/Compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description).
Page 516 Advanced-control timers (TIM1&TIM8) RM0430 Bit 5 COMG: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware 0: No action 1: When CCPC bit is set, it allows to update CCxE, CCxNE and OCxM bits Note: This bit acts only on channels having a complementary output.
Page 517: Tim1&Tim8 Capture/Compare Mode Register 1 (Timx_Ccmr1)
RM0430 Advanced-control timers (TIM1&TIM8) 17.4.7 TIM1&TIM8 capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode.
Page 518 Advanced-control timers (TIM1&TIM8) RM0430 Bits 6:4 OC1M: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 519 RM0430 Advanced-control timers (TIM1&TIM8) Bits 1:0 CC1S: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC.
Page 520: Tim1&Tim8 Capture/Compare Mode Register 2 (Timx_Ccmr2)
Advanced-control timers (TIM1&TIM8) RM0430 Bits 3:2 IC1PSC: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register). 00: no prescaler, capture is done each time an edge is detected on the capture input 01: capture is done once every 2 events 10: capture is done once every 4 events 11: capture is done once every 8 events...
Page 521: Tim1&Tim8 Capture/Compare Enable Register (Timx_Ccer)
RM0430 Advanced-control timers (TIM1&TIM8) Bit 3 OC3PE: Output compare 3 preload enable Bit 2 OC3FE: Output compare 3 fast enable Bits 1:0 CC3S: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4...
Page 522 Advanced-control timers (TIM1&TIM8) RM0430 Bit 12 CC4E: Capture/Compare 4 output enable refer to CC1E description Bit 11 CC3NP: Capture/Compare 3 complementary output polarity refer to CC1NP description Bit 10 CC3NE: Capture/Compare 3 complementary output enable refer to CC1NE description Bit 9 CC3P: Capture/Compare 3 output polarity refer to CC1P description Bit 8 CC3E: Capture/Compare 3 output enable refer to CC1E description...
Page 523 RM0430 Advanced-control timers (TIM1&TIM8) Bit 1 CC1P: Capture/Compare 1 output polarity CC1 channel configured as output: 0: OC1 active high 1: OC1 active low CC1 channel configured as input: CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations.
Page 524: Table 103. Output Control Bits For Complementary Ocx And Ocxn Channels
Advanced-control timers (TIM1&TIM8) RM0430 Table 103. Output control bits for complementary OCx and OCxN channels with break feature Control bits Output states OSSI OSSR CCxE CCxNE OCx output state OCxN output state Output Disabled (not driven by Output Disabled (not driven by the timer) the timer) OCxN=0, OCxN_EN=0 OCx=0, OCx_EN=0...
Page 525: Tim1&Tim8 Counter (Timx_Cnt)
RM0430 Advanced-control timers (TIM1&TIM8) Note: The state of the external I/O pins connected to the complementary OCx and OCxN channels depends on the OCx and OCxN channel state and the GPIO registers. 17.4.10 TIM1&TIM8 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[15:0] Bits 15:0 CNT[15:0]: Counter value 17.4.11...
Page 526: Tim1&Tim8 Repetition Counter Register (Timx_Rcr)
Advanced-control timers (TIM1&TIM8) RM0430 17.4.13 TIM1&TIM8 repetition counter register (TIMx_RCR) Address offset: 0x30 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. REP[7:0] Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e.
Page 527: Tim1 Capture/Compare Register 2 (Timx_Ccr2)
RM0430 Advanced-control timers (TIM1&TIM8) 17.4.15 TIM1 capture/compare register 2 (TIMx_CCR2) Address offset: 0x38 Reset value: 0x0000 CCR2[15:0] Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC2PE).
Page 528: Tim1&Tim8 Capture/Compare Register 4 (Timx_Ccr4)
Advanced-control timers (TIM1&TIM8) RM0430 17.4.17 TIM1&TIM8 capture/compare register 4 (TIMx_CCR4) Address offset: 0x40 Reset value: 0x0000 CCR4[15:0] Bits 15:0 CCR4[15:0]: Capture/Compare value If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit OC4PE).
Page 529 RM0430 Advanced-control timers (TIM1&TIM8) Bit 13 BKP: Break polarity 0: Break input BRK is active low 1: Break input BRK is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 530: Tim1&Tim8 Dma Control Register (Timx_Dcr)
Advanced-control timers (TIM1&TIM8) RM0430 Bits 7:0 DTG[7:0]: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x t with t DTG[7:5]=10x => DT=(64+DTG[5:0])xt with T =2xt DTG[7:5]=110 =>...
Page 531: Tim1&Tim8 Dma Address For Full Transfer (Timx_Dmar)
RM0430 Advanced-control timers (TIM1&TIM8) 17.4.20 TIM1&TIM8 DMA address for full transfer (TIMx_DMAR) Address offset: 0x4C Reset value: 0x0000 DMAB[15:0] Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the...
Page 532: Tim1&Tim8 Register Map
Advanced-control timers (TIM1&TIM8) RM0430 17.4.21 TIM1&TIM8 register map TIM1&TIM8 registers are mapped as 16-bit addressable registers as described in the table below: Table 104. TIM1&TIM8 register map and reset values Offset Register TIMx_CR1 [1:0] [1:0] 0x00 Reset value TIMx_CR2 MMS[2:0] 0x04 Reset value ETPS...
Page 533 RM0430 Advanced-control timers (TIM1&TIM8) Table 104. TIM1&TIM8 register map and reset values (continued) Offset Register TIMx_CCR1 CCR1[15:0] 0x34 Reset value TIMx_CCR2 CCR2[15:0] 0x38 Reset value TIMx_CCR3 CCR3[15:0] 0x3C Reset value TIMx_CCR4 CCR4[15:0] 0x40 Reset value LOCK TIMx_BDTR DT[7:0] [1:0] 0x44 Reset value TIMx_DCR DBL[4:0]...
Page 534: General-Purpose Timers (Tim2 To Tim5)
General-purpose timers (TIM2 to TIM5) RM0430 General-purpose timers (TIM2 to TIM5) 18.1 TIM2 to TIM5 introduction The general-purpose timers consist of a 16-bit or 32-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare and PWM).
Page 535: Tim2 To Tim5 Functional Description
RM0430 General-purpose timers (TIM2 to TIM5) Figure 135. General-purpose timer block diagram 18.3 TIM2 to TIM5 functional description 18.3.1 Time-base unit The main block of the programmable timer is a 16-bit/32-bit counter with its related auto- reload register. The counter can count up. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software.
Page 536: Figure 136. Counter Timing Diagram With Prescaler Division Change From 1 To 2
General-purpose timers (TIM2 to TIM5) RM0430 The time-base unit includes: • Counter Register (TIMx_CNT) • Prescaler Register (TIMx_PSC): • Auto-Reload Register (TIMx_ARR) The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register.
Page 537: Counter Modes
RM0430 General-purpose timers (TIM2 to TIM5) Figure 137. Counter timing diagram with prescaler division change from 1 to 4 18.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An Update event can be generated at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).
Page 538: Figure 138. Counter Timing Diagram, Internal Clock Divided By 1
General-purpose timers (TIM2 to TIM5) RM0430 Figure 138. Counter timing diagram, internal clock divided by 1 Figure 139. Counter timing diagram, internal clock divided by 2 Figure 140. Counter timing diagram, internal clock divided by 4 538/1324 RM0430 Rev 8...
Page 539: Figure 141. Counter Timing Diagram, Internal Clock Divided By N
RM0430 General-purpose timers (TIM2 to TIM5) Figure 141. Counter timing diagram, internal clock divided by N Figure 142. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded) RM0430 Rev 8 539/1324...
Page 540: Figure 143. Counter Timing Diagram, Update Event When Arpe=1 (Timx_Arr Preloaded)
General-purpose timers (TIM2 to TIM5) RM0430 Figure 143. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded) Downcounting mode In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event.
Page 541: Figure 144. Counter Timing Diagram, Internal Clock Divided By 1
RM0430 General-purpose timers (TIM2 to TIM5) Figure 144. Counter timing diagram, internal clock divided by 1 Figure 145. Counter timing diagram, internal clock divided by 2 Figure 146. Counter timing diagram, internal clock divided by 4 RM0430 Rev 8 541/1324...
Page 542: Figure 147. Counter Timing Diagram, Internal Clock Divided By N
General-purpose timers (TIM2 to TIM5) RM0430 Figure 147. Counter timing diagram, internal clock divided by N Figure 148. Counter timing diagram, Update event Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register) –...
Page 543: Figure 149. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr=0X6
RM0430 General-purpose timers (TIM2 to TIM5) In this mode, the direction bit (DIR from TIMx_CR1 register) cannot be written. It is updated by hardware and gives the current direction of the counter. The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event.
Page 544: Figure 150. Counter Timing Diagram, Internal Clock Divided By 2
General-purpose timers (TIM2 to TIM5) RM0430 Figure 150. Counter timing diagram, internal clock divided by 2 Figure 151. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 1. Center-aligned mode 2 or 3 is used with an UIF on overflow. Figure 152.
Page 545: Figure 153. Counter Timing Diagram, Update Event With Arpe=1 (Counter Underflow)
RM0430 General-purpose timers (TIM2 to TIM5) Figure 153. Counter timing diagram, Update event with ARPE=1 (counter underflow) Figure 154. Counter timing diagram, Update event with ARPE=1 (counter overflow) RM0430 Rev 8 545/1324...
Page 546: Clock Selection
General-purpose timers (TIM2 to TIM5) RM0430 18.3.3 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin (TIx) • External clock mode2: external trigger input (ETR) available on TIM2, TIM3 and TIM4 only.
Page 547: Figure 156. Ti2 External Clock Connection Example
RM0430 General-purpose timers (TIM2 to TIM5) Figure 156. TI2 external clock connection example For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: Configure channel 2 to detect rising edges on the TI2 input by writing CC2S= ‘01 in the TIMx_CCMR1 register.
Page 548: Figure 157. Control Circuit In External Clock Mode 1
General-purpose timers (TIM2 to TIM5) RM0430 Figure 157. Control circuit in external clock mode 1 External clock source mode 2 This mode is selected by writing ECE=1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR. Figure 158 gives an overview of the external trigger input block.
Page 549: Capture/Compare Channels
RM0430 General-purpose timers (TIM2 to TIM5) The delay between the rising edge on ETR and the actual clock of the counter is due to the resynchronization circuit on the ETRP signal. Figure 159. Control circuit in external clock mode 2 18.3.4 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a...
Page 550: Figure 160. Capture/Compare Channel (Example: Channel 1 Input Stage)
General-purpose timers (TIM2 to TIM5) RM0430 Figure 160. Capture/compare channel (example: channel 1 input stage) The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain. Figure 161.
Page 551: Input Capture Mode
RM0430 General-purpose timers (TIM2 to TIM5) Figure 162. Output stage of capture/compare channel (channel 1) The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register.
Page 552: Pwm Input Mode
General-purpose timers (TIM2 to TIM5) RM0430 new level have been detected (sampled at f frequency). Then write IC1F bits to 0011 in the TIMx_CCMR1 register. • Select the edge of the active transition on the TI1 channel by writing the CC1P and CC1NP bits to 00 in the TIMx_CCER register (rising edge in this case).
Page 553: Forced Output Mode
RM0430 General-purpose timers (TIM2 to TIM5) For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value): •...
Page 554: Output Compare Mode
General-purpose timers (TIM2 to TIM5) RM0430 Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the Output Compare Mode section. 18.3.8 Output compare mode This function is used to control an output waveform or indicating when a period of time has...
Page 555: Pwm Mode
RM0430 General-purpose timers (TIM2 to TIM5) Figure 164. Output compare mode, toggle on OC1 18.3.9 PWM mode Pulse width modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
Page 556: Figure 165. Edge-Aligned Pwm Waveforms (Arr=8)
General-purpose timers (TIM2 to TIM5) RM0430 PWM edge-aligned mode Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to Upcounting mode on page 537. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT <TIMx_CCRx else it becomes low.
Page 557: Figure 166. Center-Aligned Pwm Waveforms (Arr=8)
RM0430 General-purpose timers (TIM2 to TIM5) Center-aligned mode (up/down counting) on page 542. Figure 166 shows some center-aligned PWM waveforms in an example where: • TIMx_ARR=8, • PWM mode is the PWM mode 1, • The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for CMS=01 in TIMx_CR1 register.
Page 558: One-Pulse Mode
General-purpose timers (TIM2 to TIM5) RM0430 in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software. • Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results.
Page 559: Clearing The Ocxref Signal On An External Event
RM0430 General-purpose timers (TIM2 to TIM5) Let’s use TI2FP2 as trigger 1: • Map TI2FP2 on TI2 by writing CC2S=01 in the TIMx_CCMR1 register. • TI2FP2 must detect a rising edge, write CC2P=0 and CC2NP=’0’ in the TIMx_CCER register. • Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=110 in the TIMx_SMCR register.
Page 560: Encoder Interface Mode
General-purpose timers (TIM2 to TIM5) RM0430 The external trigger prescaler should be kept off: bits ETPS[1:0] in the TIMx_SMCR register are cleared to 00. The external clock mode 2 must be disabled: bit ECE in the TIM1_SMCR register is cleared to 0. The external trigger polarity (ETP) and the external trigger filter (ETF) can be configured according to the application’s needs.
Page 561: Table 105. Counting Direction Versus Encoder Signals
RM0430 General-purpose timers (TIM2 to TIM5) In this mode, the counter is modified automatically following the speed and the direction of the incremental encoder and its content, therefore, always represents the encoder’s position. The count direction correspond to the rotation direction of the connected sensor. The table summarizes the possible combinations, assuming TI1 and TI2 don’t switch at the same time.
Page 562: Figure 169. Example Of Counter Operation In Encoder Interface Mode
General-purpose timers (TIM2 to TIM5) RM0430 Figure 169. Example of counter operation in encoder interface mode Figure 170 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=1). Figure 170. Example of encoder interface mode with TI1FP1 polarity inverted The timer, when configured in Encoder Interface mode provides information on the sensor’s current position.
Page 563: Timer Input Xor Function
RM0430 General-purpose timers (TIM2 to TIM5) 18.3.13 Timer input XOR function The TI1S bit in the TIM_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the three input pins TIMx_CH1 to TIMx_CH3. The XOR output can be used with all the timer input functions such as trigger or input capture.
Page 564: Figure 172. Control Circuit In Gated Mode
General-purpose timers (TIM2 to TIM5) RM0430 Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: • Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000).
Page 565: Figure 173. Control Circuit In Trigger Mode
RM0430 General-purpose timers (TIM2 to TIM5) The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input. Figure 173. Control circuit in trigger mode Slave mode: External Clock mode 2 + trigger mode The external clock mode 2 can be used in addition to another slave mode (except external clock mode 1 and encoder mode).
Page 566: Timer Synchronization
General-purpose timers (TIM2 to TIM5) RM0430 Figure 174. Control circuit in external clock mode 2 + trigger mode 18.3.15 Timer synchronization The TIMx timers are linked together internally for timer synchronization or chaining. When one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of another Timer configured in Slave Mode.
Page 567: Figure 176. Gating Timer 2 With Oc1Ref Of Timer 1
RM0430 General-purpose timers (TIM2 to TIM5) For example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to Figure 175. To do this: • Configure Timer 1 in master mode so that it outputs a periodic trigger signal on each update event UEV.
Page 568: Figure 177. Gating Timer 2 With Enable Of Timer 1
General-purpose timers (TIM2 to TIM5) RM0430 you want in the timer counters. The timers can easily be reset by software using the UG bit in the TIMx_EGR registers. In the next example, we synchronize Timer 1 and Timer 2. Timer 1 is the master and starts from 0.
Page 569: Figure 178. Triggering Timer 2 With Update Of Timer 1
RM0430 General-purpose timers (TIM2 to TIM5) counts until we write ‘0 to the CEN bit in the TIM2_CR1 register. Both counter clock frequencies are divided by 3 by the prescaler compared to CK_INT (f /3). CK_CNT CK_INT • Configure Timer 1 master mode to send its Update Event (UEV) as trigger output (MMS=010 in the TIM1_CR2 register).
Page 570: Figure 179. Triggering Timer 2 With Enable Of Timer 1
General-purpose timers (TIM2 to TIM5) RM0430 Figure 179. Triggering timer 2 with Enable of timer 1 Using one timer as prescaler for another timer For example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to Figure 175 for connections.
Page 571: Debug Mode
RM0430 General-purpose timers (TIM2 to TIM5) counters are aligned, Timer 1 must be configured in Master/Slave mode (slave with respect to TI1, master with respect to Timer 2): • Configure Timer 1 master mode to send its Enable as trigger output (MMS=001 in the TIM1_CR2 register).
Page 572: Tim2 To Tim5 Registers
General-purpose timers (TIM2 to TIM5) RM0430 18.4 TIM2 to TIM5 registers Refer to Section 1.2 on page 52 for a list of abbreviations used in register descriptions. The 32-bit peripheral registers have to be written by words (32 bits). All other peripheral registers have to be written by half-words (16 bits) or words (32 bits).
Page 573 RM0430 General-purpose timers (TIM2 to TIM5) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: –...
Page 574: Timx Control Register 2 (Timx_Cr2)
General-purpose timers (TIM2 to TIM5) RM0430 18.4.2 TIMx control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. TI1S MMS[2:0] CCDS Res. Res. Res. Bits 15:8 Reserved, must be kept at reset value. Bit 7 TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input 1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
Page 575: Timx Slave Mode Control Register (Timx_Smcr)
RM0430 General-purpose timers (TIM2 to TIM5) 18.4.3 TIMx slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 ETPS[1:0] ETF[3:0] TS[2:0] Res. SMS[2:0] Bit 15 ETP: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is noninverted, active at high level or rising edge 1: ETR is inverted, active at low level or falling edge Bit 14 ECE: External clock enable...
Page 576: Table 106. Timx Internal Trigger Connections
General-purpose timers (TIM2 to TIM5) RM0430 Bit 7 MSM: Master/Slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Page 577: Timx Dma/Interrupt Enable Register (Timx_Dier)
RM0430 General-purpose timers (TIM2 to TIM5) 18.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 Res. Res. CC4DE CC3DE CC2DE CC1DE Res. Res. CC4IE CC3IE CC2IE CC1IE Bit 15 Reserved, must be kept at reset value. Bit 14 TDE: Trigger DMA request enable 0: Trigger DMA request disabled.
Page 578: Timx Status Register (Timx_Sr)
General-purpose timers (TIM2 to TIM5) RM0430 Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled 1: CC2 interrupt enabled Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled 18.4.5...
Page 579 RM0430 General-purpose timers (TIM2 to TIM5) Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description).
Page 580: Timx Event Generation Register (Timx_Egr)
General-purpose timers (TIM2 to TIM5) RM0430 18.4.6 TIMx event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC4G CC3G CC2G CC1G Bits 15:7 Reserved, must be kept at reset value. Bit 6 TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
Page 581: Timx Capture/Compare Mode Register 1 (Timx_Ccmr1)
RM0430 General-purpose timers (TIM2 to TIM5) 18.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode.
Page 582 General-purpose timers (TIM2 to TIM5) RM0430 Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 583 RM0430 General-purpose timers (TIM2 to TIM5) Input capture mode Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output.
Page 584: Timx Capture/Compare Mode Register 2 (Timx_Ccmr2)
General-purpose timers (TIM2 to TIM5) RM0430 18.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2) Address offset: 0x1C Reset value: 0x0000 Refer to the above CCMR1 register description. OC4CE OC4M[2:0] OC4PE OC4FE OC3CE OC3M[2:0] OC3PE OC3FE CC4S[1:0] CC3S[1:0] IC4F[3:0] IC4PSC[1:0] IC3F[3:0] IC3PSC[1:0] Output compare mode Bit 15 OC4CE: Output compare 4 clear enable Bits 14:12 OC4M: Output compare 4 mode...
Page 585: Timx Capture/Compare Enable Register (Timx_Ccer)
RM0430 General-purpose timers (TIM2 to TIM5) Input capture mode Bits 15:12 IC4F: Input capture 4 filter Bits 11:10 IC4PSC: Input capture 4 prescaler Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3...
Page 586: Table 107. Output Control Bit For Standard Ocx Channels
General-purpose timers (TIM2 to TIM5) RM0430 Bit 7 CC2NP: Capture/Compare 2 output Polarity. refer to CC1NP description Bit 6 Reserved, must be kept at reset value. Bit 5 CC2P: Capture/Compare 2 output Polarity. refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable. refer to CC1E description Bit 3 CC1NP: Capture/Compare 1 output Polarity.
Page 587: Timx Counter (Timx_Cnt)
RM0430 General-purpose timers (TIM2 to TIM5) 18.4.10 TIMx counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[15:0] Bits 15:0 CNT[15:0]: Counter value 18.4.11 TIMx prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to f / (PSC[15:0] + 1).
Page 588: Timx Capture/Compare Register 1 (Timx_Ccr1)
General-purpose timers (TIM2 to TIM5) RM0430 18.4.13 TIMx capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 0000 CCR1[31:16] (depending on timers) CCR1[15:0] Bits 31:16 CCR1[31:16]: High Capture/Compare 1 value (on TIM2 and TIM5). Bits 15:0 CCR1[15:0]: Low Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
Page 589: Timx Capture/Compare Register 3 (Timx_Ccr3)
RM0430 General-purpose timers (TIM2 to TIM5) 18.4.15 TIMx capture/compare register 3 (TIMx_CCR3) Address offset: 0x3C Reset value: 0x0000 0000 CCR3[31:16] (depending on timers) CCR3[15:0] Bits 31:16 CCR3[31:16]: High Capture/Compare 3 value (on TIM2 and TIM5). Bits 15:0 CCR3[15:0]: Low Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).
Page 590: Timx Dma Control Register (Timx_Dcr)
General-purpose timers (TIM2 to TIM5) RM0430 18.4.17 TIMx DMA control register (TIMx_DCR) Address offset: 0x48 Reset value: 0x0000 Res. Res. Res. DBL[4:0] Res. Res. Res. DBA[4:0] Bits 15:13 Reserved, must be kept at reset value. Bits 12:8 DBL[4:0]: DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address).
Page 591: Tim2 Option Register (Tim2_Or)
RM0430 General-purpose timers (TIM2 to TIM5) Configure the corresponding DMA channel as follows: – DMA channel peripheral address is the DMAR register address – DMA channel memory address is the address of the buffer in the RAM containing the data to be transferred by DMA into CCRx registers. –...
Page 592: Tim5 Option Register (Tim5_Or)
General-purpose timers (TIM2 to TIM5) RM0430 18.4.20 TIM5 option register (TIM5_OR) Address offset: 0x50 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. TI4_RMP Res. Res. Res. Res. Res. Res. Bits 15:8 Reserved, must be kept at reset value. Bits 7:6 TI4_RMP: Timer Input 4 remap Set and cleared by software.
Page 593: Timx Register Map
RM0430 General-purpose timers (TIM2 to TIM5) 18.4.21 TIMx register map TIMx registers are mapped as described in the table below: Table 108. TIM2 to TIM5 register map and reset values Offset Register TIMx_CR1 [1:0] [1:0] 0x00 Reset value TIMx_CR2 MMS[2:0] 0x04 Reset value ETPS...
Page 594 General-purpose timers (TIM2 to TIM5) RM0430 Table 108. TIM2 to TIM5 register map and reset values (continued) Offset Register TIMx_PSC PSC[15:0] 0x28 Reset value ARR[31:16] TIMx_ARR ARR[15:0] (TIM2 and TIM5 only, reserved on the other timers) 0x2C Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x30 Reserved CCR1[31:16]...
Page 595: General-Purpose Timers (Tim9 To Tim14)
RM0430 General-purpose timers (TIM9 to TIM14) General-purpose timers (TIM9 to TIM14) 19.1 TIM9 to TIM14 introduction The TIM9 to TIM14 general-purpose timers consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM).
Page 596: Tim10/Tim11 And Tim13/Tim14 Main Features
General-purpose timers (TIM9 to TIM14) RM0430 Figure 181. General-purpose timer block diagram (TIM9 and TIM12) Internal clock (CK_INT) ITR0 Trigger controller ITR1 ITR2 TRGI Slave ITR3 Reset, Enable, Count mode TI1F_ED controller TI1FP1 TI2FP2 Auto-reload register Stop, Clear CK_PSC CK_CNT Prescaler COUNTER CC1I...
Page 597: Figure 182. General-Purpose Timer Block Diagram (Tim10/11/13/14)
RM0430 General-purpose timers (TIM9 to TIM14) Figure 182. General-purpose timer block diagram (TIM10/11/13/14) RM0430 Rev 8 597/1324...
Page 598: Tim9 To Tim14 Functional Description
General-purpose timers (TIM9 to TIM14) RM0430 19.3 TIM9 to TIM14 functional description 19.3.1 Time-base unit The main block of the timer is a 16-bit counter with its related auto-reload register. The counters counts up. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software.
Page 599: Figure 183. Counter Timing Diagram With Prescaler Division Change From 1 To 2
RM0430 General-purpose timers (TIM9 to TIM14) Figure 183. Counter timing diagram with prescaler division change from 1 to 2 Figure 184. Counter timing diagram with prescaler division change from 1 to 4 RM0430 Rev 8 599/1324...
Page 600: Counter Modes
General-purpose timers (TIM9 to TIM14) RM0430 19.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller on TIM9 and TIM12) also generates an update event.
Page 601: Figure 186. Counter Timing Diagram, Internal Clock Divided By 2
RM0430 General-purpose timers (TIM9 to TIM14) Figure 186. Counter timing diagram, internal clock divided by 2 Figure 187. Counter timing diagram, internal clock divided by 4 Figure 188. Counter timing diagram, internal clock divided by N RM0430 Rev 8 601/1324...
Page 602: Figure 189. Counter Timing Diagram, Update Event When Arpe=0
General-purpose timers (TIM9 to TIM14) RM0430 Figure 189. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) Figure 190. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) 602/1324 RM0430 Rev 8...
Page 603: Clock Selection
RM0430 General-purpose timers (TIM9 to TIM14) 19.3.3 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1 (for TIM9 and TIM12): external input pin (TIx) • Internal trigger inputs (ITRx) (for TIM9 and TIM12): connecting the trigger output from another timer.
Page 604: Figure 192. Ti2 External Clock Connection Example
General-purpose timers (TIM9 to TIM14) RM0430 Figure 192. TI2 external clock connection example For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register.
Page 605: Capture/Compare Channels
RM0430 General-purpose timers (TIM9 to TIM14) 19.3.4 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control). Figure 194 Figure 196 give an overview of one capture/compare channel.
Page 606: Input Capture Mode
General-purpose timers (TIM9 to TIM14) RM0430 Figure 195. Capture/compare channel 1 main circuit Figure 196. Output stage of capture/compare channel (channel 1) The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register.
Page 607: Pwm Input Mode (Only For Tim9/12)
RM0430 General-purpose timers (TIM9 to TIM14) cleared by software by writing it to ‘0’ or by reading the captured data stored in the TIMx_CCRx register. CCxOF is cleared when you write it to ‘0’. The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises.
Page 608: Forced Output Mode
General-purpose timers (TIM9 to TIM14) RM0430 Select the active input for TIMx_CCR1: write the CC1S bits to ‘01’ in the TIMx_CCMR1 register (TI1 selected). Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): program the CC1P and CC1NP bits to ‘00’ (active on rising edge). Select the active input for TIMx_CCR2: write the CC2S bits to ‘10’...
Page 609: Output Compare Mode
RM0430 General-purpose timers (TIM9 to TIM14) 19.3.8 Output compare mode This function is used to control an output waveform or indicating when a period of time has elapsed. When a match is found between the capture/compare register and the counter, the output compare function: Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP...
Page 610: Pwm Mode
General-purpose timers (TIM9 to TIM14) RM0430 Figure 198. Output compare mode, toggle on OC1. 19.3.9 PWM mode Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
Page 611: One-Pulse Mode
RM0430 General-purpose timers (TIM9 to TIM14) Figure 199. Edge-aligned PWM waveforms (ARR=8) 19.3.10 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay.
Page 612: Figure 200. Example Of One Pulse Mode
General-purpose timers (TIM9 to TIM14) RM0430 Figure 200. Example of one pulse mode. For example you may want to generate a positive pulse on OC1 with a length of t PULSE after a delay of t as soon as a positive edge is detected on the TI2 input pin. DELAY Use TI2FP2 as trigger 1: Map TI2FP2 to TI2 by writing CC2S=’01’...
Page 613: Tim9/12 External Trigger Synchronization
RM0430 General-purpose timers (TIM9 to TIM14) Particular case: OCx fast enable In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle.
Page 614: Figure 201. Control Circuit In Reset Mode
General-purpose timers (TIM9 to TIM14) RM0430 Figure 201. Control circuit in reset mode Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: Configure the channel 1 to detect low levels on TI1.
Page 615: Figure 202. Control Circuit In Gated Mode
RM0430 General-purpose timers (TIM9 to TIM14) Figure 202. Control circuit in gated mode Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: Configure the channel 2 to detect rising edges on TI2.
Page 616: Timer Synchronization (Tim9/12)
General-purpose timers (TIM9 to TIM14) RM0430 19.3.12 Timer synchronization (TIM9/12) The TIM timers are linked together internally for timer synchronization or chaining. Refer to Section 18.3.15: Timer synchronization for details. 19.3.13 Debug mode ® When the microcontroller enters debug mode (Cortex -M4 with FPU core halted), the TIMx counter either continues to work normally or stops, depending on DBG_TIMx_STOP configuration bit in DBG module.
Page 617 RM0430 General-purpose timers (TIM9 to TIM14) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generates an update interrupt if enabled: – Counter overflow –...
Page 618: Tim9/12 Slave Mode Control Register (Timx_Smcr)
General-purpose timers (TIM9 to TIM14) RM0430 19.4.2 TIM9/12 slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. TS[2:0] Res. SMS[2:0] Bits 15:8 Reserved, must be kept at reset value. Bit 7 MSM: Master/Slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO).
Page 619: Tim9/12 Interrupt Enable Register (Timx_Dier)
RM0430 General-purpose timers (TIM9 to TIM14) Table 109. TIMx internal trigger connections Slave TIM ITR0 (TS = ‘000’) ITR1 (TS = ‘001’) ITR2 (TS = ‘010’) ITR3 (TS = ‘011’) TIM9 TIM2 TIM3 or LPTIM1 TIM10_OC TIM11_OC TIM12 TIM4 TIM5 TIM13_OC TIM14_OC 1.
Page 620: Tim9/12 Status Register (Timx_Sr)
General-purpose timers (TIM9 to TIM14) RM0430 19.4.4 TIM9/12 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 Res. Res. Res. Res. Res. CC2OF CC1OF Res. Res. Res. Res. Res. CC2IF CC1IF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:11 Reserved, must be kept at reset value. Bit 10 CC2OF: Capture/compare 2 overcapture flag refer to CC1OF description Bit 9 CC1OF: Capture/Compare 1 overcapture flag...
Page 621 RM0430 General-purpose timers (TIM9 to TIM14) Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value. It is cleared by software. 0: No match. 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
Page 622: Tim9/12 Event Generation Register (Timx_Egr)
General-purpose timers (TIM9 to TIM14) RM0430 19.4.5 TIM9/12 event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC2G CC1G Bits 15:7 Reserved, must be kept at reset value. Bit 6 TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
Page 623 RM0430 General-purpose timers (TIM9 to TIM14) Output compare mode Bit 15 Reserved, must be kept at reset value. Bits 14:12 OC2M[2:0]: Output compare 2 mode Bit 11 OC2PE: Output compare 2 preload enable Bit 10 OC2FE: Output compare 2 fast enable Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection This bitfield defines the direction of the channel (input/output) as well as the used input.
Page 624 General-purpose timers (TIM9 to TIM14) RM0430 Bit 3 OC1PE: Output compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken into account immediately 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register.
Page 625 RM0430 General-purpose timers (TIM9 to TIM14) Input capture mode Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/compare 2 selection This bitfield defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1...
Page 626: Tim9/12 Capture/Compare Enable Register (Timx_Ccer)
General-purpose timers (TIM9 to TIM14) RM0430 19.4.7 TIM9/12 capture/compare enable register (TIMx_CCER) Address offset: 0x20 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. CC2NP Res. CC2P CC2E CC1NP Res. CC1P CC1E Bits 15:8 Reserved, must be kept at reset value. Bit 7 CC2NP: Capture/Compare 2 output Polarity refer to CC1NP description Bit 6 Reserved, must be kept at reset value.
Page 627: Tim9/12 Counter (Timx_Cnt)
RM0430 General-purpose timers (TIM9 to TIM14) Table 110. Output control bit for standard OCx channels CCxE bit OCx output state Output disabled (OCx=’0’, OCx_EN=’0’) OCx=OCxREF + Polarity, OCx_EN=’1’ Note: The states of the external I/O pins connected to the standard OCx channels depend on the state of the OCx channel and on the GPIO registers.
Page 628: Tim9/12 Capture/Compare Register 1 (Timx_Ccr1)
General-purpose timers (TIM9 to TIM14) RM0430 19.4.11 TIM9/12 capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 CCR1[15:0] Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded into the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (OC1PE bit).
Page 629: Tim9/12 Register Map
RM0430 General-purpose timers (TIM9 to TIM14) 19.4.13 TIM9/12 register map TIM9/12 registers are mapped as 16-bit addressable registers as described below: Table 111. TIM9/12 register map and reset values Offset Register TIMx_CR1 [1:0] 0x00 Reset value TIMx_SMCR TS[2:0] SMS[2:0] 0x08 Reset value TIMx_DIER 0x0C...
Page 630 General-purpose timers (TIM9 to TIM14) RM0430 Table 111. TIM9/12 register map and reset values (continued) Offset Register TIMx_CCR1 CCR1[15:0] 0x34 Reset value TIMx_CCR2 CCR2[15:0] 0x38 Reset value 0x3C to Reserved 0x4C Refer to Section 2.2.2 on page 58 for the register boundary addresses. 630/1324 RM0430 Rev 8...
Page 631: Tim10/11/13/14 Registers
RM0430 General-purpose timers (TIM9 to TIM14) 19.5 TIM10/11/13/14 registers The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). 19.5.1 TIM10/11/13/14 control register 1 (TIMx_CR1) Address offset: 0x00...
Page 632: Tim10/11/13/14 Interrupt Enable Register (Timx_Dier)
General-purpose timers (TIM9 to TIM14) RM0430 19.5.2 TIM10/11/13/14 Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC1IE Bits 15:2 Reserved, must be kept at reset value. Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled...
Page 633: Tim10/11/13/14 Event Generation Register (Timx_Egr)
RM0430 General-purpose timers (TIM9 to TIM14) Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value. It is cleared by software. 0: No match. 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
Page 634: Tim10/11/13/14 Capture/Compare Mode Register 1
General-purpose timers (TIM9 to TIM14) RM0430 19.5.5 TIM10/11/13/14 capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode.
Page 635 RM0430 General-purpose timers (TIM9 to TIM14) Output compare mode Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 is derived.
Page 636 General-purpose timers (TIM9 to TIM14) RM0430 Input capture mode Bits 15:8 Reserved, must be kept at reset value. Bits 7:4 IC1F: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1.
Page 637: Tim10/11/13/14 Capture/Compare Enable Register
RM0430 General-purpose timers (TIM9 to TIM14) 19.5.6 TIM10/11/13/14 capture/compare enable register (TIMx_CCER) Address offset: 0x20 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC1NP Res. CC1P CC1E Bits 15:4 Reserved, must be kept at reset value. Bit 3 CC1NP: Capture/Compare 1 complementary output Polarity.
Page 638: Tim10/11/13/14 Counter (Timx_Cnt)
General-purpose timers (TIM9 to TIM14) RM0430 19.5.7 TIM10/11/13/14 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[15:0] Bits 15:0 CNT[15:0]: Counter value 19.5.8 TIM10/11/13/14 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to f / (PSC[15:0] + 1).
Page 639: Tim10/11/13/14 Capture/Compare Register 1 (Timx_Ccr1)
RM0430 General-purpose timers (TIM9 to TIM14) 19.5.10 TIM10/11/13/14 capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 CCR1[15:0] Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE).
Page 640: Tim10/11/13/14 Register Map
General-purpose timers (TIM9 to TIM14) RM0430 19.5.12 TIM10/11/13/14 register map TIMx registers are mapped as 16-bit addressable registers as described in the table below: Table 113. TIM10/11/13/14 register map and reset values Offset Register TIMx_CR1 [1:0] 0x00 Reset value TIMx_SMCR 0x08 Reset value TIMx_DIER...
Page 641 RM0430 General-purpose timers (TIM9 to TIM14) Table 113. TIM10/11/13/14 register map and reset values (continued) Offset Register TIMx_CCR1 CCR1[15:0] 0x34 Reset value 0x38 to Reserved 0x4C TIMx_OR 0x50 Reset value Refer to Section 2.2.2 on page 58 for the register boundary addresses. RM0430 Rev 8 641/1324...
Page 642: Basic Timers (Tim6/7)
Basic timers (TIM6/7) RM0430 Basic timers (TIM6/7) 20.1 Introduction The basic timers TIM6, TIM7 consist of a 16-bit auto-reload counter driven by a programmable prescaler. 20.2 TIM6/7 main features Basic timer (TIM6/TIM7) features include: • 16-bit auto-reload upcounter • 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65536 •...
Page 643: Tim6/7 Functional Description
RM0430 Basic timers (TIM6/7) 20.3 TIM6/7 functional description 20.3.1 Time-base unit The main block of the programmable timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software.
Page 644: Figure 205. Counter Timing Diagram With Prescaler Division Change From 1 To 2
Basic timers (TIM6/7) RM0430 Figure 205. Counter timing diagram with prescaler division change from 1 to 2 Figure 206. Counter timing diagram with prescaler division change from 1 to 4 644/1324 RM0430 Rev 8...
Page 645: Counting Mode
RM0430 Basic timers (TIM6/7) 20.3.2 Counting mode The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An update event can be generate at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).
Page 646: Figure 208. Counter Timing Diagram, Internal Clock Divided By 2
Basic timers (TIM6/7) RM0430 Figure 208. Counter timing diagram, internal clock divided by 2 Figure 209. Counter timing diagram, internal clock divided by 4 646/1324 RM0430 Rev 8...
Page 647: Figure 210. Counter Timing Diagram, Internal Clock Divided By N
RM0430 Basic timers (TIM6/7) Figure 210. Counter timing diagram, internal clock divided by N Figure 211. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded) RM0430 Rev 8 647/1324...
Page 648: Clock Source
Basic timers (TIM6/7) RM0430 Figure 212. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) 20.3.3 Clock source The counter clock is provided by the Internal clock (CK_INT) source. The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except for UG that remains cleared automatically).
Page 649: Debug Mode
RM0430 Basic timers (TIM6/7) Figure 213. Control circuit in normal mode, internal clock divided by 1 20.3.4 Debug mode ® When the microcontroller enters the debug mode (Cortex -M4 with FPU core - halted), the TIMx counter either continues to work normally or stops, depending on the DBG_TIMx_STOP configuration bit in the DBG module.
Page 650: Tim6/7 Registers
Basic timers (TIM6/7) RM0430 20.4 TIM6/7 registers Refer to Section 1.2: List of abbreviations for registers for a list of abbreviations used in register descriptions. The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).
Page 651: Tim6/7 Control Register 2 (Timx_Cr2)
RM0430 Basic timers (TIM6/7) 20.4.2 TIM6/7 control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. MMS[2:0] Res. Res. Res. Res. Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 MMS: Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO).
Page 652: Tim6/7 Status Register (Timx_Sr)
Basic timers (TIM6/7) RM0430 20.4.4 TIM6/7 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rc_w0 Bits 15:1 Reserved, must be kept at reset value. Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event.
Page 653: Tim6/7 Prescaler (Timx_Psc)
RM0430 Basic timers (TIM6/7) 20.4.7 TIM6/7 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency (CK_CNT) is equal to f / (PSC[15:0] + 1). CK_PSC PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”).
Page 654: Tim6/7 Register Map
Basic timers (TIM6/7) RM0430 20.4.9 TIM6/7 register map TIMx registers are mapped as 16-bit addressable registers as described in the table below: Table 114. TIM6 register map and reset values Offset Register TIMx_CR1 0x00 Reset value TIMx_CR2 MMS[2:0] 0x04 Reset value 0x08 Res.
Page 655: Low-Power Timer (Lptim)
RM0430 Low-power timer (LPTIM) Low-power timer (LPTIM) 21.1 Introduction The LPTIM is a 16-bit timer that benefits from the ultimate developments in power consumption reduction. Thanks to its diversity of clock sources, the LPTIM is able to keep running in all power modes except for Standby mode. Given its capability to run even with no internal clock source, the LPTIM can be used as a “Pulse Counter”...
Page 656: Lptim Functional Description
Low-power timer (LPTIM) RM0430 21.4 LPTIM functional description 21.4.1 LPTIM block diagram Figure 214. Low-power timer block diagram 21.4.2 LPTIM trigger mapping The LPTIM external trigger connections are detailed hereafter: Table 116. LPTIM1 external trigger connection TRIGSEL External trigger lptim_ext_trig0 PB6 or PC3 input on AF1 lptim_ext_trig1 RTC alarm A output signal...
Page 657: Lptim Input1 Multiplexing
RM0430 Low-power timer (LPTIM) Table 116. LPTIM1 external trigger connection (continued) TRIGSEL External trigger lptim_ext_trig6 Reserved lptim_ext_trig7 Reserved 21.4.3 LPTIM input1 multiplexing Various inputs can be selected for LPTIM1 input 1 through the LPTMI option register (LPTIM1_OR). This input can either be connected to the pads selected by the LPTIM alternate function (AF1) or directly connected internally to PA4, PB9 pad or to TIM6/DAC trigger.
Page 658: Prescaler
Low-power timer (LPTIM) RM0430 The digital filters are divided into two groups: • The first group of digital filters protects the LPTIM external inputs. The digital filters sensitivity is controlled by the CKFLT bits • The second group of digital filters protects the LPTIM internal trigger inputs. The digital filters sensitivity is controlled by the TRGFLT bits.
Page 659: Trigger Multiplexer
RM0430 Low-power timer (LPTIM) 21.4.7 Trigger multiplexer The LPTIM counter may be started either by software or after the detection of an active edge on one of the 8 trigger inputs. TRIGEN[1:0] is used to determine the LPTIM trigger source: •...
Page 660: Figure 216. Lptim Output Waveform, Single Counting Mode Configuration
Low-power timer (LPTIM) RM0430 Figure 216. LPTIM output waveform, single counting mode configuration - Set-once mode activated: It should be noted that when the WAVE bit-field in the LPTIM_CFGR register is set, the Set- once mode is activated. In this case, the counter is only started once following the first trigger, and any subsequent trigger event is discarded as shown in Figure 217.
Page 661: Timeout Function
RM0430 Low-power timer (LPTIM) Figure 218. LPTIM output waveform, Continuous counting mode configuration SNGSTRT and CNTSTRT bits can only be set when the timer is enabled (The ENABLE bit is set to ‘1’). It is possible to change “on the fly” from One-shot mode to Continuous mode. If the Continuous mode was previously selected, setting SNGSTRT will switch the LPTIM to the One-shot mode.
Page 662: Register Update
Low-power timer (LPTIM) RM0430 The LPTIM output waveform can be configured through the WAVE bit as follow: • Resetting the WAVE bit to ‘0’ forces the LPTIM to generate either a PWM waveform or a One pulse waveform depending on which bit is set: CNTSTRT or SNGSTRT. •...
Page 663: Counter Mode
RM0430 Low-power timer (LPTIM) counter comparator. Within this latency period, any additional write into these registers must be avoided. The ARROK flag and the CMPOK flag in the LPTIM_ISR register indicate when the write operation is completed to respectively the LPTIM_ARR register and the LPTIM_CMP register.
Page 664: Encoder Mode
Low-power timer (LPTIM) RM0430 The LPTIM_CFGR and LPTIM_IER registers must be modified only when the LPTIM is disabled. 21.4.14 Encoder mode This mode allows handling signals from quadrature encoders used to detect angular position of rotary elements. Encoder interface mode acts simply as an external clock with direction selection.
Page 665: Debug Mode
RM0430 Low-power timer (LPTIM) Figure 220. Encoder mode counting sequence 21.4.15 Debug mode When the microcontroller enters debug mode (core halted), the LPTIM counter either continues to work normally or stops, depending on the DBG_LPTIM_STOP configuration bit in the DBG module. 21.5 LPTIM interrupts The following events generate an interrupt/wake-up event, if they are enabled through the...
Page 666: Lptim Registers
Low-power timer (LPTIM) RM0430 Table 119. Interrupt events Interrupt event Description Interrupt flag is raised when the content of the Counter register Compare match (LPTIM_CNT) matches the content of the compare register (LPTIM_CMP). Interrupt flag is raised when the content of the Counter register Auto-reload match (LPTIM_CNT) matches the content of the Auto-reload register (LPTIM_ARR).
Page 667: Lptim Interrupt Clear Register (Lptim_Icr)
RM0430 Low-power timer (LPTIM) Bit 10 Reserved, must be kept at reset value. Bit 9 Reserved, must be kept at reset value. Bits 8:7 Reserved, must be kept at reset value. Bit 6 DOWN: Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down.
Page 668: Lptim Interrupt Enable Register (Lptim_Ier)
Low-power timer (LPTIM) RM0430 Bits 18:16 Reserved, must be kept at reset value. Bit 15 Reserved, must be kept at reset value. Bit 14 Reserved, must be kept at reset value. Bit 13 Reserved, must be kept at reset value. Bit 12 Reserved, must be kept at reset value.
Page 669 RM0430 Low-power timer (LPTIM) Bit 24 Reserved, must be kept at reset value. Bit 23 Reserved, must be kept at reset value. Bit 22 Reserved, must be kept at reset value. Bit 21 Reserved, must be kept at reset value. Bit 20 Reserved, must be kept at reset value.
Page 670: Lptim Configuration Register (Lptim_Cfgr)
Low-power timer (LPTIM) RM0430 21.6.4 LPTIM configuration register (LPTIM_CFGR) Address offset: 0x00C Reset value: 0x0000 0000 COUNT Res. Res. Res. Res. Res. Res. Res. PRELOAD WAVPOL WAVE TIMOUT TRIGEN[1:0] Res. MODE TRIGSEL[2:0] Res. PRESC[2:0] Res. TRGFLT[1:0] Res. CKFLT[1:0] CKPOL[1:0] CKSEL Bits 31:30 Reserved, must be kept at reset value.
Page 671 RM0430 Low-power timer (LPTIM) Bits 18:17 TRIGEN[1:0]: Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge: 00: software trigger (counting start is initiated by software) 01: rising edge is the active edge 10: falling edge is the active edge...
Page 672: Lptim Control Register (Lptim_Cr)
Low-power timer (LPTIM) RM0430 Bits 4:3 CKFLT[1:0]: Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any external clock signal level change is considered as a valid transition 01: external clock signal level change must be stable for at least 2 clock periods before it is...
Page 673: Lptim Compare Register (Lptim_Cmp)
RM0430 Low-power timer (LPTIM) Bits 31:3 Reserved, must be kept at reset value. Bit 2 CNTSTRT: Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected.
Page 674: Lptim Autoreload Register (Lptim_Arr)
Low-power timer (LPTIM) RM0430 21.6.7 LPTIM autoreload register (LPTIM_ARR) Address offset: 0x018 Reset value: 0x0000 0001 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ARR[15:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 ARR[15:0]: Auto reload value ARR is the autoreload value for the LPTIM.
Page 675: Lptim1 Option Register (Lptim1_Optr)
RM0430 Low-power timer (LPTIM) 21.6.9 LPTIM1 option register (LPTIM1_OPTR) Address offset: 0x020 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIM9_ITR1 TIM5_ITR1 TIM1_ITR2 LPT_IN1 Res. Res. Res. Res. Res.
Page 676: Lptim Register Map
Low-power timer (LPTIM) RM0430 21.6.10 LPTIM register map The following table summarizes the LPTIM registers. Table 120. LPTIM register map and reset values Offset Register name LPTIM_ISR 0x000 0 0 0 0 0 0 0 Reset value LPTIM_ICR 0x004 0 0 0 0 0 0 0 Reset value LPTIM_IER 0x008...
Page 677 RM0430 Low-power timer (LPTIM) Refer to Section 2.2.2 on page 58 for the register boundary addresses. RM0430 Rev 8 677/1324...
Page 678: Independent Watchdog (Iwdg)
Independent watchdog (IWDG) RM0430 Independent watchdog (IWDG) 22.1 IWDG introduction The devices feature two embedded watchdog peripherals that offer a combination of high safety level, timing accuracy and flexibility of use. Both watchdog peripherals (Independent and Window) serve to detect and resolve malfunctions due to software failure, and to trigger system reset or an interrupt (window watchdog only) when the counter reaches a given timeout value.
Page 679: Debug Mode
RM0430 Independent watchdog (IWDG) A status register is available to indicate that an update of the prescaler or the down-counter reload value is on going. 22.3.3 Debug mode ® When the microcontroller enters debug mode (Cortex -M4 with FPU core halted), the IWDG counter either continues to work normally or stops, depending on DBG_IWDG_STOP configuration bit in DBG module.
Page 680: Iwdg Registers
Independent watchdog (IWDG) RM0430 22.4 IWDG registers Refer to Section 1.2 on page 52 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits). 22.4.1 Key register (IWDG_KR) Address offset: 0x00 Reset value: 0x0000 0000 (reset by Standby mode) Res.
Page 681: Prescaler Register (Iwdg_Pr)
RM0430 Independent watchdog (IWDG) 22.4.2 Prescaler register (IWDG_PR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 682: Reload Register (Iwdg_Rlr)
Independent watchdog (IWDG) RM0430 22.4.3 Reload register (IWDG_RLR) Address offset: 0x08 Reset value: 0x0000 0FFF (reset by Standby mode) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RL[11:0] Bits 31:12 Reserved, must be kept at reset value.
Page 683: Iwdg Register Map
RM0430 Independent watchdog (IWDG) Note: If several reload values or prescaler values are used by application, it is mandatory to wait until RVU bit is reset before changing the reload value and to wait until PVU bit is reset before changing the prescaler value. However, after updating the prescaler and/or the reload value it is not necessary to wait until RVU or PVU is reset before continuing code execution (even in case of low-power mode entry, the write operation is taken into account and will complete)
Page 684: Window Watchdog (Wwdg)
Window watchdog (WWDG) RM0430 Window watchdog (WWDG) 23.1 WWDG introduction The window watchdog is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the contents of the downcounter before the T6 bit becomes cleared.
Page 685: Figure 222. Watchdog Block Diagram
RM0430 Window watchdog (WWDG) Figure 222. Watchdog block diagram The application program must write in the WWDG_CR register at regular intervals during normal operation to prevent an MCU reset. This operation must occur only when the counter value is lower than the window register value. The value to be stored in the WWDG_CR register must be between 0xFF and 0xC0.
Page 686: How To Program The Watchdog Timeout
Window watchdog (WWDG) RM0430 In some applications, the EWI interrupt can be used to manage a software system check and/or system recovery/graceful degradation, without generating a WWDG reset. In this case, the corresponding interrupt service routine (ISR) should reload the WWDG counter to avoid the WWDG reset, then trigger the required actions.
Page 687: Debug Mode
RM0430 Window watchdog (WWDG) As an example, let us assume APB1 frequency is equal to 24 MHz, WDGTB[1:0] is set to 3 and T[5:0] is set to 63: ⁄ × × × t WWDG 24000 4096 21.85 ms Refer to the datasheets for the minimum and maximum values of the t WWDG.
Page 688: Wwdg Registers
Window watchdog (WWDG) RM0430 23.6 WWDG registers Refer to for a list of abbreviations used in register descriptions. Section 1.2 on page 52 The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits). 23.6.1 Control register (WWDG_CR) Address offset: 0x00 Reset value: 0x0000 007F Res.
Page 689: Configuration Register (Wwdg_Cfr)
RM0430 Window watchdog (WWDG) 23.6.2 Configuration register (WWDG_CFR) Address offset: 0x04 Reset value: 0x0000 007F Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WDGTB[1:0] W[6:0] Bits 31:10 Reserved, must be kept at reset value. Bit 9 EWI: Early wakeup interrupt When set, an interrupt occurs whenever the counter reaches the value 0x40.
Page 690: Wwdg Register Map
Window watchdog (WWDG) RM0430 23.6.4 WWDG register map The following table gives the WWDG register map and reset values. Table 123. WWDG register map and reset values Offset Register WWDG_CR T[6:0] 0x00 Reset value WWDG_CFR W[6:0] 0x04 Reset value WWDG_SR 0x08 Reset value Refer to...
Page 691: Aes Hardware Accelerator (Aes)
RM0430 AES hardware accelerator (AES) AES hardware accelerator (AES) 24.1 Introduction The AES hardware accelerator (AES) encrypts or decrypts data, using an algorithm and implementation fully compliant with the advanced encryption standard (AES) defined in Federal information processing standards (FIPS) publication 197. Multiple chaining modes are supported (ECB, CBC, CTR, GCM, GMAC, CCM), for key sizes of 128 or 256 bits.
Page 692: Aes Implementation
AES hardware accelerator (AES) RM0430 24.3 AES implementation The device has a single instance of AES peripheral. 24.4 AES functional description 24.4.1 AES block diagram Figure 224 shows the block diagram of AES. Figure 224. AES block diagram 24.4.2 AES internal signals Table 124 describes the user relevant internal signals interfacing the AES peripheral.
Page 693: Aes Cryptographic Core
RM0430 AES hardware accelerator (AES) 24.4.3 AES cryptographic core Overview The AES cryptographic core consists of the following components: • AES algorithm (AEA) • multiplier over a binary Galois field (GF2mul) • key input • initialization vector (IV) input • chaining algorithm logic (XOR, feedback/counter, mask) The AES core works on 128-bit data blocks (four words) with 128-bit or 256-bit key length.
Page 694: Figure 225. Ecb Encryption And Decryption Principle
AES hardware accelerator (AES) RM0430 Chaining modes The following chaining modes are supported by AES, selected through the CHMOD[2:0] bitfield of the AES_CR register: • Electronic code book (ECB) • Cipher block chaining (CBC) • Counter (CTR) • Galois counter mode (GCM) •...
Page 695: Figure 226. Cbc Encryption And Decryption Principle
RM0430 AES hardware accelerator (AES) Cipher block chaining (CBC) mode Figure 226. CBC encryption and decryption principle In CBC mode the output of each block chains with the input of the following block. To make each message unique, an initialization vector is used during the first block processing. Note: For decryption, a special key scheduling is required before processing the first block.
Page 696: Figure 227. Ctr Encryption And Decryption Principle
AES hardware accelerator (AES) RM0430 Counter (CTR) mode Figure 227. CTR encryption and decryption principle The CTR mode uses the AES core to generate a key stream. The keys are then XORed with the plaintext to obtain the ciphertext as specified in NIST Special Publication 800-38A, Recommendation for Block Cipher Modes of Operation.
Page 697: Figure 228. Gcm Encryption And Authentication Principle
RM0430 AES hardware accelerator (AES) Galois/counter mode (GCM) Figure 228. GCM encryption and authentication principle In Galois/counter mode (GCM), the plaintext message is encrypted while a message authentication code (MAC) is computed in parallel, thus generating the corresponding ciphertext and its MAC (also known as authentication tag). It is defined in NIST Special Publication 800-38D, Recommendation for Block Cipher Modes of Operation - Galois/Counter Mode (GCM) and GMAC.
Page 698: Aes Procedure To Perform A Cipher Operation
AES algorithm. AES accelerates the execution of the AES-128 and AES-256 cryptographic algorithms in ECB, CBC, CTR, CCM, and GCM operating modes. Note: For more details on the cryptographic library, refer to the UM1924 user manual “STM32 crypto library” available from www.st.com. 698/1324 RM0430 Rev 8...
Page 699: Figure 231. Stm32 Cryptolib Aes Flowchart Examples
RM0430 AES hardware accelerator (AES) Figure 231. STM32 cryptolib AES flowchart examples RM0430 Rev 8 699/1324...
Page 700: Figure 232. Stm32 Cryptolib Aes Flowchart Examples (Continued)
AES hardware accelerator (AES) RM0430 Figure 232. STM32 cryptolib AES flowchart examples (continued) Initialization of AES To initialize AES, first disable it by clearing the EN bit of the AES_CR register. Then perform the following steps in any order: • Configure the AES mode, by programming the MODE[1:0] bitfield of the AES_CR register.
Page 701 RM0430 AES hardware accelerator (AES) Data append This section describes different ways of appending data for processing, where the size of data to process is not a multiple of 128 bits. For ECB, CBC and GCM encryption mode, refer to Section 24.4.6: AES ciphertext stealing and data padding.
Page 702: Aes Decryption Key Preparation
AES hardware accelerator (AES) RM0430 Data append using DMA With this method, all the transfers and processing are managed by DMA and AES. To use the method, proceed as follows: Prepare the last four-word data block (if the data to process does not fill it completely), by padding the remainder of the block with zeros.
Page 703: Aes Ciphertext Stealing And Data Padding
RM0430 AES hardware accelerator (AES) Figure 233. Encryption key derivation for ECB/CBC decryption (Mode 2) If the software stores the initial key prepared for decryption, it is enough to do the key schedule operation only once for all the data to be decrypted with a given cipher key. Note: The operation of the key preparation lasts 80 or 109 clock cycles, depending on the key size (128- or 256-bit).
Page 704: Aes Task Suspend And Resume
AES hardware accelerator (AES) RM0430 Disable the AES peripheral by clearing the EN bit of the AES_CR register Change the mode to CTR by writing 010 to the CHMOD[2:0] bitfield of the AES_CR register. Pad the last block (smaller than 128 bits) with zeros to have a complete block of 128 bits, then write it into AES_DINR register.
Page 705: Aes Basic Chaining Modes (Ecb, Cbc)
RM0430 AES hardware accelerator (AES) 24.4.8 AES basic chaining modes (ECB, CBC) Overview This section gives a brief explanation of the four basic operation modes provided by the AES computing core: ECB encryption, ECB decryption, CBC encryption and CBC decryption. For detailed information, refer to the FIPS publication 197 from November 26, 2001.
Page 706: Figure 237. Cbc Encryption
AES hardware accelerator (AES) RM0430 In ECB decrypt mode, the 128-bit ciphertext input data block C1 in the AES_DINR register first goes through bit/byte/half-word swapping. The keying sequence is reversed compared to that of the ECB encryption. The swap result I1 is processed with the AES core set in decrypt mode, using the formerly prepared decryption key.
Page 707: Figure 239. Ecb/Cbc Encryption (Mode 1)
RM0430 AES hardware accelerator (AES) In CBC decrypt mode, like in ECB decrypt mode, the secret key must be prepared to perform an AES decryption. After the key preparation process, the decryption goes as follows: the first 128-bit ciphertext block (after the swap operation) is used directly as the AES core input block I1 for decrypt operation, using the 128-bit or 256-bit key.
Page 708: Figure 240. Ecb/Cbc Decryption (Mode 3)
AES hardware accelerator (AES) RM0430 ECB/CBC decryption sequence The sequence of events to perform an AES ECB/CBC decryption is as follows (more detail Section 24.4.4): Follow the steps described in Section 24.4.5: AES decryption key preparation on page 702, in order to prepare the decryption key in AES core. Disable the AES peripheral by clearing the EN bit of the AES_CR register.
Page 709 RM0430 AES hardware accelerator (AES) then stop the DMA transfers from the OUT FIFO by clearing the DMAOUTEN bit of the AES_CR register. If DMA is not used, poll the CCF flag of the AES_SR register until it becomes 1 (computation completed).
Page 710: Aes Counter (Ctr) Mode
AES hardware accelerator (AES) RM0430 Note: When mode 4 is selected mode 3 cannot be used. In mode 4, the AES_KEYRx registers contain the encryption key during all phases of the processing. No derivation key is stored in these registers. It is stored internally in AES. 24.4.9 AES counter (CTR) mode Overview...
Page 711: Table 125. Ctr Mode Initialization Vector Definition
RM0430 AES hardware accelerator (AES) Figure 242. CTR encryption Figure 243. CTR decryption In CTR mode, the cryptographic core output (also called keystream) Ox is XOR-ed with relevant input block (Px' for encryption, Cx' for decryption), to produce the correct output block (Cx' for encryption, Px' for decryption).
Page 712: Aes Galois/Counter Mode (Gcm)
AES hardware accelerator (AES) RM0430 encryption) or ciphertext (CTR decryption) input. In CTR mode, the MODE[1:0] bitfield settings 11, 10 or 00 default all to encryption mode, and the setting 01 (key derivation) is forbidden. The sequence of events to perform an encryption or a decryption in CTR chaining mode: Ensure that AES is disabled (the EN bit of the AES_CR must be 0).
Page 713: Table 126. Gcm Last Block Definition
RM0430 AES hardware accelerator (AES) Figure 244. Message construction in GCM The message has the following structure: • 16-byte initial counter block (ICB), composed of two distinct fields: – Initialization vector (IV): a 96-bit value that must be unique for each encryption cycle with a given key.
Page 714: Table 127. Gcm Mode Ivi Bitfield Initialization
AES hardware accelerator (AES) RM0430 GCM processing Figure 245 describes the GCM implementation in the AES peripheral. The GCM is selected by writing 011 to the CHMOD[2:0] bitfield of the AES_CR register. Figure 245. GCM authenticated encryption The mechanism for the confidentiality of the plaintext in GCM mode is similar to that in the Counter mode, with a particular increment function (denoted 32-bit increment) that generates the sequence of input counter blocks.
Page 715 RM0430 AES hardware accelerator (AES) The authentication mechanism in GCM mode is based on a hash function called GF2mul that performs multiplication by a fixed parameter, called hash subkey (H), within a binary Galois field. A GCM message is processed through the following phases, further described in next subsections: •...
Page 716 AES hardware accelerator (AES) RM0430 GCM payload phase This phase, identical for encryption and decryption, is executed after the GCM header phase. During this phase, the encrypted/decrypted payload is stored in the AES_DOUTR register. The sequence to execute is: If the header phase was skipped, enable the AES peripheral by setting the EN bit of the AES_CR register.
Page 717: Aes Galois Message Authentication Code (Gmac)
RM0430 AES hardware accelerator (AES) Suspend/resume operations in GCM mode To suspend the processing of a message, proceed as follows: If DMA is used, stop the AES DMA transfers to the IN FIFO by clearing the DMAINEN bit of the AES_CR register. If DMA is not used, make sure that the current computation is completed, which is indicated by the CCF flag of the AES_SR register set to 1.
Page 718: Figure 246. Message Construction In Gmac Mode
AES hardware accelerator (AES) RM0430 A typical message construction for GMAC is given in Figure 246. Figure 246. Message construction in GMAC mode AES GMAC processing Figure 247 describes the GMAC mode implementation in the AES peripheral. This mode is selected by writing 011 to the CHMOD[2:0] bitfield of the AES_CR register.
Page 719: Aes Counter With Cbc-Mac (Ccm)
RM0430 AES hardware accelerator (AES) 24.4.12 AES counter with CBC-MAC (CCM) Overview The AES counter with cipher block chaining-message authentication code (CCM) algorithm allows encryption and authentication of plaintext, generating the corresponding ciphertext and tag (also known as message authentication code). To ensure confidentiality, the CCM algorithm is based on AES in counter mode.
Page 720 AES hardware accelerator (AES) RM0430 standard also states that, on MSB bits of the first message block (B1), the associated data length expressed in bytes (a) must be encoded as follows: – If 0 < a < 2 , then it is encoded as [a] , that is, on two bytes.
Page 721: Table 128. Initialization Of Aes_Ivrx Registers In Ccm Mode
RM0430 AES hardware accelerator (AES) CCM processing Figure 249 describes the CCM implementation within the AES peripheral (decryption example). Figure 249. CCM mode authenticated decryption The data input to the generation-encryption process are a valid nonce, a valid payload string, and a valid associated data string, all properly formatted. The CBC chaining mechanism is applied to the formatted plaintext data to generate a MAC, with a known length.
Page 722 AES hardware accelerator (AES) RM0430 A CCM message is processed through two distinct processes - first, payload encryption or decryption, in which the AES peripheral is configured in CTR mode, then associated data and payload authentication, in which the AES peripheral first executes the CCM header phase, then the CCM final phase.
Page 723 RM0430 AES hardware accelerator (AES) In final phase, the AES peripheral generates the CCM authentication tag and stores it in the AES_DOUTR register: 11. Indicate the final phase, by setting to 11 the GCMPH[1:0] bitfield of the AES_CR register. Keep as-is the encryption mode in the MODE[1:0] bitfield. 12.
Page 724: Aes Data Registers And Data Swapping
AES hardware accelerator (AES) RM0430 To resume the authentication of the associated data and payload (GCMPH[1:0]= 01 or 11), proceed as follows: If DMA is used, configure the DMA controller in order to complete the rest of the FIFO IN transfers. Ensure that AES processor is disabled (the EN bit of the AES_CR register must be 0).
Page 725: Figure 250. 128-Bit Block Construction With Respect To Data Swap
RM0430 AES hardware accelerator (AES) Figure 250. 128-bit block construction with respect to data swap Note: The data in AES key registers (AES_KEYRx) and initialization registers (AES_IVRx) are not sensitive to the swap mode selection. Data padding Figure 250 also gives an example of memory data block padding with zeros such that the zeroed bits after the data swap form a contiguous zone at the MSB end of the AES core input buffer.
Page 726: Aes Key Registers
AES hardware accelerator (AES) RM0430 24.4.14 AES key registers The AES_KEYRx registers store the encryption or decryption key bitfield KEY[127:0] or KEY[255:0]. The data to write to or to read from each register is organized in the memory in little-endian order, that is, with most significant byte on the highest address. The key is spread over the eight registers as shown in Table 129.
Page 727: Table 130. Dma Channel Configuration For Memory-To-Aes Data Transfer
RM0430 AES hardware accelerator (AES) Table 130. DMA channel configuration for memory-to-AES data transfer DMA channel control Recommended configuration register field Message length: a multiple of 128 bits. According to the algorithm and the mode selected, special padding/ Transfer size ciphertext stealing might be required.
Page 728: Table 131. Dma Channel Configuration For Aes-To-Memory Data Transfer
AES hardware accelerator (AES) RM0430 Table 131. DMA channel configuration for AES-to-memory data transfer DMA channel control Recommended configuration register field It is the message length multiple of AES block size (4 words). According to Transfer size the case extra bytes will have to be discarded. Source burst size Single (peripheral)
Page 729: Aes Error Management
RM0430 AES hardware accelerator (AES) in ECB/CBC modes Section 24.4.8: AES basic chaining modes (ECB, CBC) as example. 24.4.17 AES error management The read error flag (RDERR) and write error flag (WRERR) of the AES_SR register are set when an unexpected read or write operation, respectively, is detected. An interrupt can be generated if the error interrupt enable (ERRIE) bit of the AES_CR register is set.
Page 730: Aes Processing Latency
AES hardware accelerator (AES) RM0430 The status of the individual maskable interrupt sources can be read from the AES_SR register. Table 132 gives a summary of the interrupt sources, their event flags and enable bits. Table 132. AES interrupt requests AES interrupt event Event flag Enable bit...
Page 731: Aes Registers
RM0430 AES hardware accelerator (AES) Note: Data insertion can include wait states forced by AES on the AHB bus (maximum 3 cycles, typical 1 cycle). This applies to all header/payload/tag phases. 24.7 AES registers 24.7.1 AES control register (AES_CR) Address offset: 0x00 Reset value: 0x0000 0000 KEYSI CHMO...
Page 732 AES hardware accelerator (AES) RM0430 Bit 12 DMAOUTEN: DMA output enable This bit enables/disables data transferring with DMA, in the output phase: 0: Disable 1: Enable When the bit is set, DMA requests are automatically generated by AES during the output data phase.
Page 733 RM0430 AES hardware accelerator (AES) Bits 6:5 CHMOD[1:0]: Chaining mode selection, bits [1:0] These bits, together with the bit CHMOD[2] (see bit 16 of this register), form CHMOD[2:0] bitfield that selects the AES chaining mode: 000: Electronic codebook (ECB) 001: Cipher-Block Chaining (CBC) 010: Counter Mode (CTR) 011: Galois Counter Mode (GCM) and Galois Message Authentication Code (GMAC) 100: Counter with CBC-MAC (CCM)
Page 734: Aes Status Register (Aes_Sr)
AES hardware accelerator (AES) RM0430 24.7.2 AES status register (AES_SR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 735: Aes Data Input Register (Aes_Dinr)
RM0430 AES hardware accelerator (AES) Bit 2 WRERR: Write error This flag indicates the detection of an unexpected write operation to the AES_DINR register (during computation or data output phase): 0: Not detected 1: Detected The flag is set by hardware. It is cleared by software upon setting the ERRC bit of the AES_CR register.
Page 736: Aes Data Output Register (Aes_Doutr)
AES hardware accelerator (AES) RM0430 Bits 31:0 DIN[x+31:x]: One of four 32-bit words of a 128-bit input data block being written into the peripheral This bitfield feeds a 32-bit input buffer. A 4-fold sequential write to this bitfield during the input phase virtually writes a complete 128-bit block of input data to the AES peripheral.
Page 737: Aes Key Register 1 (Aes_Keyr1)
RM0430 AES hardware accelerator (AES) KEY[31:16] KEY[15:0] Bits 31:0 KEY[31:0]: Cryptographic key, bits [31:0] This bitfield contains the bits [31:0] of the AES encryption or decryption key, depending on the operating mode: - In Mode 1 (encryption), Mode 2 (key derivation) and Mode 4 (key derivation then single decryption): the value to write into the bitfield is the encryption key.
Page 738: Aes Key Register 3 (Aes_Keyr3)
AES hardware accelerator (AES) RM0430 Bits 31:0 KEY[95:64]: Cryptographic key, bits [95:64] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield. 24.7.8 AES key register 3 (AES_KEYR3) Address offset: 0x1C Reset value: 0x0000 0000 KEY[127:112] KEY[111:96] Bits 31:0 KEY[127:96]: Cryptographic key, bits [127:96] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.
Page 739: Aes Initialization Vector Register 2 (Aes_Ivr2)
RM0430 AES hardware accelerator (AES) IVI[63:48] IVI[47:32] Bits 31:0 IVI[63:32]: Initialization vector input, bits [63:32] Refer to Section 24.4.15: AES initialization vector registers on page 726 for description of the IVI[127:0] bitfield. The initialization vector is only used in chaining modes other than ECB. The initialization vector may be written only when the AES peripheral is disabled.
Page 740: Aes Key Register 4 (Aes_Keyr4)
AES hardware accelerator (AES) RM0430 Bits 31:0 IVI[127:96]: Initialization vector input, bits [127:96] Refer to Section 24.4.15: AES initialization vector registers on page 726 for description of the IVI[127:0] bitfield. The initialization vector is only used in chaining modes other than ECB. The initialization vector may be written only when the AES peripheral is disabled.
Page 741: Aes Key Register 7 (Aes_Keyr7)
RM0430 AES hardware accelerator (AES) Bits 31:0 KEY[223:192]: Cryptographic key, bits [223:192] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield. 24.7.16 AES key register 7 (AES_KEYR7) Address offset: 0x3C Reset value: 0x0000 0000 KEY[255:240] KEY[239:224] Bits 31:0 KEY[255:224]: Cryptographic key, bits [255:224] Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.
Page 742: Aes Register Map
AES hardware accelerator (AES) RM0430 24.7.18 AES register map Table 135. AES register map and reset values Offset Register AES_CR 0x0000 Reset value AES_SR 0x0004 Reset value AES_DINR DIN[x+31:x] x=96,64,32,0 0x0008 Reset value AES_DOUTR DOUT[x+31:x] 0x000 x=96,64,32,0 Reset value AES_KEYR0 KEY[31:0] 0x0010 Reset value...
Page 743 RM0430 AES hardware accelerator (AES) Table 135. AES register map and reset values (continued) Offset Register AES_KEYR7 KEY[255:224] 0x003 Reset value AES_SUSP0R SUSP0[31:0] 0x0040 Reset value AES_SUSP1R SUSP1[31:0] 0x0044 Reset value AES_SUSP2R SUSP2[31:0] 0x0048 Reset value AES_SUSP3R SUSP3[31:0] 0x004 Reset value AES_SUSP4R SUSP4[31:0] 0x0050...
Page 744: Real-Time Clock (Rtc)
Real-time clock (RTC) RM0430 Real-time clock (RTC) 25.1 Introduction The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time-of-day clock/calendar, two programmable alarm interrupts, and a periodic programmable wakeup flag with interrupt capability. The RTC also includes an automatic wakeup unit to manage low power modes.
Page 745 RM0430 Real-time clock (RTC) – 0.95 ppm accuracy, obtained in a calibration window of several seconds • Timestamp function for event saving (1 event) • Tamper detection: – 2 tamper events with configurable filter and internal pull-up. • 20 backup registers (80 bytes). The backup registers are reset when a tamper detection event occurs.
Page 746: Rtc Functional Description
Real-time clock (RTC) RM0430 25.3 RTC functional description 25.3.1 Clock and prescalers The RTC clock source (RTCCLK) is selected through the clock controller among the LSE clock, the LSI oscillator clock, and the HSE clock. For more information on the RTC clock source configuration, refer to Section 6: Reset and clock control (RCC) for STM32F413/423.
Page 747: Programmable Alarms
RM0430 Real-time clock (RTC) Every two RTCCLK periods, the current calendar value is copied into the shadow registers, and the RSF bit of RTC_ISR register is set (see Section 25.6.4). The copy is not performed in Stop and Standby mode. When exiting these modes, the shadow registers are updated after up to two RTCCLK periods.
Page 748: Rtc Initialization And Configuration
Real-time clock (RTC) RM0430 complete (see Programming the wakeup timer), the timer starts counting down.When the wakeup function is enabled, the down-counting remains active in low power modes. In addition, when it reaches 0, the WUTF flag is set in the RTC_ISR register, and the wakeup counter is automatically reloaded with its reload value (RTC_WUTR register value).
Page 749 RM0430 Real-time clock (RTC) factor. Even if only one of the two fields needs to be changed, 2 separate write accesses must be performed to the RTC_PRER register. Load the initial time and date values in the shadow registers (RTC_TR and RTC_DR), and configure the time format (12 or 24 hours) through the FMT bit in the RTC_CR register.
Page 750: Reading The Calendar
Real-time clock (RTC) RM0430 25.3.6 Reading the calendar BYPSHAD control bit is cleared in the RTC_CR register When To read the RTC calendar registers (RTC_SSR, RTC_TR and RTC_DR) properly, the APB1 clock frequency (f ) must be equal to or greater than seven times the f PCLK1 RTCCLK clock frequency.
Page 751: Resetting The Rtc
RM0430 Real-time clock (RTC) 25.3.7 Resetting the RTC The calendar shadow registers (RTC_SSR, RTC_TR and RTC_DR) and some bits of the RTC status register (RTC_ISR) are reset to their default values by all available system reset sources. On the contrary, the following registers are resetted to their default values by a backup domain reset and are not affected by a system reset: the RTC current calendar registers, the RTC control register (RTC_CR), the prescaler register (RTC_PRER), the RTC calibration registers (RTC_CALIBR or RTC_CALR), the RTC shift register (RTC_SHIFTR),...
Page 752: Rtc Reference Clock Detection
Real-time clock (RTC) RM0430 25.3.9 RTC reference clock detection The RTC calendar update can be synchronized to a reference clock RTC_REFIN, usually the mains (50 or 60 Hz). The RTC_REFIN reference clock should have a higher precision than the 32.768 kHz LSE clock. When the RTC_REFIN detection is enabled (REFCKON bit of RTC_CR set to 1), the calendar is still clocked by the LSE, and RTC_REFIN is used to compensate for the imprecision of the calendar update frequency (1 Hz).
Page 753: Rtc Smooth Digital Calibration
RM0430 Real-time clock (RTC) When positive calibration is enabled (DCS = ‘0’), 2 ck_apre cycles are added every minute (around 15360 ck_apre cycles) for 2xDC minutes. This causes the calendar to be updated sooner, thereby adjusting the effective RTC frequency to be a bit higher. When negative calibration is enabled (DCS = ‘1’), 1 ck_apre cycle is removed every minute (around 15360 ck_apre cycles) for 2xDC minutes.
Page 754 Real-time clock (RTC) RM0430 The smooth calibration register (RTC_CALR) specifies the number of RTCCLK clock cycles to be masked during the 32-second cycle: • Setting the bit CALM[0] to 1 causes exactly one pulse to be masked during the 32- second cycle.
Page 755: Timestamp Function
RM0430 Real-time clock (RTC) Verifying the RTC calibration RTC precision is performed by measuring the precise frequency of RTCCLK and calculating the correct CALM value and CALP values. An optional 1 Hz output is provided to allow applications to measure and verify the RTC precision. Measuring the precise frequency of the RTC over a limited interval can result in a measurement error of up to 2 RTCCLK clock cycles over the measurement period, depending on how the digital calibration cycle is aligned with the measurement period.
Page 756: Tamper Detection
Real-time clock (RTC) RM0430 If a new timestamp event is detected while the timestamp flag (TSF) is already set, the timestamp overflow flag (TSOVF) flag is set and the timestamp registers (RTC_TSTR and RTC_TSDR) maintain the results of the previous event. Note: TSF is set 2 ck_apre cycles after the timestamp event occurs due to synchronization process.
Page 757: Calibration Clock Output
RM0430 Real-time clock (RTC) Edge detection on tamper inputs If the TAMPFLT bits are “00”, the TAMPER pins generate tamper detection events (RTC_TAMP[2:1]) when either a rising edge is observed or an falling edge is observed depending on the corresponding TAMPxTRG bit. The internal pull-up resistors on the TAMPER inputs are deactivated when edge detection is selected.
Page 758: Alarm Output
Real-time clock (RTC) RM0430 The RTC_CALIB output is not impacted by the calibration value programmed in RTC_CALIBR register. The RTC_CALIB duty cycle is irregular: there is a light jitter on falling edges. It is therefore recommended to use rising edges. If COSEL is set and “PREDIV_S+1”...
Page 759: Rtc Interrupts
RM0430 Real-time clock (RTC) 25.5 RTC interrupts All RTC interrupts are connected to the EXTI controller. To enable the RTC Alarm interrupt, the following sequence is required: Configure and enable the EXTI Line 17 in interrupt mode and select the rising edge sensitivity.
Page 760: Rtc Registers
Bits 14:12 MNT[2:0]: Minute tens in BCD format Bits 11:8 MNU[3:0]: Minute units in BCD format Bit 7 Reserved, must be kept at reset value. Bits 6:4 ST[2:0]: Second tens in BCD format Bits 3:0 SU[3:0]: Second units in BCD format Note: This register is write protected.
Page 761: Rtc Date Register (Rtc_Dr)
RM0430 Real-time clock (RTC) 25.6.2 RTC date register (RTC_DR) The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration Reading the calendar. Address offset: 0x04 Backup domain reset value: 0x0000_2101 System reset: 0x0000 2101 when BYPSHAD = 0.
Page 762: Rtc Control Register (Rtc_Cr)
Real-time clock (RTC) RM0430 25.6.3 RTC control register (RTC_CR) Address offset: 0x08 Backup domain reset value: 0x0000 0000 System reset: not affected Res. Res. Res. Res. Res. Res. Res. Res. OSEL[1:0] COSEL BKP SUB1H ADD1H TSIE WUTIE ALRBIE ALRAIE WUTE ALRBE ALRAE DCE FMT BYPSHAD REFCKON TSEDGE WUCKSEL[2:0] Bits 31:24 Reserved, must be kept at reset value.
Page 763 RM0430 Real-time clock (RTC) Bit 16 ADD1H: Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0. 0: No effect 1: Adds 1 hour to the current time. This can be used for summer time change Bit 15 TSIE: Timestamp interrupt enable 0: Timestamp Interrupt disable 1: Timestamp Interrupt enable...
Page 764: Rtc Initialization And Status Register (Rtc_Isr)
Real-time clock (RTC) RM0430 Bit 4 REFCKON: Reference clock detection enable (50 or 60 Hz) 0: Reference clock detection disabled 1: Reference clock detection enabled Note: PREDIV_S must be 0x00FF. Bit 3 TSEDGE: Timestamp event active edge 0: TIMESTAMP rising edge generates a timestamp event 1: TIMESTAMP falling edge generates a timestamp event TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting Bits 2:0 WUCKSEL[2:0]: Wakeup clock selection...
Page 765 RM0430 Real-time clock (RTC) Bit 13 TAMP1F: Tamper detection flag This flag is set by hardware when a tamper detection event is detected. It is cleared by software writing 0. Bit 12 TSOVF: Timestamp overflow flag This flag is set by hardware when a timestamp event occurs while TSF is already set. This flag is cleared by software by writing 0.
Page 766: Rtc Prescaler Register (Rtc_Prer)
Real-time clock (RTC) RM0430 Bit 3 SHPF: Shift operation pending 0: No shift operation is pending 1: A shift operation is pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR.
Page 767: Rtc Wakeup Timer Register (Rtc_Wutr)
RM0430 Real-time clock (RTC) Bits 31:23 Reserved, must be kept at reset value Bits 22:16 PREDIV_A[6:0]: Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1) Bit 15 Reserved, must be kept at reset value. Bits 14:0 PREDIV_S[14:0]: Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1) Note:...
Page 768 Real-time clock (RTC) RM0430 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DC[4:0] Bits 31:8 Reserved, must be kept at reset value Bit 7 DCS: Digital calibration sign 0: Positive calibration: calendar update frequency is increased 1: Negative calibration: calendar update frequency is decreased...
Page 769: Rtc Alarm A Register (Rtc_Alrmar)
Bit 7 MSK1: Alarm A seconds mask 0: Alarm A set if the seconds match 1: Seconds don’t care in Alarm A comparison Bits 6:4 ST[2:0]: Second tens in BCD format. Bits 3:0 SU[3:0]: Second units in BCD format. Note: This register can be written only when ALRAWF is set to 1 in RTC_ISR, or in initialization mode.
Page 770: Rtc Alarm B Register (Rtc_Alrmbr)
Bit 7 MSK1: Alarm B seconds mask 0: Alarm B set if the seconds match 1: Seconds don’t care in Alarm B comparison Bits 6:4 ST[2:0]: Second tens in BCD format Bits 3:0 SU[3:0]: Second units in BCD format Note: This register can be written only when ALRBWF is set to 1 in RTC_ISR, or in initialization mode.
Page 771: Rtc Write Protection Register (Rtc_Wpr)
RM0430 Real-time clock (RTC) 25.6.10 RTC write protection register (RTC_WPR) Address offset: 0x24 Backup domain reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 772: Rtc Shift Control Register (Rtc_Shiftr)
Real-time clock (RTC) RM0430 25.6.12 RTC shift control register (RTC_SHIFTR) Address offset: 0x2C Backup domain reset value: 0x0000 0000 System reset: not affected ADD1S Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SUBFS[14:0] Bit 31 ADD1S: Add one second 0: No effect...
Page 773: Rtc Time Stamp Time Register (Rtc_Tstr)
Bits 14:12 MNT[2:0]: Minute tens in BCD format. Bits 11:8 MNU[3:0]: Minute units in BCD format. Bit 7 Reserved, must be kept at reset value. Bits 6:4 ST[2:0]: Second tens in BCD format. Bits 3:0 SU[3:0]: Second units in BCD format. Note: The content of this register is valid only when TSF is set to 1 in RTC_ISR.
Page 774: Rtc Timestamp Sub Second Register (Rtc_Tsssr)
Real-time clock (RTC) RM0430 Bits 31:16 Reserved, must be kept at reset value. Bits 15:13 WDU[1:0]: Week day units Bit 12 MT: Month tens in BCD format Bits 11:8 MU[3:0]: Month units in BCD format Bits 7:6 Reserved, must be kept at reset value. Bits 5:4 DT[1:0]: Date tens in BCD format Bits 3:0 DU[3:0]: Date units in BCD format Note:...
Page 775: Rtc Tamper And Alternate Function Configuration Register
RM0430 Real-time clock (RTC) Bits 31:16 Reserved, must be kept at reset value Bit 15 CALP: Increase frequency of RTC by 488.5 ppm 0: No RTCCLK pulses are added. 1: One RTCCLK pulse is effectively inserted every 2 pulses (frequency increased by 488.5 ppm).
Page 776 Real-time clock (RTC) RM0430 Bits 31:19 Reserved, must be kept at reset value. Always read as 0. Bit 18 ALARMOUTTYPE: RTC_ALARM output type 0: RTC_ALARM is an open-drain output 1: RTC_ALARM is a push-pull output Bit 17 TSINSEL: TIMESTAMP mapping 0: RTC_AF1 used as TIMESTAMP 1: Reserved Bit 16 TAMP1INSEL: TAMPER1 mapping...
Page 777: Rtc Alarm A Sub Second Register (Rtc_Alrmassr)
RM0430 Real-time clock (RTC) Bits 6:3 Reserved. Always read as 0. Bit 2 TAMPIE: Tamper interrupt enable 0: Tamper interrupt disabled 1: Tamper interrupt enabled Bit 1 TAMP1TRG: Active level for tamper 1 if TAMPFLT != 00: 0: TAMPER1 staying low triggers a tamper detection event. 1: TAMPER1 staying high triggers a tamper detection event.
Page 778: Rtc Alarm B Sub Second Register (Rtc_Alrmbssr)
Real-time clock (RTC) RM0430 Bits 23:15 Reserved, must be kept at reset value Bits 14:0 SS[14:0]: Sub seconds value This value is compared with the contents of the synchronous prescaler’s counter to determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. Note: This register can be written only when ALRAE is reset in RTC_CR register, or in initialization mode.
Page 779: Rtc Backup Registers (Rtc_Bkpxr)
This register is reset on a tamper detection event, as long as TAMPxF=1. 25.6.21 RTC register map Table 138. RTC register map and reset values Offset Register RTC_TR HU[3:0] MNT[2:0] MNU[3:0] ST[2:0] SU[3:0] [1:0] 0x00 Reset value RTC_DR YT[3:0] YU[3:0] WDU[2:0] MU[3:0]...
Page 780 Real-time clock (RTC) RM0430 Table 138. RTC register map and reset values (continued) Offset Register RTC_ALRMAR DU[3:0] HU[3:0] MNT[2:0] MNU[3:0] ST[2:0] SU[3:0] [1:0] [1:0] 0x1C Reset value RTC_ALRMBR DU[3:0] HU[3:0] MNT[2:0] MNU[3:0] ST[2:0] SU[3:0] [1:0] [1:0] 0x20 Reset value RTC_WPR...
Page 781 RM0430 Real-time clock (RTC) Table 138. RTC register map and reset values (continued) Offset Register RTC_BKP0R BKP[31:0] Reset value 0x50 to 0x9C BKP[31:0] RTC_BKP19R Reset value Refer to Section 2.2.2 on page 58 for the register boundary addresses. Caution: Table 138, the reset value is the value after a backup domain reset.
Page 782: Fast-Mode Plus Inter-Integrated Circuit (Fmpi2C) Interface
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 26.1 Introduction The I C (inter-integrated circuit) bus interface handles communications between the microcontroller and the serial I C bus. It provides multimaster capability, and controls all I bus-specific sequencing, protocol, arbitration and timing.
Page 783: Fmpi2C Implementation
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface The following additional features are also available depending on the product implementation (see Section 26.3: FMPI2C implementation): • SMBus specification rev 3.0 compatibility: – Hardware PEC (Packet Error Checking) generation and verification with ACK control –...
Page 784: Fmpi2C Block Diagram
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 26.4.1 FMPI2C block diagram The block diagram of the FMPI2C interface is shown in Figure 255. Figure 255. FMPI2C block diagram The FMPI2C is clocked by an independent clock source which allows to the FMPI2C to operate independently from the PCLK frequency.
Page 785: Fmpi2C Clock Requirements
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 26.4.2 FMPI2C clock requirements The FMPI2C kernel is clocked by FMPI2CCLK. The FMPI2CCLK period t must respect the following conditions: I2CCLK < (t ) / 4 and t < t I2CCLK filters I2CCLK HIGH with: : SCL low time and t...
Page 786: Fmpi2C Initialization
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Figure 256. I C bus protocol Acknowledge can be enabled or disabled by software. The FMPI2C interface addresses can be selected by software. 26.4.4 FMPI2C initialization Enabling and disabling the peripheral The FMPI2C peripheral clock must be configured and enabled in the clock controller (refer Section 6: Reset and clock control (RCC) for STM32F413/423).
Page 787: Figure 257. Setup And Hold Timings
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface FMPI2C timings The timings must be configured in order to guarantee a correct data hold and setup time, used in master and slave modes. This is done by programming the PRESC[3:0], SCLDEL[3:0] and SDADEL[3:0] bits in the FMPI2C_TIMINGR register. The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C configuration window Figure 257.
Page 788: Table 140. I2C-Smbus Specification Data Setup And Hold Times
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 • When the SCL falling edge is internally detected, a delay is inserted before sending SDA output. This delay is where = SDADEL x t = (PRESC+1) SDADEL PRESC I2CCLK PRESC I2CCLK impacts the hold time SDADEL HD;DAT.
Page 789 RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface The SDA and SCL transition time values to be used are the ones in the application. Using the maximum values from the standard increases the constraints for the SDADEL and SCLDEL calculation, but ensures the feature whatever the application. Note: At every clock pulse, after SCL falling edge detection, the I2C master or slave stretches SCL low during at least [(SDADEL+SCLDEL+1) x (PRESC+1) + 1] x t...
Page 790: Software Reset
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Figure 258. FMPI2C initialization flowchart 26.4.5 Software reset A software reset can be performed by clearing the PE bit in the FMPI2C_CR1 register. In that case FMPI2C lines SCL and SDA are released. Internal states machines are reset and communication control bits, as well as status bits come back to their reset value.
Page 791: Data Transfer
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 26.4.6 Data transfer The data transfer is managed through transmit and receive data registers and a shift register. Reception The SDA input fills the shift register. After the 8th SCL pulse (when the complete data byte is received), the shift register is copied into FMPI2C_RXDR register if it is empty (RXNE=0).
Page 792: Figure 260. Data Transmission
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Transmission If the FMPI2C_TXDR register is not empty (TXE=0), its content is copied into the shift register after the 9th SCL pulse (the Acknowledge pulse). Then the shift register content is shifted out on SDA line. If TXE=1, meaning that no data is written yet in FMPI2C_TXDR, SCL line is stretched low until FMPI2C_TXDR is written.
Page 793: Fmpi2C Slave Mode
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface When RELOAD=0 in master mode, the counter can be used in 2 modes: • Automatic end mode (AUTOEND = ‘1’ in the FMPI2C_CR2 register). In this mode, the master automatically sends a STOP condition once the number of bytes programmed in the NBYTES[7:0] bit field has been transferred.
Page 794 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 By default, the slave uses its clock stretching capability, which means that it stretches the SCL signal at low level when needed, in order to perform software actions. If the master does not support clock stretching, the FMPI2C must be configured with NOSTRETCH=1 in the FMPI2C_CR1 register.
Page 795: Figure 261. Slave Initialization Flowchart
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Slave Byte Control mode In order to allow byte ACK control in slave reception mode, Slave Byte Control mode must be enabled by setting the SBC bit in the FMPI2C_CR1 register. This is required to be compliant with SMBus standards.
Page 796 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Slave transmitter A transmit interrupt status (TXIS) is generated when the FMPI2C_TXDR register becomes empty. An interrupt is generated if the TXIE bit is set in the FMPI2C_CR1 register. The TXIS bit is cleared when the FMPI2C_TXDR register is written with the next data byte to be transmitted.
Page 797: Figure 262. Transfer Sequence Flowchart For Fmpi2C Slave Transmitter, Nostretch=0
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 262. Transfer sequence flowchart for FMPI2C slave transmitter, NOSTRETCH=0 RM0430 Rev 8 797/1324...
Page 798: Figure 263. Transfer Sequence Flowchart For Fmpi2C Slave Transmitter, Nostretch=1
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Figure 263. Transfer sequence flowchart for FMPI2C slave transmitter, NOSTRETCH=1 798/1324 RM0430 Rev 8...
Page 799: Figure 264. Transfer Bus Diagrams For Fmpi2C Slave Transmitter
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 264. Transfer bus diagrams for FMPI2C slave transmitter RM0430 Rev 8 799/1324...
Page 800: Figure 265. Transfer Sequence Flowchart For Slave Receiver With Nostretch=0
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Slave receiver RXNE is set in FMPI2C_ISR when the FMPI2C_RXDR is full, and generates an interrupt if RXIE is set in FMPI2C_CR1. RXNE is cleared when FMPI2C_RXDR is read. When a STOP is received and STOPIE is set in FMPI2C_CR1, STOPF is set in FMPI2C_ISR and an interrupt is generated.
Page 801: Figure 266. Transfer Sequence Flowchart For Slave Receiver With Nostretch=1
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 266. Transfer sequence flowchart for slave receiver with NOSTRETCH=1 Figure 267. Transfer bus diagrams for FMPI2C slave receiver RM0430 Rev 8 801/1324...
Page 802: Fmpi2C Master Mode
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 26.4.8 FMPI2C master mode FMPI2C master initialization Before enabling the peripheral, the FMPI2C master clock must be configured by setting the SCLH and SCLL bits in the FMPI2C_TIMINGR register. The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C Configuration window.
Page 803: Figure 268. Master Clock Generation
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 268. Master clock generation Caution: In order to be I C or SMBus compliant, the master clock must respect the timings given below: RM0430 Rev 8 803/1324...
Page 804: Table 142. I2C-Smbus Specification Clock Timings
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Table 142. I C-SMBUS specification clock timings Standard- Fast-mode Fast-mode SMBUS mode (Sm) (Fm) Plus (Fm+) Symbol Parameter Unit SCL clock frequency 1000 Hold time (repeated) START condition 0.26 µs HD:STA Set-up time for a repeated START 0.26 µs SU:STA...
Page 805: Figure 269. Master Initialization Flowchart
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface master will re-launch automatically the slave address transmission until ACK is received. In this case ADDRCF must be set if a NACK is received from the slave, in order to stop sending the slave address. If the FMPI2C is addressed as a slave (ADDR=1) while the START bit is set, the FMPI2C switches to slave mode and the START bit is cleared when the ADDRCF bit is set.
Page 806: Figure 271. 10-Bit Address Read Access With Head10R=1
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 • If the master addresses a 10-bit address slave, transmits data to this slave and then reads data from the same slave, a master transmission flow must be done first. Then a repeated start is set with the 10 bit slave address configured with HEAD10R=1. In this case the master sends this sequence: ReStart + Slave address 10-bit header Read.
Page 807: Figure 272. Transfer Sequence Flowchart For Fmpi2C Master Transmitter For N≤255 Bytes
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 272. Transfer sequence flowchart for FMPI2C master transmitter for N≤255 bytes RM0430 Rev 8 807/1324...
Page 808: Figure 273. Transfer Sequence Flowchart For Fmpi2C Master Transmitter For N>255 Bytes
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Figure 273. Transfer sequence flowchart for FMPI2C master transmitter for N>255 bytes 808/1324 RM0430 Rev 8...
Page 809: Figure 274. Transfer Bus Diagrams For Fmpi2C Master Transmitter
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 274. Transfer bus diagrams for FMPI2C master transmitter RM0430 Rev 8 809/1324...
Page 810 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Master receiver In the case of a read transfer, the RXNE flag is set after each byte reception, after the 8th SCL pulse. An RXNE event generates an interrupt if the RXIE bit is set in the FMPI2C_CR1 register.
Page 811: Figure 275. Transfer Sequence Flowchart For Fmpi2C Master Receiver For N≤255 Bytes
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 275. Transfer sequence flowchart for FMPI2C master receiver for N≤255 bytes RM0430 Rev 8 811/1324...
Page 812: Figure 276. Transfer Sequence Flowchart For Fmpi2C Master Receiver For N >255 Bytes
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Figure 276. Transfer sequence flowchart for FMPI2C master receiver for N >255 bytes 812/1324 RM0430 Rev 8...
Page 813: Figure 277. Transfer Bus Diagrams For Fmpi2C Master Receiver
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 277. Transfer bus diagrams for FMPI2C master receiver RM0430 Rev 8 813/1324...
Page 814: Fmpi2C_Timingr Register Configuration Examples
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 26.4.9 FMPI2C_TIMINGR register configuration examples The tables below provide examples of how to program the FMPI2C_TIMINGR to obtain timings compliant with the I C specification. In order to get more accurate configuration values, the STM32CubeMX tool (I2C Configuration window) should be used. Table 143.
Page 815: Smbus Specific Features
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 2. t minimum value is 4 x t = 250 ns. Example with t = 1000 ns SYNC1 + SYNC2 I2CCLK SYNC1 + SYNC2 minimum value is 4 x t = 250 ns. Example with t = 750 ns SYNC1 + SYNC2...
Page 816 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Received Command and Data acknowledge control A SMBus receiver must be able to NACK each received command or data. In order to allow the ACK control in slave mode, the Slave Byte Control mode must be enabled by setting SBC bit in FMPI2C_CR1 register.
Page 817: Table 145. Smbus Timeout Specifications
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Timeouts This peripheral embeds hardware timers in order to be compliant with the 3 timeouts defined in SMBus specification. Table 145. SMBus timeout specifications Limits Symbol Parameter Unit Detect clock low timeout TIMEOUT Cumulative clock low extend time (slave device) LOW:SEXT Cumulative clock low extend time (master device)
Page 818: Smbus Initialization
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Bus idle detection A master can assume that the bus is free if it detects that the clock and data signals have been high for t greater than t . (refer to Table 140: I2C-SMBUS specification data IDLE HIGH setup and hold...
Page 819: Table 146. Smbus With Pec Configuration
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Table 146. SMBUS with PEC configuration Mode SBC bit RELOAD bit AUTOEND bit PECBYTE bit Master Tx/Rx NBYTES + PEC+ STOP Master Tx/Rx NBYTES + PEC + ReSTART Slave Tx/Rx with PEC Timeout detection The timeout detection is enabled by setting the TIMOUTEN and TEXTEN bits in the FMPI2C_TIMEOUTR register.
Page 820: Smbus: Fmpi2C_Timeoutr Register Configuration Examples
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Refer to Table 149: Examples of TIMEOUTA settings for various FMPI2CCLK frequencies (max tIDLE = 50 µs) Caution: Changing the TIMEOUTA and TIDLE configuration is not allowed when the TIMEOUTEN is set. SMBus: 26.4.12 FMPI2C_TIMEOUTR register configuration examples This section is relevant only when SMBus feature is supported.
Page 821: Figure 279. Transfer Sequence Flowchart For Smbus Slave Transmitter N Bytes + Pec
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface FMPI2C_PECR register is automatically transmitted if the master requests an extra byte after the NBYTES-1 data transfer. Caution: The PECBYTE bit has no effect when the RELOAD bit is set. Figure 279. Transfer sequence flowchart for SMBus slave transmitter N bytes + PEC RM0430 Rev 8 821/1324...
Page 822: Figure 280. Transfer Bus Diagrams For Smbus Slave Transmitter (Sbc=1)
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Figure 280. Transfer bus diagrams for SMBus slave transmitter (SBC=1) SMBus Slave receiver When the FMPI2C is used in SMBus mode, SBC must be programmed to ‘1’ in order to allow the PEC checking at the end of the programmed number of data bytes. In order to allow the ACK control of each byte, the reload mode must be selected (RELOAD=1).
Page 823: Figure 281. Transfer Sequence Flowchart For Smbus Slave Receiver N Bytes + Pec
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 281. Transfer sequence flowchart for SMBus slave receiver N Bytes + PEC RM0430 Rev 8 823/1324...
Page 824: Figure 282. Bus Transfer Diagrams For Smbus Slave Receiver (Sbc=1)
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Figure 282. Bus transfer diagrams for SMBus slave receiver (SBC=1) This section is relevant only when SMBus feature is supported. Refer to Section 26.3: FMPI2C implementation. In addition to FMPI2C master transfer management (refer to Section 26.4.8: FMPI2C master mode) some additional software flowcharts are provided to support SMBus.
Page 825: Figure 283. Bus Transfer Diagrams For Smbus Master Transmitter
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface When the SMBus master wants to send a RESTART condition after the PEC, software mode must be selected (AUTOEND=0). In this case, once NBYTES-1 have been transmitted, the FMPI2C_PECR register content is transmitted and the TC flag is set after the PEC transmission, stretching the SCL line low.
Page 826 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 SMBus Master receiver When the SMBus master wants to receive the PEC followed by a STOP at the end of the transfer, automatic end mode can be selected (AUTOEND=1). The PECBYTE bit must be set and the slave address must be programmed, before setting the START bit.
Page 827: Error Conditions
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 284. Bus transfer diagrams for SMBus master receiver 26.4.14 Error conditions The following are the error conditions which may cause communication to fail. Bus error (BERR) A bus error is detected when a START or a STOP condition is detected and is not located after a multiple of 9 SCL clock pulses.
Page 828 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 In case of a misplaced START or RESTART detection in slave mode, the FMPI2C enters address recognition state like for a correct START condition. When a bus error is detected, the BERR flag is set in the FMPI2C_ISR register, and an interrupt is generated if the ERRIE bit is set in the FMPI2C_CR1 register.
Page 829: Dma Requests
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Timeout Error (TIMEOUT) This section is relevant only when the SMBus feature is supported. Refer to Section 26.3: FMPI2C implementation. A timeout error occurs for any of these conditions: • TIDLE=0 and SCL remained low for the time defined in the TIMEOUTA[11:0] bits: this is used to detect a SMBus timeout.
Page 830: Debug Mode
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 NBYTES counter. Refer to Master transmitter on page 806. • In slave mode: – With NOSTRETCH=0, when all data are transferred using DMA, the DMA must be initialized before the address match event, or in ADDR interrupt subroutine, before clearing ADDR.
Page 831: Fmpi2C Interrupts
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 26.6 FMPI2C interrupts The table below gives the list of FMPI2C interrupt requests. Table 151. FMPI2C Interrupt requests Interrupt Enable Interrupt clear Exit the Exit the Interrupt event Event flag acronym control bit method Sleep mode Stop mode...
Page 832 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed.
Page 833 RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Bit 17 NOSTRETCH: Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. 0: Clock stretching enabled 1: Clock stretching disabled Note: This bit can only be programmed when the I2C is disabled (PE = 0).
Page 834: Control Register 2 (Fmpi2C_Cr2)
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Bit 5 STOPIE: Stop detection Interrupt enable 0: Stop detection (STOPF) interrupt disabled 1: Stop detection (STOPF) interrupt enabled Bit 4 NACKIE: Not acknowledge received Interrupt enable 0: Not acknowledge (NACKF) received interrupts disabled 1: Not acknowledge (NACKF) received interrupts enabled Bit 3 ADDRIE: Address match Interrupt enable (slave only) 0: Address match (ADDR) interrupts disabled...
Page 835 RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Bits 31:27 Reserved, must be kept at reset value. Bit 26 PECBYTE: Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0.
Page 836 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Bit 13 START: Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing ‘1’...
Page 837: Own Address 1 Register (Fmpi2C_Oar1)
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 26.7.3 Own address 1 register (FMPI2C_OAR1) Address offset: 0x08 Reset value: 0x0000 0000 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed.
Page 838: Own Address 2 Register (Fmpi2C_Oar2)
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 26.7.4 Own address 2 register (FMPI2C_OAR2) Address offset: 0x0C Reset value: 0x0000 0000 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed.
Page 839: Timing Register (Fmpi2C_Timingr)
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 26.7.5 Timing register (FMPI2C_TIMINGR) Address offset: 0x10 Reset value: 0x0000 0000 Access: No wait states PRESC[3:0] Res. Res. Res. Res. SCLDEL[3:0] SDADEL[3:0] SCLH[7:0] SCLL[7:0] Bits 31:28 PRESC[3:0]: Timing prescaler This field is used to prescale FMPI2CCLK in order to generate the clock period t used for PRESC data setup and hold counters (refer to...
Page 840: Timeout Register (Fmpi2C_Timeoutr)
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 26.7.6 Timeout register (FMPI2C_TIMEOUTR) Address offset: 0x14 Reset value: 0x0000 0000 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed.
Page 841: Interrupt And Status Register (Fmpi2C_Isr)
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 26.7.7 Interrupt and status register (FMPI2C_ISR) Address offset: 0x18 Reset value: 0x0000 0001 Access: No wait states Res. Res. Res. Res. Res. Res. Res. Res. ADDCODE[6:0] TIME BUSY Res. ALERT ARLO BERR STOPF NACKF ADDR RXNE TXIS Bits 31:24 Reserved, must be kept at reset value.
Page 842 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Bit 11 PECERR: PEC Error in reception This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit.
Page 843: Interrupt Clear Register (Fmpi2C_Icr)
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Bit 2 RXNE: Receive data register not empty (receivers) This bit is set by hardware when the received data is copied into the FMPI2C_RXDR register, and is ready to be read. It is cleared when FMPI2C_RXDR is read. Note: This bit is cleared by hardware when PE=0.
Page 844: Pec Register (Fmpi2C_Pecr)
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Bit 10 OVRCF: Overrun/Underrun flag clear Writing 1 to this bit clears the OVR flag in the FMPI2C_ISR register. Bit 9 ARLOCF: Arbitration Lost flag clear Writing 1 to this bit clears the ARLO flag in the FMPI2C_ISR register. Bit 8 BERRCF: Bus error flag clear Writing 1 to this bit clears the BERRF flag in the FMPI2C_ISR register.
Page 845: Receive Data Register (Fmpi2C_Rxdr)
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 26.7.10 Receive data register (FMPI2C_RXDR) Address offset: 0x24 Reset value: 0x0000 0000 Access: No wait states Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 846: Fmpi2C Register Map
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 26.7.12 FMPI2C register map The table below provides the FMPI2C register map and reset values. Table 152. FMPI2C register map and reset values Register Offset name FMPI2C_CR1 DNF[3:0] Reset value FMPI2C_CR2 NBYTES[7:0] SADD[9:0] Reset value FMPI2C_OAR1 OA1[9:0]...
Page 847 RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Table 152. FMPI2C register map and reset values (continued) Register Offset name FMPI2C_TXDR TXDATA[7:0] 0x28 Reset value Refer to Section 2.2.2 on page 58 for the register boundary addresses. RM0430 Rev 8 847/1324...
Page 848: Inter-Integrated Circuit (I 2 C) Interface
Inter-integrated circuit (I C) interface RM0430 Inter-integrated circuit (I C) interface 27.1 C introduction C (inter-integrated circuit) bus Interface serves as an interface between the microcontroller and the serial I C bus. It provides multimaster capability, and controls all I C bus-specific sequencing, protocol, arbitration and timing.
Page 849: I 2 C Main Features
RM0430 Inter-integrated circuit (I C) interface 27.2 C main features • Parallel-bus/I C protocol converter • Multimaster capability: the same interface can act as Master or Slave • C Master features: – Clock generation – Start and Stop generation • C Slave features: –...
Page 850: C Functional Description
Inter-integrated circuit (I C) interface RM0430 Note: Some of the above features may not be available in certain products. The user should refer to the product data sheet, to identify the specific features supported by the I C interface implementation. 27.3 C functional description In addition to receiving and transmitting data, this interface converts it from serial to parallel...
Page 851: I2C Slave Mode
RM0430 Inter-integrated circuit (I C) interface The block diagram of the I C interface is shown in Figure 286. Figure 286. I C block diagram 1. SMBA is an optional signal in SMBus mode. This signal is not applicable if SMBus is disabled. 27.3.2 C slave mode By default the I...
Page 852 Inter-integrated circuit (I C) interface RM0430 Note: In 10-bit addressing mode, the comparison includes the header sequence (11110xx0), where xx denotes the two most significant bits of the address. Header or address not matched: the interface ignores it and waits for another Start condition.
Page 853: Figure 287. Transfer Sequence Diagram For Slave Transmitter
RM0430 Inter-integrated circuit (I C) interface Figure 287. Transfer sequence diagram for slave transmitter 1. The EV1 and EV3_1 events stretch SCL low until the end of the corresponding software sequence. 2. The EV3 event stretches SCL low if the software sequence is not completed before the end of the next byte transmission Slave receiver Following the address reception and after clearing ADDR, the slave receives bytes from the...
Page 854: I2C Master Mode
Inter-integrated circuit (I C) interface RM0430 Figure 288. Transfer sequence diagram for slave receiver 1. The EV1 event stretches SCL low until the end of the corresponding software sequence. 2. The EV2 event stretches SCL low if the software sequence is not completed before the end of the next byte reception.
Page 855 RM0430 Inter-integrated circuit (I C) interface SCL master clock generation The CCR bits are used to generate the high and low level of the SCL clock, starting from the generation of the rising and falling edge (respectively). As a slave may stretch the SCL line, the peripheral checks the SCL input from the bus at the end of the time programmed in TRISE bits after rising edge generation.
Page 856 Inter-integrated circuit (I C) interface RM0430 The master can decide to enter Transmitter or Receiver mode depending on the LSB of the slave address sent. • In 7-bit addressing mode, – To enter Transmitter mode, a master sends the slave address with LSB reset. –...
Page 857: Figure 289. Transfer Sequence Diagram For Master Transmitter
RM0430 Inter-integrated circuit (I C) interface Figure 289. Transfer sequence diagram for master transmitter 1. The EV5, EV6, EV9, EV8_1 and EV8_2 events stretch SCL low until the end of the corresponding software sequence. 2. The EV8 event stretches SCL low if the software sequence is not complete before the end of the next byte transmission. RM0430 Rev 8 857/1324...
Page 858 Inter-integrated circuit (I C) interface RM0430 Master receiver Following the address transmission and after clearing ADDR, the I C interface enters Master Receiver mode. In this mode the interface receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence: An acknowledge pulse if the ACK bit is set The RxNE bit is set and an interrupt is generated if the ITEVFEN and ITBUFEN bits are...
Page 859: Figure 290. Transfer Sequence Diagram For Master Receiver
RM0430 Inter-integrated circuit (I C) interface Figure 290. Transfer sequence diagram for master receiver 1. If a single byte is received, it is NA. 2. The EV5, EV6 and EV9 events stretch SCL low until the end of the corresponding software sequence. 3.
Page 860: Error Conditions
Inter-integrated circuit (I C) interface RM0430 For N >2 -byte reception, from N-2 data reception • Wait until BTF = 1 (data N-2 in DR, data N-1 in shift register, SCL stretched low until data N-2 is read) • Set ACK low •...
Page 861: Programmable Noise Filter
RM0430 Inter-integrated circuit (I C) interface Overrun/underrun error (OVR) An overrun error can occur in slave mode when clock stretching is disabled and the I interface is receiving data. The interface has received a byte (RxNE=1) and the data in DR has not been read, before the next byte is received by the interface.
Page 862: Sda/Scl Line Control
Inter-integrated circuit (I C) interface RM0430 Note: For each frequency range, the constraint is given based on the worst case which is the minimum frequency of the range. Greater DNF values can be used if the system can support maximum hold time violation. 27.3.6 SDA/SCL line control •...
Page 863: Table 154. Smbus Vs. I2C
RM0430 Inter-integrated circuit (I C) interface Table 154. SMBus vs. I SMBus Max. speed 100 kHz Max. speed 400 kHz Min. clock speed 10 kHz No minimum clock speed 35 ms clock low timeout No timeout Logic levels are fixed Logic levels are V dependent Different address types (reserved, dynamic etc.)
Page 864 Inter-integrated circuit (I C) interface RM0430 SMBus alert mode SMBus Alert is an optional signal with an interrupt line for devices that want to trade their ability to master for a pin. SMBA is a wired-AND signal just as the SCL and SDA signals are. SMBA is used in conjunction with the SMBus General Call Address.
Page 865: Dma Requests
RM0430 Inter-integrated circuit (I C) interface 27.3.8 DMA requests DMA requests (when enabled) are generated only for data transfer. DMA requests are generated by Data Register becoming empty in transmission and Data Register becoming full in reception. The DMA must be initialized and enabled before the I2C data transfer. The DMAEN bit must be set in the I2C_CR2 register before the ADDR event.
Page 866: Packet Error Checking
Inter-integrated circuit (I C) interface RM0430 Reception using DMA DMA mode can be enabled for reception by setting the DMAEN bit in the I2C_CR2 register. Data will be loaded from the I2C_DR register to a Memory area configured using the DMA peripheral (refer to the DMA specification) whenever a data byte is received.
Page 867: I 2 C Interrupts
RM0430 Inter-integrated circuit (I C) interface be set before the ACK of the CRC reception in slave mode. It must be set when the ACK is set low in master mode. • A PECERR error flag/interrupt is also available in the I2C_SR1 register. •...
Page 868: Figure 291. I2C Interrupt Mapping Diagram
Inter-integrated circuit (I C) interface RM0430 Figure 291. I C interrupt mapping diagram ITEVFEN ADDR ADD10 STOPF it_event ITBUFEN RxNE ITERREN BERR ARLO it_error PECERR TIMEOUT SMBALERT 868/1324 RM0430 Rev 8...
Page 869: I 2 C Debug Mode
RM0430 Inter-integrated circuit (I C) interface 27.5 C debug mode ® When the microcontroller enters the debug mode (Cortex -M4 with FPU core halted), the SMBUS timeout either continues to work normally or stops, depending on the DBG_I2Cx_SMBUS_TIMEOUT configuration bits in the DBG module. For more details, refer to Section 34.16.2: Debug support for timers, watchdog, bxCAN and I2C.
Page 870 Inter-integrated circuit (I C) interface RM0430 Bit 11 POS: Acknowledge/PEC Position (for data reception) This bit is set and cleared by software and cleared by hardware when PE=0. 0: ACK bit controls the (N)ACK of the current byte being received in the shift register. The PEC bit indicates that current byte in shift register is a PEC.
Page 871: I 2 C Control Register 2 (I2C_Cr2)
RM0430 Inter-integrated circuit (I C) interface Bit 2 Reserved, must be kept at reset value Bit 1 SMBUS: SMBus mode 0: I C mode 1: SMBus mode Bit 0 PE: Peripheral enable 0: Peripheral disable 1: Peripheral enable Note: If this bit is reset while a communication is on going, the peripheral is disabled at the end of the current communication, when back to IDLE state.
Page 872 Inter-integrated circuit (I C) interface RM0430 ITERREN: Error interrupt enable 0: Error interrupt disabled 1: Error interrupt enabled This interrupt is generated when: – BERR = 1 – ARLO = 1 – AF = 1 – OVR = 1 – PECERR = 1 –...
Page 873: I 2 C Own Address Register 1 (I2C_Oar1)
RM0430 Inter-integrated circuit (I C) interface 27.6.3 C Own address register 1 (I2C_OAR1) Address offset: 0x08 Reset value: 0x0000 Res. Res. Res. Res. Res. ADD[9:8] ADD[7:1] ADD0 MODE Bit 15 ADDMODE Addressing mode (slave mode) 0: 7-bit slave address (10-bit address not acknowledged) 1: 10-bit slave address (7-bit address not acknowledged) Bit 14 Should always be kept at 1 by software.
Page 874: C Data Register (I2C_Dr)
Inter-integrated circuit (I C) interface RM0430 27.6.5 C Data register (I2C_DR) Address offset: 0x10 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. DR[7:0] Bits 15:8 Reserved, must be kept at reset value Bits 7:0 DR[7:0] 8-bit data register Byte received or to be transmitted to the bus.
Page 875 RM0430 Inter-integrated circuit (I C) interface Bit 15 SMBALERT: SMBus alert In SMBus host mode: 0: no SMBALERT 1: SMBALERT event occurred on pin In SMBus slave mode: 0: no SMBALERT response address header 1: SMBALERT response address header to SMBALERT LOW received –...
Page 876 Inter-integrated circuit (I C) interface RM0430 Bit 9 ARLO: Arbitration lost (master mode) 0: No Arbitration Lost detected 1: Arbitration Lost detected Set by hardware when the interface loses the arbitration of the bus to another master – Cleared by software writing 0, or by hardware when PE=0. After an ARLO event the interface switches back automatically to Slave mode (MSL=0).
Page 877 RM0430 Inter-integrated circuit (I C) interface Bit 3 ADD10: 10-bit header sent (Master mode) 0: No ADD10 event occurred. 1: Master has sent first address byte (header). – Set by hardware when the master has sent the first byte in 10-bit address mode. –...
Page 878: I 2 C Status Register 2 (I2C_Sr2)
Inter-integrated circuit (I C) interface RM0430 27.6.7 C Status register 2 (I2C_SR2) Address offset: 0x18 Reset value: 0x0000 Note: Reading I2C_SR2 after reading I2C_SR1 clears the ADDR flag, even if the ADDR flag was set after reading I2C_SR1. Consequently, I2C_SR2 must be read only when ADDR is found set in I2C_SR1 or when the STOPF bit is cleared.
Page 879: I 2 C Clock Control Register (I2C_Ccr)
RM0430 Inter-integrated circuit (I C) interface Bit 2 TRA: Transmitter/receiver 0: Data bytes received 1: Data bytes transmitted This bit is set depending on the R/W bit of the address byte, at the end of total address phase. It is also cleared by hardware after detection of Stop condition (STOPF=1), repeated Start condition, loss of bus arbitration (ARLO=1), or when PE=0.
Page 880: C Trise Register (I2C_Trise)
Inter-integrated circuit (I C) interface RM0430 Bit 14 DUTY: Fm mode duty cycle 0: Fm mode t high 1: Fm mode t = 16/9 (see CCR) high Bits 13:12 Reserved, must be kept at reset value Bits 11:0 CCR[11:0]: Clock control register in Fm/Sm mode (Master mode) Controls the SCL clock in master mode.
Page 881: I 2 C Fltr Register (I2C_Fltr)
RM0430 Inter-integrated circuit (I C) interface 27.6.10 C FLTR register (I2C_FLTR) Address offset: 0x24 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ANOFF DNF[3:0] Bits 15:5 Reserved, must be kept at reset value Bit 4 ANOFF: Analog noise filter OFF 0: Analog noise filter enable 1: Analog noise filter disable Note: ANOFF must be configured only when the I2C is disabled (PE = 0).
Page 882: I2C Register Map
Inter-integrated circuit (I C) interface RM0430 27.6.11 C register map The table below provides the I C register map and reset values. Table 156. I C register map and reset values Offset Register I2C_CR1 0x00 Reset value I2C_CR2 FREQ[5:0] 0x04 Reset value ADD[ I2C_OAR1...
Page 883: Universal Synchronous Receiver Transmitter (Usart) /Universal Asynchronous Receiver Transmitter (Uart)
RM0430 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmitter (UART) 28.1 USART introduction The universal synchronous asynchronous receiver transmitter (USART) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format.
Page 884: Usart Main Features
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- 28.2 USART main features • Full duplex, asynchronous communications • NRZ standard format (Mark/Space) • Configurable oversampling method by 16 or by 8 to give flexibility between speed and clock tolerance •...
Page 885: Usart Implementation
RM0430 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver – Receive data register full – Idle line received – Overrun error – Framing error – Noise error – Parity error • Multiprocessor communication - enter into mute mode if address match does not occur •...
Page 886 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- RX: Receive Data Input is the serial data input. Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. TX: Transmit Data Output. When the transmitter is disabled, the output pin returns to its I/O port configuration.
Page 887: Figure 292. Usart Block Diagram
RM0430 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Figure 292. USART block diagram PWDATA PRDATA Write Read (Data register) DR (CPU or DMA) (CPU or DMA) Receive data register (RDR) Transmit data register (TDR) IrDA SW_RX Receive Shift Register Transmit Shift Register ENDEC block...
Page 888: Usart Character Description
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- 28.4.1 USART character description Word length may be selected as being either 8 or 9 bits by programming the M bit in the USART_CR1 register (see Figure 293). The TX pin is in low state during the start bit. It is in high state during the stop bit. An Idle character is interpreted as an entire frame of “1”s followed by the start bit of the next frame that contains data (The number of “1”...
Page 889: Transmitter
RM0430 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver 28.4.2 Transmitter The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the transmit enable bit (TE) is set, the data in the transmit shift register is output on the TX pin and the corresponding clock pulses are output on the SCLK pin.
Page 890: Figure 294. Configurable Stop Bits
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Figure 294. Configurable stop bits 8-bit Word length (M bit is reset) Possible Next data frame parity Data frame Next Start start Stop Bit2 Bit0 Bit1 Bit3 Bit4 Bit5 Bit6 Bit7 CLOCK **** ** LBCL bit controls last data clock pulse...
Page 891: Figure 295. Tc/Txe Behavior When Transmitting
RM0430 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver When a transmission is taking place, a write instruction to the USART_DR register stores the data in the TDR register and which is copied in the shift register at the end of the current transmission.
Page 892: Receiver
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- 28.4.3 Receiver The USART can receive data words of either 8 or 9 bits depending on the M bit in the USART_CR1 register. Start bit detection The start bit detection sequence is the same when oversampling by 16 or by 8. In the USART, the start bit is detected when a specific sequence of samples is recognized.
Page 893 RM0430 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Procedure: Enable the USART by writing the UE bit in USART_CR1 register to 1. Program the M bit in USART_CR1 to define the word length. Program the number of stop bits in USART_CR2. Select DMA enable (DMAR) in USART_CR3 if multibuffer communication is to take place.
Page 894 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- The RXNE flag is set after every byte received. An overrun error occurs if RXNE flag is set when the next data is received or the previous DMA request has not been serviced. When an overrun error occurs: •...
Page 895: Table 158. Noise Detection From Sampled Data
RM0430 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver receiver tolerance to clock deviation). In this case the NF bit will never be set. When noise is detected in a frame: • The NF bit is set at the rising edge of the RXNE bit. •...
Page 896 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Table 158. Noise detection from sampled data (continued) Sampled value NE status Received bit value Framing error A framing error is detected when: The stop bit is not recognized on reception at the expected time, following either a de- synchronization or excessive noise.
Page 897: Fractional Baud Rate Generation
RM0430 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver be set. The second stop bit is not checked for framing error. The RXNE flag will be set at the end of the first stop bit. 28.4.4 Fractional baud rate generation The baud rate for the receiver and transmitter (Rx and Tx) are both set to the same value as programmed in the Mantissa and Fraction values of USARTDIV.
Page 898 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- This leads to: DIV_Fraction = 16*0d0.99 = 0d15.84 The nearest real number is 0d16 = 0x10 => overflow of DIV_frac[3:0] => carry must be added up to the mantissa DIV_Mantissa = mantissa (0d50.990 + carry) = 0d51 = 0x33 Then, USART_BRR = 0x330 hence USARTDIV = 0d51.000 How to derive USARTDIV from USART_BRR register values when OVER8=1 Example 1:...
Page 899: Table 159. Error Calculation For Programmed Baud Rates At F
RM0430 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Table 159. Error calculation for programmed baud rates at f = 8 MHz or f = 12 MHz, PCLK PCLK oversampling by 16 Oversampling by 16 (OVER8=0) Baud rate = 8 MHz = 12 MHz PCLK PCLK...
Page 900 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Table 160. Error calculation for programmed baud rates at f = 8 MHz or f = 12 MHz, PCLK PCLK oversampling by 8 (continued) Oversampling by 8 (OVER8 = 1) Baud rate = 8 MHz = 12 MHz PCLK...
Page 901 RM0430 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Table 162. Error calculation for programmed baud rates at f = 16 MHz or f = 24 MHz, PCLK PCLK oversampling by 8 Oversampling by 8 (OVER8=1) Baud rate = 16 MHz = 24 MHz PCLK PCLK...
Page 902 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Table 163. Error calculation for programmed baud rates at f = 8 MHz or f = 16 MHz, PCLK PCLK oversampling by 16 (continued) Oversampling by 16 (OVER8=0) Baud rate = 8 MHz = 16 MHz PCLK PCLK...
Page 903 RM0430 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Table 165. Error calculation for programmed baud rates at f = 30 MHz or f = 60 MHz, PCLK PCLK (1)(2) oversampling by 16 Oversampling by 16 (OVER8=0) Baud rate = 30 MHz = 60 MHz PCLK PCLK...
Page 904 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Table 166. Error calculation for programmed baud rates at f = 30 MHz or f = 60 MHz, PCLK PCLK (1) (2) oversampling by 8 (continued) Oversampling by 8 (OVER8=1) Baud rate = 30 MHz =60 MHz PCLK...
Page 905 RM0430 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Table 167. Error calculation for programmed baud rates at f = 42 MHz or f = 84 Hz, PCLK PCLK (1)(2) oversampling by 16 (continued) Oversampling by 16 (OVER8=0) Baud rate = 42 MHz = 84 MHz PCLK...
Page 906: Usart Receiver Tolerance To Clock Deviation
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Table 168. Error calculation for programmed baud rates at f = 42 MHz or f = 84 MHz, PCLK PCLK (1)(2) oversampling by 8 (continued) Oversampling by 8 (OVER8=1) Baud rate = 42 MHz = 84 MHz PCLK...
Page 907: Multiprocessor Communication
RM0430 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Table 170. USART receiver tolerance when DIV_Fraction is different from 0 OVER8 bit = 0 OVER8 bit = 1 M bit ONEBIT=0 ONEBIT=1 ONEBIT=0 ONEBIT=1 3.33% 3.88% 3.03% 3.53% 1.82% 2.73% Note: The figures specified in Table 169...
Page 908: Figure 299. Mute Mode Using Idle Line Detection
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Figure 299. Mute mode using Idle line detection Address mark detection (WAKE=1) In this mode, bytes are recognized as addresses if their MSB is a ‘1 else they are considered as data. In an address byte, the address of the targeted receiver is put on the 4 LSB.
Page 909: Parity Control
RM0430 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver 28.4.7 Parity control Parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the PCE bit in the USART_CR1 register. Depending on the frame length defined by the M bit, the possible USART frame formats are as listed in Table 171.
Page 910: Lin (Local Interconnection Network) Mode
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- 28.4.8 LIN (local interconnection network) mode The LIN mode is selected by setting the LINEN bit in the USART_CR2 register. In LIN mode, the following bits must be kept cleared: • STOP[1:0] and CLKEN in the USART_CR2 register •...
Page 911: Figure 301. Break Detection In Lin Mode (11-Bit Break Length - Lbdl Bit Is Set)
RM0430 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Figure 301. Break detection in LIN mode (11-bit break length - LBDL bit is set) RM0430 Rev 8 911/1324...
Page 912: Usart Synchronous Mode
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Figure 302. Break detection in LIN mode vs. Framing error detection 28.4.9 USART synchronous mode The synchronous mode is selected by writing the CLKEN bit in the USART_CR2 register to 1. In synchronous mode, the following bits must be kept cleared: •...
Page 913: Figure 303. Usart Example Of Synchronous Transmission
RM0430 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver has been written). This means that it is not possible to receive a synchronous data without transmitting data. The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly.
Page 914: Single-Wire Half-Duplex Communication
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Figure 305. USART data clock timing diagram (M=1) Figure 306. RX data setup/hold time Note: The function of SCLK is different in Smartcard mode. Refer to the Smartcard mode chapter for more details. 28.4.10 Single-wire half-duplex communication The single-wire half-duplex mode is selected by setting the HDSEL bit in the USART_CR3...
Page 915: Smartcard
RM0430 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver As soon as HDSEL is written to 1: • the TX and RX lines are internally connected • the RX pin is no longer used • the TX pin is always released when no data is transmitted. Thus, it acts as a standard I/O in idle or in reception.
Page 916: Figure 308. Parity Error Detection Using The 1.5 Stop Bits
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- shifting on the next baud clock edge. In Smartcard mode this transmission is further delayed by a guaranteed 1/2 baud clock. • If a parity error is detected during reception of a frame programmed with a 0.5 or 1.5 stop bit period, the transmit line is pulled low for a baud clock period after the completion of the receive frame.
Page 917: Irda Sir Endec Block
RM0430 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver prescaler register USART_GTPR. SCLK frequency can be programmed from f /2 to /62, where f is the peripheral input clock. 28.4.12 IrDA SIR ENDEC block The IrDA mode is selected by setting the IREN bit in the USART_CR3 register. In IrDA mode, the following bits must be kept cleared: •...
Page 918: Figure 309. Irda Sir Endec- Block Diagram
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- IrDA low-power mode Transmitter: In low-power mode the pulse width is not maintained at 3/16 of the bit period. Instead, the width of the pulse is 3 times the low-power baud rate that can be a minimum of 1.42 MHz. Generally this value is 1.8432 MHz (1.42 MHz <...
Page 919: Continuous Communication Using Dma
RM0430 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver 28.4.13 Continuous communication using DMA The USART is capable of continuous communication using the DMA. The DMA requests for Rx buffer and Tx buffer are generated independently. Transmission using DMA DMA mode can be enabled for transmission by setting DMAT bit in the USART_CR3 register.
Page 920: Figure 311. Transmission Using Dma
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Figure 311. Transmission using DMA Reception using DMA DMA mode can be enabled for reception by setting the DMAR bit in USART_CR3 register. Data is loaded from the USART_DR register to a SRAM area configured using the DMA peripheral (refer to the DMA specification) whenever a data byte is received.
Page 921: Hardware Flow Control
RM0430 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Figure 312. Reception using DMA Error flagging and interrupt generation in multibuffer communication In case of multibuffer communication if any error occurs during the transaction the error flag will be asserted after the current byte. An interrupt will be generated if the interrupt enable flag is set.
Page 922: Figure 314. Rts Flow Control
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- RTS flow control If the RTS flow control is enabled (RTSE=1), then nRTS is asserted (tied low) as long as the USART receiver is ready to receive a new data. When the receive register is full, nRTS is deasserted, indicating that the transmission is expected to stop at the end of the current frame.
Page 923: Usart Interrupts
RM0430 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Note: Special behavior of break frames: when the CTS flow is enabled, the transmitter does not check the nCTS input state to send a break. 28.5 USART interrupts Table 172. USART interrupt requests Interrupt event Event flag Enable control bit...
Page 924: Usart Registers
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Figure 316. USART interrupt mapping diagram 28.6 USART registers Refer to for a list of abbreviations used in register descriptions. Section 1.2 on page 52 The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits). 28.6.1 Status register (USART_SR) Address offset: 0x00...
Page 925 RM0430 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Bits 31:10 Reserved, must be kept at reset value Bit 9 CTS: CTS flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software (by writing it to 0).
Page 926 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Bit 3 ORE: Overrun error This bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the RDR register while RXNE=1. An interrupt is generated if RXNEIE=1 in the USART_CR1 register.
Page 927: Data Register (Usart_Dr)
RM0430 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver 28.6.2 Data register (USART_DR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 928: Control Register 1 (Usart_Cr1)
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- 28.6.4 Control register 1 (USART_CR1) Address offset: 0x0C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OVER8 Res. WAKE PEIE TXEIE TCIE...
Page 929 RM0430 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Bit 8 PEIE: PE interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An USART interrupt is generated whenever PE=1 in the USART_SR register Bit 7 TXEIE: TXE interrupt enable This bit is set and cleared by software.
Page 930: Control Register 2 (Usart_Cr2)
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- 28.6.5 Control register 2 (USART_CR2) Address offset: 0x10 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LINEN STOP[1:0] CLKEN CPOL CPHA...
Page 931: Control Register 3 (Usart_Cr3)
RM0430 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Bit 8 LBCL: Last bit clock pulse This bit allows the user to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. 0: The clock pulse of the last data bit is not output to the SCLK pin 1: The clock pulse of the last data bit is output to the SCLK pin Note: 1: The last bit is the 8th or 9th data bit transmitted depending on the 8 or 9 bit format selected...
Page 932 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Bit 9 CTSE: CTS enable 0: CTS hardware flow control disabled 1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while a data is being transmitted, then the transmission is completed before stopping.
Page 933: Guard Time And Prescaler Register (Usart_Gtpr)
RM0430 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Bit 0 EIE: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USART_SR register) in case of Multi Buffer Communication (DMAR=1 in the USART_CR3 register).
Page 934: Usart Register Map
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- 28.6.8 USART register map The table below gives the USART register map and reset values. Table 173. USART register map and reset values Offset Register USART_SR 0x00 Reset value USART_DR DR[8:0] 0x04 Reset value DIV_Fraction...
Page 935: Serial Peripheral Interface/ Inter-Ic Sound (Spi/I2S)
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) Serial peripheral interface/ inter-IC sound (SPI/I2S) 29.1 Introduction The SPI/I²S interface can be used to communicate with external devices using the SPI protocol or the I S audio protocol. SPI or I S mode is selectable by software. SPI mode is selected by default after a device reset.
Page 936: Spi Main Features
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 29.1.1 SPI main features • Master or slave operation • Full-duplex synchronous transfers on three lines • Half-duplex synchronous transfer on two lines (with bidirectional data line) • Simplex synchronous transfers on two lines (with unidirectional data line) •...
Page 937: Spi Extended Features
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) 29.1.2 SPI extended features • SPI TI mode support 29.1.3 I2S features • Full-duplex communication • Half-duplex communication (only transmitter or receiver) • Master or slave operations • 8-bit programmable linear prescaler to reach accurate audio sample frequencies (from 8 kHz to 192 kHz) •...
Page 938: Spi Functional Description
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 29.3 SPI functional description 29.3.1 General description The SPI allows synchronous, serial communication between the MCU and external devices. Application software can manage the communication by polling the status flag or using dedicated SPI interrupt. The main elements of SPI and their interactions are shown in the following block diagram Figure 317.
Page 939: Communications Between One Master And One Slave
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) 29.3.2 Communications between one master and one slave The SPI allows the MCU to communicate using different configurations, depending on the device targeted and the application requirements. These configurations use 2 or 3 wires (with software NSS management) or 3 or 4 wires (with hardware NSS management).
Page 940: Figure 319. Half-Duplex Single Master/ Single Slave Application
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 Figure 319. Half-duplex single master/ single slave application 1. The NSS pins can be used to provide a hardware control flow between master and slave. Optionally, the pins can be left unused by the peripheral. Then the flow has to be handled internally for both master and slave.
Page 941: Figure 320. Simplex Single Master/Single Slave Application
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) Figure 320. Simplex single master/single slave application (master in transmit-only/ slave in receive-only mode) 1. The NSS pins can be used to provide a hardware control flow between master and slave. Optionally, the pins can be left unused by the peripheral.
Page 942: Standard Multi-Slave Communication
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 29.3.3 Standard multi-slave communication In a configuration with two or more independent slaves, the master uses GPIO pins to manage the chip select lines for each slave (see Figure 321.). The master must select one of the slaves individually by pulling low the GPIO connected to the slave NSS input.
Page 943: Multi-Master Communication
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) 29.3.4 Multi-master communication Unless SPI bus is not designed for a multi-master capability primarily, the user can use build in feature which detects a potential conflict between two nodes trying to master the bus at the same time.
Page 944: Figure 323. Hardware/Software Slave Select Management
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 – NSS output enable (SSM=0,SSOE = 1): this configuration is only used when the MCU is set as master. The NSS pin is managed by the hardware. The NSS signal is driven low as soon as the SPI is enabled in master mode (SPE=1), and is kept low until the SPI is disabled (SPE =0).
Page 945: Communication Formats
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) 29.3.6 Communication formats During SPI communication, receive and transmit operations are performed simultaneously. The serial clock (SCK) synchronizes the shifting and sampling of the information on the data lines. The communication format depends on the clock phase, the clock polarity and the data frame format.
Page 946: Figure 324. Data Clock Timing Diagram
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 Figure 324. Data clock timing diagram Note: The order of data bits depends on LSBFIRST bit setting. Data frame format The SPI shift register can be set up to shift out MSB-first or LSB-first, depending on the value of the LSBFIRST bit.
Page 947: Spi Configuration
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) 29.3.7 SPI configuration The configuration procedure is almost the same for master and slave. For specific mode setups, follow the dedicated chapters. When a standard communication is to be initialized, perform these steps: Write proper GPIO registers: Configure GPIO for MOSI, MISO and SCK pins.
Page 948: Data Transmission And Reception Procedures
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 29.3.9 Data transmission and reception procedures Rx and Tx buffers In reception, data are received and then stored into an internal Rx buffer while in transmission, data are first stored into an internal Tx buffer before being transmitted. A read access to the SPI_DR register returns the Rx buffered value whereas a write access to the SPI_DR stores the written data into the Tx buffer.
Page 949: Figure 325. Txe/Rxne/Bsy Behavior In Master / Full-Duplex Mode (Bidimode=0, Rxonly=0) In The Case Of Continuous Transfers
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) underflow error signal for slave operating in SPI mode, and that data from the slave are always transacted and processed by the master even if the slave cannot not prepare them correctly in time. It is preferable for the slave to use DMA, especially when data frames are shorter and bus rate is high.
Page 950: Procedure For Disabling The Spi
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 Figure 326. TXE/RXNE/BSY behavior in slave / full-duplex mode (BIDIMODE=0, RXONLY=0) in the case of continuous transfers 29.3.10 Procedure for disabling the SPI When SPI is disabled, it is mandatory to follow the disable procedures described in this paragraph.
Page 951: Communication Using Dma (Direct Memory Addressing)
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) Note: During discontinuous communications, there is a 2 APB clock period delay between the write operation to the SPI_DR register and BSY bit setting. As a consequence it is mandatory to wait first until TXE is set and then until BSY is cleared after writing the last data.
Page 952: Figure 327. Transmission Using Dma
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 To close communication it is mandatory to follow these steps in order: Disable DMA streams for Tx and Rx in the DMA registers, if the streams are used. Disable the SPI by following the SPI disable procedure. Disable DMA Tx and Rx buffers by clearing the TXDMAEN and RXDMAEN bits in the SPI_CR2 register, if DMA Tx and/or DMA Rx are used.
Page 953: Spi Status Flags
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) Figure 328. Reception using DMA 29.3.12 SPI status flags Three status flags are provided for the application to completely monitor the state of the SPI bus. Tx buffer empty flag (TXE) When it is set, the TXE flag indicates that the Tx buffer is empty and that the next data to be transmitted can be loaded into the buffer.
Page 954: Spi Error Flags
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 The BSY flag is cleared under any one of the following conditions: • When the SPI is correctly disabled • When a fault is detected in Master mode (MODF bit set to 1) •...
Page 955: Spi Special Features
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) CRC error (CRCERR) This flag is used to verify the validity of the value received when the CRCEN bit in the SPIx_CR1 register is set. The CRCERR flag in the SPIx_SR register is set if the value received in the shift register does not match the receiver SPIx_RXCRC value.
Page 956: Crc Calculation
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 Note: To detect TI frame errors in slave transmitter only mode by using the Error interrupt (ERRIE=1), the SPI must be configured in 2-line unidirectional mode by setting BIDIMODE and BIDIOE to 1 in the SPI_CR1 register. When BIDIMODE is set to 0, OVR is set to 1 because the data register is never read and error interrupts are always generated, while when BIDIMODE is set to 1, data are not received and OVR is never set.
Page 957 RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) The received CRC is stored in the Rx buffer like any other data frame. A CRC-format transaction takes one more data frame to communicate at the end of data sequence. When the last CRC data is received, an automatic check is performed comparing the received value and the value in the SPIx_RXCRC register.
Page 958: Spi Interrupts
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 29.5 SPI interrupts During SPI communication an interrupts can be generated by the following events: • Transmit Tx buffer ready to be loaded • Data received in Rx buffer • Master mode fault •...
Page 959: I 2 S Functional Description
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) 29.6 S functional description 29.6.1 S general description The block diagram of the I S is shown in Figure 330. Figure 330. I S block diagram 1. I2S2ext_SD and I2S3ext_SD are the extended SD pins that control the I2S full-duplex mode. 2.
Page 960: I2S Full-Duplex
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 The SPI can function as an audio I S interface when the I S capability is enabled (by setting the I2SMOD bit in the SPIx_I2SCFGR register). This interface mainly uses the same pins, flags and interrupts as the SPI.
Page 961: Supported Audio Protocols
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) I2Sx can operate in master mode. As a result: • Only I2Sx can output SCK and WS in half-duplex mode • Only I2Sx can deliver SCK and WS to I2S2_ext and I2S3_ext in full-duplex mode. The extended I2Ss (I2Sx_ext) can be used only in full-duplex mode.
Page 962: Figure 332. I 2 S Philips Protocol Waveforms (16/32-Bit Full Accuracy, Cpol = 0)
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 Figure 332. I S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0) Data are latched on the falling edge of CK (for the transmitter) and are read on the rising edge (for the receiver). The WS signal is also latched on the falling edge of CK. Figure 333.
Page 963: Figure 335. Receiving 0X8Eaa33
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) Figure 335. Receiving 0x8EAA33 Figure 336. I S Philips standard (16-bit extended to 32-bit packet frame with CPOL = 0) When 16-bit data frame extended to 32-bit channel frame is selected during the I configuration phase, only one access to the SPIx_DR register is required.
Page 964: Figure 338. Msb Justified 16-Bit Or 32-Bit Full-Accuracy Length With Cpol = 0
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 Figure 338. MSB Justified 16-bit or 32-bit full-accuracy length with CPOL = 0 Data are latched on the falling edge of CK (for transmitter) and are read on the rising edge (for the receiver). Figure 339.
Page 965: Figure 341. Lsb Justified 16-Bit Or 32-Bit Full-Accuracy With Cpol = 0
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) Figure 341. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0 Figure 342. LSB justified 24-bit frame length with CPOL = 0 • In transmission mode: If data 0x3478AE have to be transmitted, two write operations to the SPIx_DR register are required by software or by DMA.
Page 966: Figure 344. Operations Required To Receive 0X3478Ae
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 Figure 344. Operations required to receive 0x3478AE Figure 345. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 When 16-bit data frame extended to 32-bit channel frame is selected during the I configuration phase, Only one access to the SPIx_DR register is required.
Page 967: Clock Generator
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) PCM standard For the PCM standard, there is no need to use channel-side information. The two PCM modes (short and long frame) are available and configurable using the PCMSYNC bit in SPIx_I2SCFGR register. Figure 347.
Page 968: Figure 349. Audio Sampling Frequency Definition
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 Figure 349. Audio sampling frequency definition When the master mode is configured, a specific action needs to be taken to properly program the linear divider in order to communicate with the desired audio frequency. Figure 350 presents the communication clock architecture.
Page 969: Table 176. Audio-Frequency Precision Using Standard 8 Mhz Hse
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) Table 176. Audio-frequency precision using standard 8 MHz HSE SYSCLK Data Target f I2SDIV I2SODD MCLK Real f (KHz) Error length (Hz) (MHz) 96000 93750 2.3438% 96000 93750 2.3438% 48000 48387.0968 0.8065% 48000 46875 2.3438% 44100...
Page 970: I 2 S Master Mode
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 29.6.5 S master mode The I S can be configured as follows: • In master mode for transmission or reception (half-duplex mode using I2Sx) • In master mode transmission and reception (full-duplex mode using I2Sx and I2Sx_ext).
Page 971 RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) To ensure a continuous audio data transmission, it is mandatory to write the SPIx_DR register with the next data to transmit before the end of the current transmission. To switch off the I S, by clearing I2SE, it is mandatory to wait for TXE = 1 and BSY = 0.
Page 972: I 2 S Slave Mode
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 29.6.6 S slave mode The I S can be configured as follows: • In slave mode for transmission or reception (half-duplex mode using I2Sx) • In slave mode transmission and reception (full-duplex mode using I2Sx and I2Sx_ext). The operating mode is following mainly the same rules as described for the I S master configuration.
Page 973: I 2 S Status Flags
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) To secure a continuous audio data transmission, it is mandatory to write the SPIx_DR register with the next data to transmit before the end of the current transmission. An underrun flag is set and an interrupt may be generated if the data are not written into the SPIx_DR register before the first clock edge of the next data communication.
Page 974: I 2 S Error Flags
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 The BSY flag is cleared: • When a transfer completes (except in master transmit mode, in which the communication is supposed to be continuous) • When the I S is disabled When communication is continuous: •...
Page 975: I 2 S Interrupts
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) Overrun flag (OVR) This flag is set when data are received and the previous data have not yet been read from the SPIx_DR register. As a result, the incoming data are lost. An interrupt may be generated if the ERRIE bit is set in the SPIx_CR2 register.
Page 976: Spi And I 2 S Registers
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 29.7 SPI and I S registers The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). SPI_DR in addition by can be accessed by 8-bit access. Refer to Section 1.2 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16 bits) or words (32 bits).
Page 977 RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) Bit 11 DFF: Data frame format 0: 8-bit data frame format is selected for transmission/reception 1: 16-bit data frame format is selected for transmission/reception Note: This bit should be written only when SPI is disabled (SPE = ‘0’) for correct operation. It is not used in I S mode.
Page 978: Spi Control Register 2 (Spi_Cr2)
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 Bit 2 MSTR: Master selection 0: Slave configuration 1: Master configuration Note: This bit should not be changed when communication is ongoing. It is not used in I S mode. Bit1 CPOL: Clock polarity 0: CK to 0 when idle 1: CK to 1 when idle Note: This bit should not be changed when communication is ongoing.
Page 979: Spi Status Register (Spi_Sr)
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) Bit 2 SSOE: SS output enable 0: SS output is disabled in master mode and the cell can work in multimaster configuration 1: SS output is enabled in master mode and when the cell is enabled. The cell cannot work in a multimaster environment.
Page 980 Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 Bit 5 MODF: Mode fault 0: No mode fault occurred 1: Mode fault occurred This flag is set by hardware and reset by a software sequence. Refer to Section 29.4 on page 955 for the software sequence.
Page 981: Spi Data Register (Spi_Dr)
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) 29.7.4 SPI data register (SPI_DR) Address offset: 0x0C Reset value: 0x0000 DR[15:0] Bits 15:0 DR[15:0]: Data register Data received or to be transmitted. The data register is split into 2 buffers - one for writing (Transmit Buffer) and another one for reading (Receive buffer).
Page 982: Spi Rx Crc Register (Spi_Rxcrcr) (Not Used In I 2 S Mode)
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 29.7.6 SPI RX CRC register (SPI_RXCRCR) (not used in I S mode) Address offset: 0x14 Reset value: 0x0000 RXCRC[15:0] Bits 15:0 RXCRC[15:0]: Rx CRC register When CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of the subsequently received bytes.
Page 983: Spi_I 2 S Configuration Register (Spi_I2Scfgr)
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) 29.7.8 SPI_I S configuration register (SPI_I2SCFGR) Address offset: 0x1C Reset value: 0x0000 ASTRE PCMSY Res. Res. Res. I2SMOD I2SE I2SCFG Res. I2SSTD CKPOL DATLEN CHLEN Bits 15:13 Reserved, must be kept at reset value. Bit 12 ASTREN: Asynchronous start enable.
Page 984: Spi_I 2 S Prescaler Register (Spi_I2Spr)
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 Bits 5:4 I2SSTD: I2S standard selection 00: I S Philips standard. 01: MSB justified standard (left justified) 10: LSB justified standard (right justified) 11: PCM standard For more details on I S standards, refer to Section 29.6.3 on page 961.
Page 985 RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) Bit 9 MCKOE: Master clock output enable 0: Master clock output is disabled 1: Master clock output is enabled Note: This bit should be configured when the I S is disabled. It is used only when the I S is in master mode.
Page 986: Spi Register Map
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 29.7.10 SPI register map The table provides shows the SPI register map and reset values. Table 178. SPI register map and reset values Offset Register SPI_CR1 [2:0] 0x00 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI_CR2 0x04 Reset value...
Page 987: Serial Audio Interface (Sai)
RM0430 Serial audio interface (SAI) Serial audio interface (SAI) 30.1 Introduction The SAI interface (serial audio interface) offers a wide set of audio protocols due to its flexibility and wide range of configurations. Many stereo or mono audio applications may be targeted.
Page 988: Main Features
Serial audio interface (SAI) RM0430 30.2 Main features • Two independent audio sub-blocks which can be transmitters or receivers with their respective FIFO. • 8-word integrated FIFOs for each audio sub-block. • Synchronous or asynchronous mode between the audio sub-blocks. •...
Page 989: Figure 351. Functional Block Diagram
RM0430 Serial audio interface (SAI) Figure 351. Functional block diagram The SAI is mainly composed of two audio sub-blocks with their own clock generator. Each audio block integrates a 32-bit shift register controlled by their own functional state machine. Data are stored or read from the dedicated FIFO. FIFO may be accessed by the CPU, or by DMA in order to leave the CPU free during the communication.
Page 990: Main Sai Modes
Serial audio interface (SAI) RM0430 30.4 Main SAI modes Each audio sub-block of the SAI can be configured to be master or slave via bit MODE[0] in the SAI_xCR1 register of the selected audio block. In master mode: • The bit clock is generated by the SAI using the clock generator on pin SCK_A or SCK_B (depending which audio block is declared as a master in the SAI).
Page 991: Sai Synchronization Mode
RM0430 Serial audio interface (SAI) 30.5 SAI synchronization mode Internal synchronization An audio block can be declared synchronous with the second audio block. In this case, the bit clock and the frame synchronization signals are shared to reduce the number of external pins used for the communication.
Page 992: Frame Length
Serial audio interface (SAI) RM0430 In AC’97 mode (bit PRTCFG[1:0] = 10 in the SAI_xCR1 register), the frame synchronization shape is forced to be configured to target these protocols. The SAI_xFRCR register value is ignored. Each audio block is independent and so each requires a specific configuration. 30.7.1 Frame length •...
Page 993: Frame Synchronization Active Level Length
RM0430 Serial audio interface (SAI) flow. 30.7.3 Frame synchronization active level length Bit FSALL[6:0] in the SAI_xFRCR register configures the length of the active level of the Frame synchronization signal. The length can be set from 1 to 128 bit clock SCK. The active length may be half of the frame length in I2S, LSB or MSB-justified modes for instance, or one-bit wide for PCM/DSP or TDM mode, or even 16-bit length in AC’97.
Page 994: Slot Configuration
Serial audio interface (SAI) RM0430 1. The frame length should be even. If bit FSDEF in SAI_xFRCR is kept clear, so FS signal is equivalent to a start of frame, and if the number of slots defined in bit NBSLOT[3:0] in SAI_xSLOTR multiplied by the number of bits by slot configured in bit SLOTSZ[1:0] in SAI_xSLOTR is less than the frame size (bit FRL[7:0] in the SAI_xFRCR register), then, •...
Page 995: Figure 355. Slot Size Configuration With Fboff = 0 In Sai_Xslotr
RM0430 Serial audio interface (SAI) Figure 355. Slot size configuration with FBOFF = 0 in SAI_xSLOTR It is possible to choose the position of the first data bit to transfer within the slots, this offset is configured by bit FBOFF[5:0] in the SAI_xSLOTR register. 0 values will be injected in transmitter mode from the beginning of the slot until this offset position is reached.
Page 996: Sai Clock Generator
Serial audio interface (SAI) RM0430 30.9 SAI clock generator Each audio block has its own clock generator to make these two blocks completely independent. There is no difference in terms of functionality between these two clock generators. They are exactly the same. When the audio block is defined as Master, the clock generator generates the communication clock (the bit clock) and the master clock for external decoders.
Page 997: Internal Fifos
RM0430 Serial audio interface (SAI) Table 179. Example of possible audio frequency sampling range Input SAI_CK_x clock Most usual audio frequency MCKDIV[3:0] frequency sampling achievable 192 kHz MCKDIV[3:0] = 0000 96 kHz MCKDIV[3:0] = 0001 192 kHz x 256 48 kHz MCKDIV[3:0] = 0010 16 kHz MCKDIV[3:0] = 0100...
Page 998 Serial audio interface (SAI) RM0430 An interrupt is generated if FREQIE bit is enabled in the SAI_xIM register. This depends on: • FIFO threshold setting (FLTH bits in SAI_CR2) • Communication direction transmitter or receiver (see Section : Interrupt generation in transmitter mode Section : Interrupt generation in reception mode)
Page 999 RM0430 Serial audio interface (SAI) (FLTH[2:0] bits in SAI_xSR is higher or equal to 010b). This Interrupt (FREQ bit in SAI_XSR register) is cleared by hardware when less than a quarter of the FIFO data locations become available (FLTH[2:0] bits in SAI_xSR is less than 010b). •...
Page 1000: Ac'97 Link Controller
Serial audio interface (SAI) RM0430 30.11 AC’97 link controller The SAI is able to work as an AC’97 link controller. In this protocol: • The slot number and the slot size are fixed. • The frame synchronization signal is perfectly defined and has a fixed shape. To select this protocol, set bit PRTCFG[1:0] in the SAI_xCR1 register to 10.

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