ST STM32F301 6 Series Reference Manual page 782

Serial peripheral interface / integrated interchip sound (SPI/I2S)
27.5 SPI functional description
27.5.1 General description
The SPI allows synchronous, serial communication between the MCU and external devices.
Application software can manage the communication by polling the status flag or using
dedicated SPI interrupt. The main elements of SPI and their interactions are shown in the
following block diagram
MOSI
MISO
SCK
NSS
Four I/O pins are dedicated to SPI communication with external devices.
•
MISO: Master In / Slave Out data. In the general case, this pin is used to transmit data
in slave mode and receive data in master mode.
•
MOSI: Master Out / Slave In data. In the general case, this pin is used to transmit data
in master mode and receive data in slave mode.
•
SCK: Serial Clock output pin for SPI masters and input pin for SPI slaves.
•
NSS: Slave select pin. Depending on the SPI and NSS settings, this pin can be used to
either:
–
–
–
See
The SPI bus allows the communication between one master device and one or more slave
devices. The bus consists of at least two wires - one for the clock signal and the other for
synchronous data transfer. Other signals can be added depending on the data exchange
between SPI nodes and their slave select signal management.
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Figure
Figure 301. SPI block diagram
Rx
FIFO
Shift register
Tx
FIFO
Baud rate
generator
select an individual slave device for communication
synchronize the data frame or
detect a conflict between multiple masters
Section 27.5.5: Slave select (NSS) pin management
301.
Address and data bus
Read
RXONLY
CPOL
CPHA
DS[0:3]
Write
BIDIOE
RM0366 Rev 5
CRC controller
CRCEN
CRCNEXT
CRCL
Communication
controller
BR[2:0]
Internal NSS
NSS
logic
for details.
RM0366
MS30117V1