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System window watchdog (WWDG)
22.3.5
Debug mode
When the device enters debug mode (processor halted), the WWDG counter either
continues to work normally or stops, depending on the configuration bit in DBG module. For
more details, refer to .
22.4
WWDG interrupts
The early wake-up interrupt (EWI) can be used if specific safety operations or data logging
must be performed before the reset is generated. To enable the early wake-up interrupt, the
application must:
•
Write EWIF bit of WWDG_SR register to 0, to clear unwanted pending interrupt
•
Write EWI bit of WWDG_CFR register to 1, to enable interrupt
When the down-counter reaches the value 0x40, a watchdog interrupt is generated, and the
corresponding interrupt service routine (ISR) can be used to trigger specific actions (such as
communications or data logging), before resetting the device.
In some applications, the EWI interrupt can be used to manage a software system check
and/or system recovery/graceful degradation, without generating a WWDG reset. In this
case the corresponding ISR must reload the WWDG counter to avoid the WWDG reset,
then trigger the required actions.
The watchdog interrupt is cleared by writing 0 to the EWIF bit in the WWDG_SR register.
Note:
When the watchdog interrupt cannot be served (for example due to a system lock in a
higher priority task), the WWDG reset is eventually generated.
22.5
WWDG registers
Refer to
register descriptions.
The peripheral registers can be accessed by halfwords (16-bit) or words (32-bit).
22.5.1
WWDG control register (WWDG_CR)
Address offset: 0x000
Reset value: 0x0000 007F
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
592/874
Section 1.2: List of abbreviations for registers
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
WDGA
rs
rw
RM0366 Rev 5
for a list of abbreviations used in
21
20
19
18
Res.
Res.
Res.
5
4
3
2
T[6:0]
rw
rw
rw
rw
RM0366
17
16
Res.
Res.
1
0
rw
rw
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