ST STM32F301 6 Series Reference Manual page 276

Analog-to-digital converters (ADC)
Table 43. ADC register map and reset values for each ADC (offset=0x000
Register name
Offset
reset value
ADCx_OFR2
0x64
Reset value 0
ADCx_OFR3
0x68
Reset value 0
ADCx_OFR4
0x6C
Reset value 0
0x70-
Reserved
0x7C
ADCx_JDR1
0x80
Reset value
ADCx_JDR2
0x84
Reset value
ADCx_JDR3
0x88
Reset value
ADCx_JDR4
0x8C
Reset value
0x8C-
Reserved
0x9C
ADCx_AWD2CR
0xA0
Reset value
ADCx_AWD3CR
0xA4
Reset value
0xA8-
Reserved
0xAC
ADCx_DIFSEL
0xB0
Reset value
ADCx_CALFACT
0xB4
Reset value
Table 44. ADC register map and reset values (master and slave ADC
Register name
Offset
reset value
ADCx_CSR
0x00
Reset value
276/874
for master ADC, 0x100 for slave ADC, x=1) (continued)
OFFSET2_
CH[4:0]
0 0 0 0 0
OFFSET3_
CH[4:0]
0 0 0 0 0
OFFSET4_
CH[4:0]
0 0 0 0 0
common registers) offset =0x300, x=1)
0 0 0
Res.
0 0
0 0
0 0
0 0
Res.
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
CALFACT_D[6:0]
0 0 0 0 0 0 0
0 0 0 0 0 0 0
RM0366 Rev 5
OFFSET2[11:0]
0 0 0 0 0 0 0
OFFSET3[11:0]
0 0 0 0 0 0 0
OFFSET4[11:0]
0 0 0 0 0 0 0
JDATA1[15:0]
0 0 0 0 0 0 0 0 0
JDATA2[15:0]
0 0 0 0 0 0 0 0 0
JDATA3[15:0]
0 0 0 0 0 0 0 0 0
JDATA4[15:0]
0 0 0 0 0 0 0 0 0
AWD2CH[18:1]
0 0 0 0 0 0 0 0 0
AWD3CH[18:1]
0 0 0 0 0 0 0 0 0
DIFSEL[18:1]
0 0 0 0 0 0 0 0 0
CALFACT_S[6:0]
0 0
master ADC1
0 0 0 0 0
RM0366
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0 0
0 0 0 0 0