ST STM32F301 6 Series Reference Manual page 443

RM0366
ETR
ETR pin
TIMx_SMCR
For example, to configure the upcounter to count each 2 rising edges on ETR, use the
following procedure:
1. As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.
2. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register
3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR
register
4. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
5. Enable the counter by writing CEN=1 in the TIMx_CR1 register.
The counter counts once each 2 ETR rising edges.
The delay between the rising edge on ETR and the actual clock of the counter is due to the
resynchronization circuit on the ETRP signal. As a consequence, the maximum frequency
which can be correctly captured by the counter is at most ¼ of TIMxCLK frequency. When
the ETRP signal is faster, the user should apply a division of the external signal by a proper
ETPS prescaler setting.
Figure 172. External trigger input block
0
Divider
/1, /2, /4, /8
1
ETP ETPS[1:0]
TIMx_SMCR
or
ETRP
Filter
downcounter
f
DTS
ETF[3:0]
(internal clock)
TIMx_SMCR
RM0366 Rev 5
General-purpose timer (TIM2)
TI2F or
TI1F or
Encoder
mode
TRGI External clock
mode 1
External clock
ETRF
mode 2
CK_INT
Internal clock
mode
ECE SMS[2:0]
TIMx_SMCR
CK_PSC
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