ST STM32F301 6 Series Reference Manual page 685

RM0366
Controller Tx/Rx NBYTES + PEC+ STOP
Controller Tx/Rx NBYTES + PEC +
Timeout detection
The timeout detection is enabled by setting the TIMOUTEN and TEXTEN bits of the
I2C_TIMEOUTR register. The timers must be programmed in such a way that they detect a
timeout before the maximum time given in the SMBus specification.
t
TIMEOUT
To check the t
reload value. Keep the TIDLE bit at 0 to detect the SCL low level timeout.
Then set the TIMOUTEN bit of the I2C_TIMEOUTR register, to enable the timer.
If SCL is tied low for longer than the (TIMEOUTA + 1) x 2048 x
flag of the I2C_ISR register is set.
Refer to
Caution: Changing the TIMEOUTA[11:0] bitfield and the TIDLE bit values is not allowed when the
TIMEOUTEN bit is set.
t
LOW:SEXT
A 12-bit timer associated with the TIMEOUTB[11:0] bitfield allows checking t
I2C peripheral operating as a target, or t
standard only specifies a maximum, the user can choose the same value for both. The timer
is then enabled by setting the TEXTEN bit in the I2C_TIMEOUTR register.
If the SMBus peripheral performs a cumulative SCL stretch for longer than the (TIMEOUTB
+ 1) x 2048 x t
section, the TIMEOUT flag of the I2C_ISR register is set.
Refer to
Caution: Changing the TIMEOUTB[11:0] bitfield value is not allowed when the TEXTEN bit is set.
Bus idle detection
To check the
loaded with the timer reload value. Keep the TIDLE bit at 1 to detect both SCL and SDA high
level timeout. Then set the TIMOUTEN bit of the I2C_TIMEOUTR register to enable the
timer.
If both the SCL and SDA lines remain high for longer than the
(TIMEOUTA + 1) x 4 x t
Refer to
Caution: Changing the TIMEOUTA[11:0] bitfield and the TIDLE bit values is not allowed when the
TIMEOUTEN bit is set.
Table 92. SMBus with PEC configuration
Mode
ReSTART
Target Tx/Rx with PEC
check
parameter, load the 12-bit TIMEOUTA[11:0] bitfield with the timer
TIMEOUT
Table 93.
and check
t
LOW:MEXT
period, and within the timeout interval described in
I2CCLK
Table 94.
period, the TIMEOUTA[11:0] bitfield associated with 12-bit timer must be
t
IDLE
period, the TIMEOUT flag of the I2C_ISR register is set.
I2CCLK
Table 95.
Inter-integrated circuit interface (I2C)
SBC bit RELOAD bit AUTOEND bit PECBYTE bit
X
X
1
when it operates as a controller. As the
LOW:MEXT
RM0366 Rev 5
0 1
0 0
0 X
period, the TIMEOUT
t
I2CCLK
LOW:SEXT
Bus idle detection
1
1
1
for the
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