ST STM32F301 6 Series Reference Manual page 852

Debug support (DBG)
The DWT also provides some means to give some profiling information. For this, some
counters are accessible to give the number of:
•
Clock cycle
•
Folded instructions
•
Load store unit (LSU) operations
•
Sleep cycles
•
CPI (clock per instructions)
•
Interrupt overhead
28.14 ITM (instrumentation trace macrocell)
28.14.1 General description
The ITM is an application-driven trace source that supports printf style debugging to trace
Operating System (OS) and application events, and emits diagnostic system information.
The ITM emits trace information as packets, which can be generated as:
•
Software trace. Software can write directly to the ITM stimulus registers to emit
packets.
• Hardware trace. The DWT generates these packets, and the ITM emits them.
•
Time stamping. Timestamps are emitted relative to packets. The ITM contains a 21-bit
counter to generate the timestamp. The Cortex
Serial Wire Viewer (SWV) output clocks the counter.
The packets emitted by the ITM are output to the TPIU (Trace Port Interface Unit). The
formatter of the TPIU adds some extra packets (refer to TPIU) and then output the complete
packets sequence to the debugger host.
The bit TRCEN of the Debug Exception and Monitor Control Register must be enabled
before programming or using the ITM.
28.14.2 Time stamp packets, synchronization, and overflow packets
Time stamp packets encode time stamp information, generic control, and synchronization. It
uses a 21-bit timestamp counter (with possible prescalers) which is reset at each time
stamp packet emission. This counter can be either clocked by the CPU clock or the SWV
clock.
A synchronization packet consists of 6 bytes equal to 0x80_00_00_00_00_00, emitted to
the TPIU as 00 00 00 00 00 80 (LSB emitted first).
A synchronization packet is a timestamp packet control. It is emitted at each DWT trigger.
For this, the DWT must be configured to trigger the ITM: the bit CYCCNTENA (bit0) of the
DWT Control Register must be set. In addition, the bit2 (SYNCENA) of the ITM Trace
Control Register must be set.
Note: If the SYNENA bit is not set, the DWT generates synchronization triggers to the TPIU, which
sends only TPIU synchronization packets and not ITM synchronization packets.
An overflow packet consists in a special timestamp packet, which indicates that data was
written, but the FIFO was full.
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-M4F clock or the bit clock rate of the
RM0366 Rev 5
RM0366