ST STM32F301 6 Series Reference Manual page 117

RM0366
7.4.9 RTC domain control register (RCC_BDCR)
Address offset: 0x20
Reset value: 0x0000 0018 (reset by RTC domain Reset)
Access: 0
Wait states are inserted in case of successive accesses to this register.
Note: The LSEON, LSEBYP, RTCSEL, and RTCEN bits of the
(RCC_BDCR)
and the DBP bit in the
modified. These bits are only reset after an RTC domain Reset (see
domain reset). Any internal or external reset does not have any effect on these bits.
31 30 29
Res. Res. Res. Res.
15 14 13
RTC
Res. Res. Res.
EN
rw
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 BDRST: RTC domain software reset
Set and cleared by software.
0: Reset not activated
1: Resets the entire RTC domain
Bit 15 RTCEN: RTC clock enable
Set and cleared by software.
0: RTC clock disabled
1: RTC clock enabled
Bits 14:10 Reserved, must be kept at reset value.
Bits 9:8 RTCSEL[1:0]: RTC clock source selection
Set by software to select the clock source for the RTC. Once the RTC clock source has been
selected, it cannot be changed anymore unless the RTC domain is reset. The BDRST bit can
be used to reset them.
00: No clock
01: LSE oscillator clock used as RTC clock
10: LSI oscillator clock used as RTC clock
11: HSE oscillator clock divided by 32 used as RTC clock
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:3 LSEDRV[1:0]: LSE oscillator drive capability
Set and reset by software to modulate the LSE oscillator's drive capability. A reset of the RTC
domain restores the default value.
00: 'Xtal mode' lower driving capability
01: 'Xtal mode' medium high driving capability
10: 'Xtal mode' medium low driving capability
11: 'Xtal mode' higher driving capability (reset value)
Note: The oscillator is in Xtal mode when it is not in bypass mode.
wait state 3, word, half-word, and byte access
≤ ≤
are in the RTC domain. As a result, after Reset, these bits are write-protected
Power control register (PWR_CR)
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. RTCSEL[1:0]
rw
24 23 22
Res. Res. Res. Res.
8 7 6
Res. Res. Res.
rw
RM0366 Rev 5
Reset and clock control (RCC)
RTC domain control register
has to be set before these can be
Section 7.1.3: RTC
21 20 19 18
Res. Res. Res.
5 4 3 2
LSE
LSEDRV[1:0]
BYP
rw rw rw
17 16
Res. BDRST
rw
1 0
LSE
LSEON
RDY
r rw
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