ST STM32F301 6 Series Reference Manual page 684

Inter-integrated circuit interface (I2C)
Bus idle detection
A controller can assume that the bus is free if it detects that the clock and data signals have
been high for
This timing parameter covers the condition where a controller is dynamically added to the
bus, and may not have detected a state transition on the SMBCLK or SMBDAT lines. In this
case, the controller must wait long enough to ensure that a transfer is not currently in
progress. The I2C peripheral supports a hardware bus idle detection.
25.4.12 SMBus initialization
In addition to the I2C initialization for the I²C-bus, the use of the peripheral for the SMBus
communication requires some extra initialization steps.
Received command and data acknowledge control (target mode)
An SMBus receiver must be able to NACK each received command or data. To allow ACK
control in target mode, the target byte control mode must be enabled, by setting the SBC bit
of the I2C_CR1 register. Refer to
Specific addresses (target mode)
The specific SMBus addresses must be enabled if required. Refer to
more details.
The SMBus device default address (0b1100 001) is enabled by setting the SMBDEN bit of
the I2C_CR1 register.
The SMBus host address (0b0001 000) is enabled by setting the SMBHEN bit of the
I2C_CR1 register.
The alert response address (0b0001100) is enabled by setting the ALERTEN bit of the
I2C_CR1 register.
Packet error checking
PEC calculation is enabled by setting the PECEN bit of the I2C_CR1 register. Then the PEC
transfer is managed with the help of the hardware byte counter associated with the
NBYTES[7:0] bitfield of the I2C_CR2 register. The PECEN bit must be configured before
enabling the I2C.
The PEC transfer is managed with the hardware byte counter, so the SBC bit must be set
when interfacing the SMBus in target mode. The PEC is transferred after transferring
NBYTES[7:0] - 1 data bytes, if the PECBYTE bit is set and the RELOAD bit is cleared. If
RELOAD is set, PECBYTE has no effect.
Caution: Changing the PECEN configuration is not allowed when the I2C peripheral is enabled.
684/874
(max) (refer to the table in
t > t
IDLE HIGH
Target byte control mode
RM0366 Rev 5
Section 25.4.9).
for more details.
Bus idle detection
RM0366
for