ST STM32F301 6 Series Reference Manual page 168

Direct memory access controller (DMA)
10.6.3 DMA channel x configuration register (DMA_CCRx)
Address offset: 0x08 + 0x14 * (x - 1), (x = 1 to 7)
Reset value: 0x0000 0000
The register fields/bits MEM2MEM, PL[1:0], MSIZE[1:0], PSIZE[1:0], MINC, PINC, and DIR
are read-only when EN = 1.
The states of MEM2MEM and CIRC bits must not be both high at the same time.
31 30 29
Res. Res. Res. Res.
15 14 13
MEM2
Res. PL[1:0]
MEM
rw rw
Bits 31:15 Reserved, must be kept at reset value.
Bit 14 MEM2MEM: Memory-to-memory mode
0: Disabled
1: Enabled
Note: This bit is set and cleared by software. It must not be written when the channel is
Bits 13:12 PL[1:0]: Priority level
00: Low
01: Medium
10: High
11: Very high
Note: This bitfield is set and cleared by software. It must not be written when the channel is
Bits 11:10 MSIZE[1:0]: Memory size
Defines the data size of each DMA transfer to the identified memory.
In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the
memory destination if DIR = 0.
In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and
the peripheral destination if DIR = 0.
00: 8 bits
01: 16 bits
10: 32 bits
11: Reserved
Note: This bitfield is set and cleared by software. It must not be written when the channel is
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28 27 26 25
Res. Res. Res.
12 11 10 9
MSIZE[1:0] PSIZE[1:0]
rw rw rw rw
enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
24 23 22
Res. Res. Res.
8 7 6
MINC PINC CIRC
rw rw rw
RM0366 Rev 5
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
DIR TEIE HTIE
rw rw rw rw
RM0366
17 16
Res. Res.
1 0
TCIE EN
rw rw