ST STM32F301 6 Series Reference Manual page 170

Direct memory access controller (DMA)
Bit 4 DIR: Data transfer direction
This bit must be set only in memory-to-peripheral and peripheral-to-memory modes.
0: Read from peripheral
1: Read from memory
Note: This bit is set and cleared by software. It must not be written when the channel is
Bit 3 TEIE: Transfer error interrupt enable
0: Disabled
1: Enabled
Note: This bit is set and cleared by software. It must not be written when the channel is
Bit 2 HTIE: Half transfer interrupt enable
0: Disabled
1: Enabled
Note: This bit is set and cleared by software. It must not be written when the channel is
Bit 1 TCIE: Transfer complete interrupt enable
0: Disabled
1: Enabled
Note: This bit is set and cleared by software. It must not be written when the channel is
Bit 0 EN: Channel enable
When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again
by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared
(by setting the CTEIFx bit of the DMA_IFCR register).
0: Disabled
1: Enabled
Note: This bit is set and cleared by software.
10.6.4 DMA channel x number of data to transfer register (DMA_CNDTRx)
Address offset: 0x0C + 0x14 * (x - 1), (x = 1 to 7)
Reset value: 0x0000 0000
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– Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register.
This is still valid in a memory-to-memory mode.
– Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx
register. This is still valid in a peripheral-to-peripheral mode.
– Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx
register. This is still valid in a memory-to-memory mode.
– Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register.
This is still valid in a peripheral-to-peripheral mode.
enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).
enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).
enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).
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NDT[15:0]
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RM0366 Rev 5
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RM0366
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