ST STM32F301 6 Series Reference Manual page 720

Universal synchronous/asynchronous receiver transmitter (USART/UART)
CLOCK
Character transmission procedure
1. Program the M bits in USART_CR1 to define the word length.
2. Select the desired baud rate using the USART_BRR register.
3. Program the number of stop bits in USART_CR2.
4. Enable the USART by writing the UE bit in USART_CR1 register to 1.
5. Select DMA enable (DMAT) in USART_CR3 if multibuffer communication is to take
place. Configure the DMA register as explained in multibuffer communication.
6. Set the TE bit in USART_CR1 to send an idle frame as first transmission.
7. Write the data to send in the USART_TDR register (this clears the TXE bit). Repeat this
for each data to be transmitted in case of single buffer.
8. After writing the last data into the USART_TDR register, wait until TC=1. This indicates
that the transmission of the last frame is complete. This is required for instance when
the USART is disabled or enters the Halt mode to avoid corrupting the last
transmission.
Single byte communication
Clearing the TXE bit is always performed by a write to the transmit data register.
The TXE bit is set by hardware and it indicates:
•
The data has been moved from the USART_TDR register to the shift register and the
data transmission has started.
•
The USART_TDR register is empty.
•
The next data can be written in the USART_TDR register without overwriting the
previous data.
This flag generates an interrupt if the TXEIE bit is set.
When a transmission is taking place, a write instruction to the USART_TDR register stores
the data in the TDR register; next, the data is copied in the shift register at the end of the
currently ongoing transmission.
720/874
Figure 278. Configurable stop bits
8-bit data, 1 Stop bit
Data frame
Start bit Bit0 Bit1 Bit2
8-bit data, 1 1/2 Stop bits
Data frame
Start bit Bit0 Bit1 Bit2
8-bit data, 2 Stop bits
Data frame
Start bit Bit0 Bit1 Bit2
RM0366 Rev 5
Possible
parity bit
Bit3 Bit4 Bit5 Bit6 Bit7
**
Possible
parity bit
Bit3 Bit4 Bit5 Bit6 Bit7
Possible
parity bit
Bit3 Bit4 Bit5 Bit6 Bit7
Next
Next data frame
start
Stop
bit
bit
** LBCL bit controls last data clock pulse
Next
Next data frame
start
1.5
bit
Stop
bits
Next
Next data frame
start
2
bit
Stop
bits
RM0366
MSv31887V1