ST STM32F301 6 Series Reference Manual page 295

RM0366
There is no clock enable control bit provided in the RCC controller. Reset and clock enable
bits are common for COMP and SYSCFG. To use a clock source for the comparator, the
SYSCFG clock enable control bit must be set in the RCC controller.
Important: The polarity selection logic and the output redirection to the port works
independently from the PCLK2 clock. This allows the comparator to work even in Stop
mode.
14.3.4 Comparator LOCK mechanism
The comparators can be used for safety purposes, such as over-current or thermal
protection. For applications having specific functional safety requirements, it is necessary to
insure that the comparator programming cannot be altered in case of spurious register
access or program counter corruption.
For this purpose, the comparator control and status registers can be write-protected (read-
only).
Once the programming is completed, using bits 30:0 of COMPx_CSR, the COMPx LOCK bit
can be set to 1. This causes the whole COMP_CSR register to become read-only, including
the COMPx LOCK bit.
The write protection can only be reset by a MCU reset.
14.3.5 Comparator output blanking function
The purpose of the blanking function is to prevent the current regulation to trip upon short
current spikes at the beginning of the PWM period (typically the recovery current in power
switches anti parallel diodes).It consists of a selection of a blanking window which is a timer
output compare signal. The selection is done by software (refer to the comparator register
description for possible blanking signals). Then, the complementary of the blanking signal is
ANDed with the comparator output to provide the wanted comparator output. See the
example provided in the figure below.
RM0366 Rev 5
Comparator (COMP)
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