ST STM32F301 6 Series Reference Manual page 662

Inter-integrated circuit interface (I2C)
Target transmitter
A transmit interrupt status (TXIS) flag is generated when the I2C_TXDR register becomes
empty. An interrupt is generated if the TXIE bit of the I2C_CR1 register is set.
The TXIS flag is cleared when the I2C_TXDR register is written with the next data byte to
transmit.
When NACK is received, the NACKF flag is set in the I2C_ISR register and an interrupt is
generated if the NACKIE bit of the I2C_CR1 register is set. The target automatically
releases the SCL and SDA lines to let the controller perform a STOP or a RESTART
condition. The TXIS bit is not set when a NACK is received.
When STOP is received and the STOPIE bit of the I2C_CR1 register is set, the STOPF flag
of the I2C_ISR register is set and an interrupt is generated. In most applications, the SBC bit
is usually programmed to 0. In this case, if TXE = 0 when the target address is received
(ADDR = 1), the user can choose either to send the content of the I2C_TXDR register as the
first data byte, or to flush the I2C_TXDR register, by setting the TXE bit in order to program
a new data byte.
In target byte control mode (SBC = 1), the number of bytes to transmit must be programmed
in NBYTES[7:0] in the address match interrupt subroutine (ADDR = 1). In this case, the
number of TXIS events during the transfer corresponds to the value programmed in
NBYTES[7:0].
Caution: When NOSTRETCH = 1, the SCL clock is not stretched while the ADDR flag is set, so the
user cannot flush the I2C_TXDR register content in the ADDR subroutine to program the
first data byte. The first data byte to send must be previously programmed in the I2C_TXDR
register:
•
This data can be the one written in the last TXIS event of the previous transmission
message.
•
If this data byte is not the one to send, the I2C_TXDR register can be flushed, by
setting the TXE bit, to program a new data byte. The STOPF bit must be cleared only
after these actions. This guarantees that they are executed before the first data
transmission starts, following the address acknowledge.
If STOPF is still set when the first data transmission starts, an underrun error is
generated (the OVR flag is set).
If a TXIS event (transmit interrupt or transmit DMA request) is required, the user must
set the TXIS bit in addition to the TXE bit, to generate the event.
662/874 RM0366 Rev 5
RM0366