ST STM32F301 6 Series Reference Manual page 652

Inter-integrated circuit interface (I2C)
The following figure shows the transmission of a single byte. The controller generates nine
SCL pulses. The transmitter sends the eight data bits to the receiver with the SCL pulses 1
to 8. Then the receiver sends the acknowledge bit to the transmitter with the ninth SCL
pulse.
SDA
SCL
The acknowledge can be enabled or disabled by software. The own addresses of the I2C
peripheral can be selected by software.
25.4.5 I2C initialization
Enabling and disabling the peripheral
Before enabling the I2C peripheral, configure and enable its clock through the RCC, and
initialize its control registers.
The I2C peripheral can then be enabled by setting the PE bit of the I2C_CR1 register.
Disabling the I2C peripheral by clearing the PE bit resets the I2C peripheral. Refer to
Section 25.4.6
Noise filters
Before enabling the I2C peripheral by setting the PE bit of the I2C_CR1 register, the user
must configure the analog and/or digital noise filters, as required.
The analog noise filter on the SDA and SCL inputs complies with the I²C-bus specification
which requires, in Fast-mode and Fast-mode Plus, the suppression of spikes shorter than
50 ns. Enabled by default, it can be disabled by setting the ANFOFF bit.
The digital filter is controlled through the DNF[3:0] bitfield of the I2C_CR1 register. When it is
enabled, the internal SCL and SDA signals only take the level of their corresponding I²C-bus
line when remaining stable for more than DNF[3:0] periods of I2CCLK. This allows
suppressing spikes shorter than the filtering capacity period programmable from one to
fifteen I2CCLK periods.
The following table compares the two filters.
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Figure 247. I²C-bus protocol
MSB
1
Start
condition
for more details.
RM0366 Rev 5
2 8
RM0366
ACK
9
Stop
condition
MS19854V1