ST STM32F301 6 Series Reference Manual page 591

RM0366
CNT down-counter
T[6:0]
W[6:0]
0x3F
wwdg_ewit
wwdg_rst
T6 bit
The formula to calculate the timeout value is given by:
where:
•
t
WWDG
• t
PCLK
•
4096: value corresponding to internal divider
As an example, if APB1 frequency is 48 MHz, WDGTB[1:0] is set to 3, and T[5:0] is set to
63:
Refer to the datasheet for the minimum and maximum values of t
Figure 243. Window watchdog timing diagram
Refresh not allowed
t = t
WWDG PCLK1
: WWDG timeout
: APB1 clock period measured in ms
(
t WWDG = 1
Refresh allowed
0x41
0x40
0x3F
WDGTB[1:0]
× 4096 × 2
3
⁄ ) × ×
48000 4096 2
RM0366 Rev 5
System window watchdog (WWDG)
WDGTB
T x 4096 x 2
pclk
EWIF = 0
× ( T 5:0 [ ] 1 )
+
× ( )
63 + 1 = 43.69ms
.
WWDG
Time
MS47266V1
( ms )
591/874
594