ST STM32F301 6 Series Reference Manual page 151

RM0366
Bits 31:3 Reserved, must be kept at reset value
Bits 1: 0 Reserved, must be kept at reset value
9.1.7 SYSCFG register map
Offset Register
SYSCFG_CFGR1
0x00
Reset value
SYSCFG_EXTICR1
0x08
Reset value
SYSCFG_EXTICR2
0x0C
Reset value
SYSCFG_EXTICR3
0x10
Reset value
SYSCFG_EXTICR4
0x14
Reset value
SYSCFG_CFGR2
0x18
Reset value
1. This bit is not available on the STM32F318xx
Refer to
Bit 3 Reserved, must be kept at reset value
Bit 2 PVD_LOCK: PVD lock enable bit
This bit is set by software and cleared by a system reset. It can be used to
enable and lock the PVD connection to TIM1/15/16/17 Break input, as well as
the PVDE and PLS[2:0] in the PWR_CR register.
0: PVD interrupt disconnected from TIM1/15/16/17 Break input. PVDE and
PLS[2:0] bits can be programmed by the application.
1: PVD interrupt connected to TIM1/15/16/17 Break input, PVDE and PLS[2:0]
bits are read only (This bit is not available on the STM32F318xx).
Table 22. SYSCFG register map and reset values
FPU_IE[5..0]
1 1 1 1 1 0
Section 2.2 on page 40
System configuration controller (SYSCFG)
0 0 0 0 0 0 0 0
EXTI3[3:0]
0
EXTI7[3:0]
0
EXTI11[3:0]
0
EXTI15[3:0]
0
for the register boundary addresses.
RM0366 Rev 5
0 0 0 0 0
EXTI2[3:0] EXTI1[3:0]
0 0 0 0 0 0 0 0 0 0
EXTI6[3:0] EXTI5[3:0]
0 0 0 0 0 0 0 0 0 0
EXTI10[3:0] EXTI9[3:0]
0 0 0 0 0 0 0 0 0 0
EXTI14[3:0] EXTI13[3:0]
0 0 0 0 0 0 0 0 0 0
X X
EXTI0[3:0]
0 0 0 0 0
EXTI4[3:0]
0 0 0 0 0
EXTI8[3:0]
0 0 0 0 0
EXTI12[3:0]
0 0 0 0 0
0
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