ST STM32F301 6 Series Reference Manual page 740

Universal synchronous/asynchronous receiver transmitter (USART/UART)
Idle or
preceding
transmission
Clock (CPOL=0,
CPHA=0)
Clock (CPOL=0,
CPHA=1)
Clock (CPOL=1,
CPHA=0)
Clock (CPOL=1,
CPHA=1)
Data on TX
(from master)
Data on RX
(from slave)
Capture
strobe
(capture strobe on CK rising
edge in this example)
Data on RX (from slave)
t
SETUP=
Note: The function of CK is different in smartcard mode. Refer to
smartcard mode
740/874
Figure 289. USART data clock timing diagram (M bits = 01)
Start
0 1
Start LSB
0 1
LSB
Figure 290. RX data setup/hold time
CK
t 1/16 bit time
HOLD
for more details.
M bits =01 (9 data bits)
2 3 4 5
2 3 4 5
*LBCL bit controls last data pulse
Valid DATA bit
t t
SETUP HOLD
RM0366 Rev 5
Idle or next
Stop
transmission
*
*
*
*
7
6 8
MSB Stop
6 8
7
MSB
*
Section 26.5.13: USART
RM0366
MSv34710V1
MSv31161V2