ST STM32F301 6 Series Reference Manual page 357

RM0366
TIMx_SMCR
OCREF_CLR
ETRF
ocref_clr_int
CNT > CCR4
CNT = CCR4
Figure 123. Output stage of capture/compare channel (channel 5, idem ch. 6)
OCREF_CLR
ETRF
CNT > CCR5
CNT = CCR5
1. Not available externally.
The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.
Figure 122. Output stage of capture/compare channel (channel 4)
OCCS
0
1
OC4REF
Output
mode
selector
controller
OC3REF
OC4CE OC4M[3:0]
TIM1_CCMR2
TIMx_SMCR
OCCS
0
1
ocref_clr_int
Output
mode
controller
OC5CE OC5M[3:0]
TIM1_CCMR2
To the master
mode controller
OC4REFC
'0'
0
Output
1
CC4E
TIM1_CCER
To the master
mode controller
'0'
0
OC5REF
1
CC5E
TIM1_CCER
RM0366 Rev 5
Advanced-control timer (TIM1)
0
Output
enable
1
circuit
CC4P
CC4E TIM1_CCER
TIM1_CCER
OSSI
MOE
OIS4
0
Output
enable
1
circuit
CC5P
CC5E TIM1_CCER
TIM1_CCER
OSSI
MOE
OIS5 TIM1_CR2
OC4
TIM1_BDTR
TIM1_CR2
MS33100V2
(1)
OC5
TIM1_BDTR
MS33101V2
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