ST STM32F301 6 Series Reference Manual page 670

Inter-integrated circuit interface (I2C)
Caution: For compliance with the I²C-bus or SMBus specification, the controller clock must respect
the timings in the following table.
Symbol
f SCL clock frequency
SCL
t Hold time (repeated) START condition
HD:STA
Set-up time for a repeated START
t
SU:STA
condition
t Set-up time for STOP condition
SU:STO
Bus free time between a STOP and
t
BUF
START condition
t Low period of the SCL clock
LOW
t High period of the SCL clock
HIGH
t Rise time of both SDA and SCL signals
r
t Fall time of both SDA and SCL signals
f
Note: The SCLL[7:0] bitfield also determines the
and
t
HD:STA
Refer to
frequency.
Controller communication initialization (address phase)
To initiate the communication with a target to address, set the following bitfields of the
I2C_CR2 register:
•
ADD10: addressing mode (7-bit or 10-bit)
•
SADD[9:0]: target address to send
•
RD_WRN: transfer direction
•
HEAD10R: in case of 10-bit address read, this bit determines whether the header only
(for direction change) or the complete address sequence is sent.
• NBYTES[7:0]: the number of bytes to transfer; if equal to or greater than 255 bytes, the
bitfield must initially be set to 0xFF.
Note: Changing these bitfields is not allowed as long as the START bit is set.
Before launching the communication, make sure that the I²C-bus is idle. This can be
checked using the bus idle detection function or by verifying that the IDR bits of the GPIOs
selected as SDA and SCL are set. Any low-level incident on the I²C-bus lines that coincides
with the START condition asserted by the I2C peripheral may cause its deadlock if not
filtered out by the input filters. If such incidents cannot be prevented, design the software so
that it restores the normal operation of the I2C peripheral in case of a deadlock, by toggling
the PE bit of the I2C_CR1 register.
670/874
Table 87. I²C-bus and SMBus specification clock timings
Parameter
timings
t .
SU:STO
Section 25.4.10 for examples of I2C_TIMINGR settings versus the I2CCLK
Standard- Fast-mode
mode (Sm) (Fm)
Min Max Min Max
- 100 -
4.0 - 0.6
4.7 - 0.6
4.0 - 0.6
4.7 - 1.3
4.7 - 1.3
4.0 - 0.6
- 1000 -
- 300 -
and
t t
BUF SU:STA
RM0366 Rev 5
Fast-mode
SMBus
Plus (Fm+)
Min Max Min
400 - 1000 -
- 0.26 - 4.0
- 0.26 - 4.7
- 0.26 - 4.0
- 0.5 - 4.7
- 0.5 - 4.7
- 0.26 - 4.0
300 - 120 -
300 - 120 -
timings and SCLH[7:0] the
RM0366
Unit
Max
100 kHz
-
-
-
µs
-
-
50
1000
ns
300