ST STM32F301 6 Series Reference Manual page 259

RM0366
12.5.10 ADC regular sequence register 1 (ADCx_SQR1, x=1)
Address offset: 0x30
Reset value: 0x0000 0000
31 30 29
Res. Res. Res.
15 14 13
SQ2[3:0]
rw rw rw
Bits 31:29 Reserved, must be kept at reset value.
Bits 28:24 SQ4[4:0]: 4th conversion in regular sequence
These bits are written by software with the channel number (1..18) assigned as the 4th in the
regular conversion sequence.
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no
Note: Analog input channel 0 is not mapped: value "00000" should not be used
Bit 23 Reserved, must be kept at reset value.
Bits 22:18 SQ3[4:0]: 3rd conversion in regular sequence
These bits are written by software with the channel number (1..18) assigned as the 3rd in the
regular conversion sequence.
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no
Note: Analog input channel 0 is not mapped: value "00000" should not be used
Bit 17 Reserved, must be kept at reset value.
Bits 16:12 SQ2[4:0]: 2nd conversion in regular sequence
These bits are written by software with the channel number (1..18) assigned as the 2nd in the
regular conversion sequence.
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no
Note: Analog input channel 0 is not mapped: value "00000" should not be used
Bit 11 Reserved, must be kept at reset value.
28 27 26 25
SQ4[4:0]
rw rw rw rw
12 11 10 9
Res.
rw rw rw
regular conversion is ongoing).
regular conversion is ongoing).
regular conversion is ongoing).
24 23 22
Res.
rw rw
8 7 6
SQ1[4:0] Res.
rw rw rw
RM0366 Rev 5
Analog-to-digital converters (ADC)
21 20 19 18
SQ3[4:0]
rw rw rw rw
5 4 3 2
Res.
rw rw
17 16
Res. SQ2[4]
rw
1 0
L[3:0]
rw rw
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