ST STM32F301 6 Series Reference Manual page 700

Inter-integrated circuit interface (I2C)
Bit 5 STOPIE: STOP detection interrupt enable
Bit 4 NACKIE: Not acknowledge received interrupt enable
Bit 3 ADDRIE: Address match interrupt enable (target only)
Bit 2 RXIE: RX interrupt enable
Bit 1 TXIE: TX interrupt enable
Bit 0 PE: Peripheral enable
Note: When PE = 0, the I2C SCL and SDA lines are released. Internal state machines and
25.9.2 I2C control register 2 (I2C_CR2)
Address offset: 0x04
Reset value: 0x0000 0000
Access: no wait states, except if a write access occurs while a write access is ongoing. In
this case, wait states are inserted in the second write access until the previous one is
completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.
31 30 29
Res. Res. Res. Res.
15 14 13
HEAD1
NACK STOP START
rs rs rs
Bits 31:27 Reserved, must be kept at reset value.
Bit 26 PECBYTE: Packet error checking byte
Note: Writing 0 to this bit has no effect.
700/874
0: STOP detection (STOPF) interrupt disabled
1: STOP detection (STOPF) interrupt enabled
0: Not acknowledge (NACKF) received interrupts disabled
1: Not acknowledge (NACKF) received interrupts enabled
0: Address match (ADDR) interrupts disabled
1: Address match (ADDR) interrupts enabled
0: Receive (RXNE) interrupt disabled
1: Receive (RXNE) interrupt enabled
0: Transmit (TXIS) interrupt disabled
1: Transmit (TXIS) interrupt enabled
0: Peripheral disabled
1: Peripheral enabled
status bits are put back to their reset value. When cleared, PE must be kept low for at
least three APB clock cycles.
28 27 26 25
PECBY AUTOE
Res.
TE ND
rs rw
12 11 10 9
RD_W
ADD10
0R RN
rw rw rw rw
This bit is set by software, and cleared by hardware when the PEC is transferred, or when a
STOP condition or an Address matched is received, also when PE = 0.
0: No PEC transfer
1: PEC transmission/reception is requested
This bit has no effect when RELOAD is set, and in target mode when SBC = 0.
24 23 22
RELOA
D
rw rw rw
8 7 6
rw rw rw
RM0366 Rev 5
21 20 19 18
NBYTES[7:0]
rw rw rw rw
5 4 3 2
SADD[9:0]
rw rw rw rw
RM0366
17 16
rw rw
1 0
rw rw