ST STM32F301 6 Series Reference Manual page 224

Analog-to-digital converters (ADC)
The ADC also notifies the end of Sampling phase by setting the status bit EOSMP (for
regular conversions only). EOSMP flag is cleared by software by writing 1 to it. An interrupt
can be generated if bit EOSMPIE is set.
12.3.24 End of conversion sequence (EOS, JEOS)
The ADC notifies the application for each end of regular sequence (EOS) and for each end
of injected sequence (JEOS) event.
The ADC sets the EOS flag as soon as the last data of the regular conversion sequence is
available in the ADCx_DR register. An interrupt can be generated if bit EOSIE is set. EOS
flag is cleared by the software either by writing 1 to it.
The ADC sets the JEOS flag as soon as the last data of the injected conversion sequence is
complete. An interrupt can be generated if bit JEOSIE is set. JEOS flag is cleared by the
software either by writing 1 to it.
12.3.25 Timing diagrams example (single/continuous modes,
hardware/software triggers)
Figure 49. Single conversions of a sequence, software trigger
(1)
ADSTART
EOC
EOS
RDY
(2)
ADC state
ADC_DR
by SW
1. EXTEN=0x0, CONT=0
2. Channels selected = 1,9, 10, 17; AUTDLY=0.
224/874
CH1 CH9 CH10 CH17
D1
D9 D10
by HW
RDY CH1
D17
RM0366 Rev 5
CH9 CH10 CH17
D1 D9 D10
Indicative timings
RM0366
RDY
D17
MS30549V1