ST STM32F301 6 Series Reference Manual page 110

Reset and clock control (RCC)
7.4.5 APB1 peripheral reset register (RCC_APB1RSTR)
Address offset: 0x10
Reset value: 0x0000 0000
Access: no wait state, word, half-word, and byte access
31 30 29
I2C3 DAC1 PWR
Res.
RST RST RST
rw
15 14 13
SPI3 SPI2
Res. Res.
RST RST
rw rw
Bit 31 Reserved, must be kept at reset value.
Bit 30 I2C3RST: I2C3 reset
Set and cleared by software.
Bit 29 DAC1RST: DAC1 interface reset
Set and cleared by software.
Bit 28 PWRRST: Power interface reset
Set and cleared by software.
Bits 27:23 Reserved, must be kept at reset value.
Bit 22 I2C2RST: I2C2 reset
Set and cleared by software.
Bit 21 I2C1RST: I2C1 reset
Set and cleared by software.
Bits 20:19 Reserved, must be kept at reset value.
Bit 18 USART3RST: USART3 reset
Set and cleared by software.
Bit 17 USART2RST: USART2 reset
Set and cleared by software.
110/874
28 27 26 25
Res. Res Res.
rw
12 11 10 9
WWDG
Res. Res.
RST
rw
0: No effect
1: Reset I2C3
0: No effect
1: Reset DAC1 interface
0: No effect
1: Reset power interface
0: No effect
1: Reset I2C2
0: No effect
1: Reset I2C1
0: No effect
1: Reset USART3
0: No effect
1: Reset USART2
24 23 22
I2C1
I2C2
Res. Res.
RST
RST
rw
8 7 6
Res. Res. Res. Res
RM0366 Rev 5
21 20 19 18
USART3
Res. Res.
RST
rw rw
5 4 3 2
TIM6
Res. Res
RST
rw
RM0366
17 16
USART2
Res.
RST
rw
1 0
TIM2
Res
RST
rw