ST STM32F301 6 Series Reference Manual page 722

Universal synchronous/asynchronous receiver transmitter (USART/UART)
Start bit detection
The start bit detection sequence is the same when oversampling by 16 or by 8.
In the USART, the start bit is detected when a specific sequence of samples is recognized.
This sequence is: 1 1 1 0 X 0 X 0X 0X 0 X 0X 0.
RX state
RX line
Ideal
sample
clock
Real
sample
clock
Conditions
to validate
the start bit
Note: If the sequence is not complete, the start bit detection aborts and the receiver returns to the
idle state (no flag is set), where it waits for a falling edge.
The start bit is confirmed (RXNE flag set, interrupt generated if RXNEIE=1) if the 3 sampled
bits are at 0 (first sampling on the 3rd, 5th and 7th bits finds the 3 bits at 0 and second
sampling on the 8th, 9th and 10th bits also finds the 3 bits at 0).
The start bit is validated (RXNE flag set, interrupt generated if RXNEIE=1) but the NF noise
flag is set if,
a)
or
b)
If neither conditions a. or b. are met, the start detection aborts and the receiver returns to the
idle state (no flag is set).
722/874
Figure 280. Start bit detection when oversampling by 16 or 8
1 2
X X
1 1 1 0 X
Falling edge
detection
for both samplings, 2 out of the 3 sampled bits are at 0 (sampling on the 3rd, 5th
and 7th bits and sampling on the 8th, 9th and 10th bits)
for one of the samplings (sampling on the 3rd, 5th and 7th bits or sampling on the
8th, 9th and 10th bits), 2 out of the 3 bits are found at 0.
Idle
3 4 5 6 7 8
Sampled values
X X X X X X 9
7/16
One-bit time
X 0 X 0 0 0
0
At least 2 bits At least 2 bits
out of 3 at 0 out of 3 at 0
RM0366 Rev 5
Start bit
9 10 11 12 13 14 15 16
10 11 12 13 14 15 16
6/16
7/16
0 X X X X X X
RM0366
ai15471d