ST STM32F301 6 Series Reference Manual page 122

Reset and clock control (RCC)
Bits 3:0 PREDIV: PREDIV division factor
These bits are set and cleared by software to select PREDIV division factor. They can be
written only when the PLL is disabled.
Note: Bit 0 is the same bit as bit17 in
0000: HSE input to PLL not divided
0001: HSE input to PLL divided by 2
0010: HSE input to PLL divided by 3
0011: HSE input to PLL divided by 4
0100: HSE input to PLL divided by 5
0101: HSE input to PLL divided by 6
0110: HSE input to PLL divided by 7
0111: HSE input to PLL divided by 8
1000: HSE input to PLL divided by 9
1001: HSE input to PLL divided by 10
1010: HSE input to PLL divided by 11
1011: HSE input to PLL divided by 12
1100: HSE input to PLL divided by 13
1101: HSE input to PLL divided by 14
1110: HSE input to PLL divided by 15
1111: HSE input to PLL divided by 16
7.4.13 Clock configuration register 3 (RCC_CFGR3)
Address: 0x30
Reset value: 0x0000 0000
Access: no wait states, word, half-word and byte access
31 30 29
Res. Res. Res. Res.
15 14 13
TIM17
Res. Res. Res.
SW
rw
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 TIM17SW: Timer17 clock source selection
Set and reset by software to select TIM17 clock source.
The bit is writable only when the following conditions occur: system clock source is the PLL
and AHB or APB2 subsystem clocks are not divided by more than 2 cumulatively.
The bit is reset by hardware when exiting from the previous condition (user must set the bit
again in case of a new switch is required)
0: PCLK2 clock (doubled frequency when prescaled) (default)
1: PLL vco output (running up to 144 MHz)
Bit 12 Reserved, must be kept at reset value.
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bit17 Clock configuration register (RCC_CFGR)
configuration register 2 (RCC_CFGR2)
28 27 26 25
Res. Res. Res.
12 11 10 9
TIM16 TIM15
Res.
SW SW
rw rw
Clock configuration register
(for compatibility with other STM32 products)
24 23 22
Res. Res. Res.
8 7 6
TIM1 I2C3
Res.
SW SW
rw rw
RM0366 Rev 5
(RCC_CFGR), so modifying
also modifies bit 0 in Clock
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
I2C2 I2C1
Res. Res.
SW SW
rw rw
RM0366
17 16
Res. Res.
1 0
USART1SW[1:0]
rw rw