ST STM32F301 6 Series Reference Manual page 106

Reset and clock control (RCC)
Bits 7:4 HPRE[3:0]: HLCK prescaler
Set and cleared by software to control the division factor of the AHB clock.
Note: The prefetch buffer must be kept on when using a prescaler different from 1 on the
Bits 3:2 SWS[1:0]: System clock switch status
Set and cleared by hardware to indicate which clock source is used as system clock.
Bits 1:0 SW[1:0]: System clock switch
Set and cleared by software to select SYSCLK source.
Cleared by hardware to force HSI selection when leaving Stop and Standby mode or in case
of failure of the HSE oscillator used directly or indirectly as system clock (if the Clock Security
System is enabled).
7.4.3 Clock interrupt register (RCC_CIR)
Address offset: 0x08
Reset value: 0x0000 0000
Access: no wait state, word, half-word, and byte access
31 30 29
Res. Res. Res. Res.
15 14 13
PLL
Res. Res. Res.
RDYIE
106/874
0xxx: SYSCLK not divided
1000: SYSCLK divided by 2
1001: SYSCLK divided by 4
1010: SYSCLK divided by 8
1011: SYSCLK divided by 16
1100: SYSCLK divided by 64
1101: SYSCLK divided by 128
1110: SYSCLK divided by 256
1111: SYSCLK divided by 512
AHB clock. Refer to section
00: HSI oscillator used as system clock
01: HSE oscillator used as system clock
10: PLL used as system clock
11: not applicable
00: HSI selected as system clock
01: HSE selected as system clock
10: PLL selected as system clock
11: not allowed
28 27 26 25
Res. Res. Res.
12 11 10 9
HSE HSI LSE
RDYIE RDYIE RDYIE
rw rw rw rw
Read operations on page 47
24 23 22
Res. CSSC Res. Res.
w
8 7 6
LSI
CSSF Res. Res.
RDYIE
rw r
RM0366 Rev 5
for more details.
21 20 19 18
PLL HSE HSI
RDYC RDYC RDYC
w w w
5 4 3 2
PLL HSE HSI
RDYF RDYF RDYF
r r r
RM0366
17 16
LSE LSI
RDYC RDYC
w w
1 0
LSE LSI
RDYF RDYF
r r