ST STM32F301 6 Series Reference Manual page 269

RM0366
12.5.19 ADC Analog Watchdog 3 Configuration Register (ADCx_AWD3CR,
x=1)
Address offset: 0xA4
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
Bits 31:19 Reserved, must be kept at reset value.
Bits 18:1 AWD3CH[18:1]: Analog watchdog 3 channel selection
These bits are set and cleared by software. They enable and select the input channels to be guarded
by the analog watchdog 3.
AWD3CH[i] = 0: ADC analog input channel-i is not monitored by AWD3
AWD3CH[i] = 1: ADC analog input channel-i is monitored by AWD3
When AWD3CH[18:1] = 000..0, the analog Watchdog 3 is disabled
Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers.
Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bit 0 Reserved, must be kept at reset value.
12.5.20 ADC Differential Mode Selection Register (ADCx_DIFSEL, x=1)
Address offset: 0xB0
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
24 23 22
Res. Res. Res.
8 7 6
AWD3CH[15:1]
rw rw rw
24 23 22
Res. Res. Res.
8 7 6
DIFSEL[15:1]
rw rw rw
RM0366 Rev 5
Analog-to-digital converters (ADC)
21 20 19 18
Res. Res. Res.
5 4 3 2
rw rw rw rw
21 20 19 18
Res. Res. Res.
r
5 4 3 2
rw rw rw rw
17 16
AWD3CH[18:16]
1 0
Res.
rw
17 16
DIFSEL[18:16]
r r
1 0
Res.
rw
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