ST STM32F301 6 Series Reference Manual page 869

RM0366
Date
21-Jul-2016
Table 128. Document revision history (continued)
Revision
Updated RTC section:
– Updated Section 24.3.7: RTC initialization and configuration step 3
in Section : Programming the wakeup timer.
– Updated Section 24.6.4: RTC initialization and status register
(RTC_ISR) bit 2 WUTWF: wakeup timer write flag.
– Updated WUCKSEL bits in Figure 241: RTC block diagram.
– Added case of RTC clocked by LSE in Section 24.3.9: Resetting the
RTC.
– Updated Figure 241: RTC block diagram adding note.
– Updated section with only 2 RTC Tamper.
– Updated Section 24.3.15: Calibration clock output.
– Added caution at the end of Section 24.6.3: RTC control register
(RTC_CR).
– Updated caution at the end of Section 24.6.16: RTC tamper and
alternate function configuration register (RTC_TAFCR).
Updated RCC section:
– Updated Section 7.4.9: RTC domain control register (RCC_BDCR)
LSEDRV[1:0] bits: '01' and '10' combinations swapped.
– Updated Section 7.2.9: RTC clock adding "the RTC remains clocked
and functional under system reset" when the RTC clock is LSE.
– Updated Figure 14: STM32F318x8STM32F3xx clock tree replacing
'USARTx (x=1,2,3)' by 'USART1'
4
– Updated Section 7.4.10: Control/status register (RCC_CSR) and
(continued)
Updated Section 7.4.14: RCC register map adding V18PWRRSTF
bit 23.
Updated TIMERS section:
– Updated Section 18.3.13: One-pulse mode modifying "IC2S=01" by
"CC2S=01".
– Updated Section 19.5.21: Slave mode – combined reset + trigger
mode (TIM15 only) adding (TIM15 only) on the title.
– Updated Section 19.6.8: TIM15 capture/compare mode register 1
[alternate] (TIM15_CCMR1) and Section 19.6.27: TIM15 register
map replacing bit 7 'reserved' by OC1CE.
– Updated Section 19.7.6: TIMx capture/compare mode register 1
(TIM16_CCMR1) (TIMx_CCMR1)(x = 16 to 17) and Section 19.7.41:
TIM16/TIM17 register map replacing bit 7 'reserved' by OC1CE.
– Added Section 17.3.4: External trigger input.
– Updated Section 18.4.14: TIM2 prescaler
(TIM2_PSC)(TIM3_PSC)(TIMx_PSC)N/A and Section 20.4.7:
TIM6TIMx prescaler (TIM6_PSC)(TIMx_PSC)(x = 6 to 7)(x = 3 to 7)
PSC[15:0] bits description.
– Updated Section 17.4.5: TIM1 status register
(TIM1_SRTIMx_SR)N/A and Section 17.4.68: TIM1 register map
CC5IF and CC6IF bit names.
Updated Embedded Flash memory section:
– Updated Section 3.5.1: Flash access control register (FLASH_ACR)
bits LATENCY[2:0] replacing SYSCLK by HCLK.
RM0366 Rev 5
Revision history
Changes
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