ST STM32F301 6 Series Reference Manual page 597

RM0366
23.3.3 Hardware watchdog
If this feature is enabled through the device option bits, the watchdog is automatically
enabled at power-on, and generates a reset unless the
written by the software before the counter reaches the end of count, and if the downcounter
is lower than the window value (WIN[11:0]).
23.3.4 Register access protection
Write access to
and IWDG window register (IWDG_WINR)
0x0000 5555 in the
different value breaks the sequence, and register access is protected again. This is the case
of the reload operation (writing 0x0000 AAAA).
A status register is available to indicate that an update of the prescaler, or of the
downcounter reload value, or of the window value, is ongoing.
23.3.5 Debug mode
When the device enters Debug mode (core halted), the IWDG counter either continues to
work normally or stops, depending on the configuration of the corresponding bit in
DBGMCU freeze register.
IWDG prescaler register
IWDG key register
RM0366 Rev 5
Independent watchdog (IWDG)
IWDG key register (IWDG_KR)
(IWDG_PR), IWDG reload register
is protected. To modify them, first write the code
(IWDG_KR). A write access to this register with a
is
(IWDG_RLR),
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