ST STM32F301 6 Series Reference Manual page 90

Reset and clock control (RCC)
7 Reset and clock control (RCC)
7.1 Reset
There are three types of reset, defined as system reset, power reset and RTC domain reset.
7.1.1 Power reset
A power reset is generated when one of the following events occurs:
1. Power-on/power-down reset (POR/PDR reset)
2. When exiting Standby mode
A power reset sets all registers to their reset values except the RTC domain (see
7.1.2 System reset
A system reset sets all registers to their reset values unless specified otherwise in the
register description.
A system reset is generated when one of the following events occurs:
1. A low level on the NRST pin (external reset)
2. Window watchdog event (WWDG reset)
3. Independent watchdog event (IWDG reset)
4. A software reset (SW reset) (see
5. Low-power management reset (see
6. Option byte loader reset (see
7. A power reset
The reset source can be identified by checking the reset flags in the Control/Status register,
RCC_CSR (see
These sources act on the NRST pin and it is always kept low during the delay phase. The
RESET service routine vector is fixed at address 0x0000_0004 in the memory map.
The system reset signal provided to the device is output on the NRST pin. The pulse
generator guarantees a minimum reset pulse duration of 20 µs for each internal reset
source. In case of an external reset, the reset pulse is generated while the NRST pin is
asserted low.
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Option byte loader
Section 7.4.10: Control/status register
RM0366 Rev 5
Software reset)
Low-power management
reset)
(RCC_CSR)).
RM0366
Figure
reset)
6).