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RM0366
16.6.3
TSC interrupt clear register (TSC_ICR)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 MCEIC: Max count error interrupt clear
Bit 0 EOAIC: End of acquisition interrupt clear
16.6.4
TSC interrupt status register (TSC_ISR)
Address offset: 0x0C
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 MCEF: Max count error flag
This bit is set by hardware as soon as an analog I/O group counter reaches the max count
value specified. It is cleared by software writing 1 to the bit MCEIC of the TSC_ICR register.
0: No max count error (MCE) detected
1: Max count error (MCE) detected
Bit 0 EOAF: End of acquisition flag
This bit is set by hardware when the acquisition of all enabled group is complete (all GxS bits
of all enabled analog I/O groups are set or when a max count error is detected). It is cleared
by software writing 1 to the bit EOAIC of the TSC_ICR register.
0: Acquisition is ongoing or not started
1: Acquisition is complete
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
This bit is set by software to clear the max count error flag and it is cleared by hardware
when the flag is reset. Writing a 0 has no effect.
0: No effect
1: Clears the corresponding MCEF of the TSC_ISR register
This bit is set by software to clear the end of acquisition flag and it is cleared by hardware
when the flag is reset. Writing a 0 has no effect.
0: No effect
1: Clears the corresponding EOAF of the TSC_ISR register
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0366 Rev 5
Touch sensing controller (TSC)
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
17
16
Res.
Res.
1
0
MCEIC EOAIC
rw
rw
17
16
Res.
Res.
1
0
MCEF
EOAF
r
r
325/874
330
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