ST STM32F301 6 Series Reference Manual page 370

Advanced-control timer (TIM1)
The source for BRK_ACTH can be internal only:
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Caution: The internal sources protection is not available when the timer is in automatic output enable
mode (AOE bit set in the TIMx_BDTR). The MOE bit is set again on the next update event,
regardless of any pending error on the BRK_ACTH input.
The source for BRK2 can be:
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An external source connected to the BKIN2 pin
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An internal source coming from COMPx output, x = , 2, 4 or 6
If there are several break sources, the resulting break signal will be an OR between all the
input signals.
When exiting from reset, the break circuit is disabled and the MOE bit is low. The break
functions can be enabled by setting the BKE and BK2E bits in the TIMx_BDTR register. The
break input polarities can be selected by configuring the BKP and BK2P bits in the same
register. BKE/BK2E and BKP/BK2P can be modified at the same time. When the BKE/BK2E
and BKP/BK2P bits are written, a delay of 1 APB clock cycle is applied before the writing is
effective. Consequently, it is necessary to wait 1 APB clock period to correctly read back the
bit after the write operation.
Because MOE falling edge can be asynchronous, a resynchronization circuit has been
inserted between the actual signal (acting on the outputs) and the synchronous control bit
(accessed in the TIMx_BDTR register). It results in some delays between the asynchronous
and the synchronous signals. In particular, if MOE is set to 1 whereas it was low, a delay
must be inserted (dummy instruction) before reading it correctly. This is because the write
acts on the asynchronous signal whereas the read reflects the synchronous signal.
The break can be generated by any of the two break inputs (BRK, BRK2)and which has a:
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The digital filter feature is available on BRK and BRK2. It is not available on BRK_ACTH.
That means that the digital filter is:
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Available when the break source is external and comes from the external inputs
BKIN/BKIN2.
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Available when the break source is internal and connected to BRK (COMP4 output) or
BRK2 (all comparators' outputs)
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Not available when the break source is internal and connected to BRK_ACTH. (i.e.
PVD output, Cortex
Break events can also be generated by software using BG and B2G bits in the TIMx_EGR
register. The software break generation using BG and B2G is active whatever the BKE and
BK2E enable bits values.
370/874
A clock failure event generated by the CSS. For further information on the CSS,
refer to Section 7.2.7: Clock security system (CSS)
A PVD output
®
Cortex -M4F LOCKUP (Hardfault) output
COMPx output, x = (2, 6)
Programmable polarity (BKP/BK2P bit in the TIMx_BDTR register)
Programmable enable bit (BKE/BK2E in the TIMx_BDTR register)
Programmable filter (BKxF[3:0] bits in the TIMx_BDTR register) to avoid spurious
events.
®
-M4F LOCKUP (Hardfault) output or COMPx output, x = 2, 6).
RM0366 Rev 5
RM0366