ST STM32F301 6 Series Reference Manual page 434

General-purpose timer (TIM2)
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.
Timerclock = CK_CNT
Counter register
Counter underflow
(cnt_udf)
Update event (UEV)
Update interrupt flag
Timerclock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag
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Figure 158. Counter timing diagram, internal clock divided by 1
CK_PSC
CNT_EN
05
(UIF)
Figure 159. Counter timing diagram, internal clock divided by 2
CK_PSC
CNT_EN
0002
(UIF)
RM0366 Rev 5
04
03 02 01 00 36
0001 0000
35 34 33 32
31
0036 0035 0034
RM0366
30 2F
MS31184V1
0033
MS31185V1