ST STM32F301 6 Series Reference Manual page 204

Analog-to-digital converters (ADC)
For all the other control bits of the ADCx_CFGR, ADCx_SMPRx, ADCx_TRx, ADCx_SQRx,
ADCx_JDRy, ADCx_OFRy, ADCx_OFCHR and ADCx_IER registers:
•
For control bits related to configuration of regular conversions, the software is allowed
to write them only if the ADC is enabled (ADEN=1) and if there is no regular conversion
ongoing (ADSTART must be equal to 0).
•
For control bits related to configuration of injected conversions, the software is allowed
to write them only if the ADC is enabled (ADEN=1) and if there is no injected
conversion ongoing (JADSTART must be equal to 0).
The software is allowed to write the control bits ADSTP or JADSTP of the ADCx_CR
register only if the ADC is enabled and eventually converting and if there is no pending
request to disable the ADC (ADSTART or JADSTART must be equal to 1 and ADDIS to 0).
The software can write the register ADCx_JSQR at any time, when the ADC is enabled
(ADEN=1).
Note: There is no hardware protection to prevent these forbidden write accesses and ADC
behavior may become in an unknown state. To recover from this situation, the ADC must be
disabled (clear ADEN=0 as well as all the bits of ADCx_CR register).
12.3.11 Channel selection (SQRx, JSQRx)
There are up to 18 multiplexed channels per ADC:
•
5 fast analog inputs coming from GPIO pads (ADC_IN1..5)
•
Up to 10 slow analog inputs coming from GPIO pads (ADC_IN5..15). Depending on the
products, not all of them are available on GPIO pads.
•
ADC1 is connected to 3 internal analog inputs:
–
–
–
Note: To convert one of the internal analog channels, the corresponding analog sources must first
be enabled by programming bits VREFEN, TSEN or VBATEN in the ADCx_CCR registers.
It is possible to organize the conversions in two groups: regular and injected. A group
consists of a sequence of conversions that can be done on any channel and in any order.
For instance, it is possible to implement the conversion sequence in the following order:
ADC_IN3, ADC_IN8, ADC_IN2, ADC_IN2, ADC_IN0, ADC_IN2, ADC_IN2, ADC_IN15.
•
A regular group is composed of up to 16 conversions. The regular channels and their
order in the conversion sequence must be selected in the ADCx_SQR registers. The
total number of conversions in the regular group must be written in the L[3:0] bits in the
ADCx_SQR1 register.
•
An injected group is composed of up to 4 conversions. The injected channels and
their order in the conversion sequence must be selected in the ADCx_JSQR register.
The total number of conversions in the injected group must be written in the L[1:0] bits
in the ADCx_JSQR register.
ADCx_SQR registers must not be modified while regular conversions can occur. For this,
the ADC regular conversions must be first stopped by writing ADSTP=1 (refer to
Section 12.3.17: Stopping an ongoing conversion (ADSTP,
It is possible to modify the ADCx_JSQR registers on-the-fly while injected conversions are
occurring. Refer to
204/874
ADC1_IN16 = V = temperature sensor
TS
ADC1_IN17 = V /2 = V
BAT
ADC1_IN18 = V
REFINT
Section 12.3.21: Queue of context for injected conversions
channel
BAT
= Internal reference voltage.
RM0366 Rev 5
JADSTP)).
RM0366