ST STM32F301 6 Series Reference Manual page 727

RM0366
Framing error
A framing error is detected when the stop bit is not recognized on reception at the expected
time, following either a de-synchronization or excessive noise.
When the framing error is detected:
•
The FE bit is set by hardware
•
The invalid data is transferred from the Shift register to the USART_RDR register.
•
No interrupt is generated in case of single byte communication. However this bit rises
at the same time as the RXNE bit which itself generates an interrupt. In case of
multibuffer communication an interrupt is issued if the EIE bit is set in the USART_CR3
register.
The FE bit is reset by writing 1 to the FECF in the USART_ICR register.
Configurable stop bits during reception
The number of stop bits to be received can be configured through the control bits of Control
Register 2 - it can be either 1 or 2 in normal mode and 0.5 or 1.5 in smartcard mode.
•
0.5 stop bit (reception in smartcard mode): No sampling is done for 0.5 stop bit. As
a consequence, no framing error and no break frame can be detected when 0.5 stop bit
is selected.
•
1 stop bit: Sampling for 1 stop Bit is done on the 8th, 9th and 10th samples.
•
1.5 stop bits (smartcard mode): When transmitting in smartcard mode, the device
must check that the data is correctly sent. Thus the receiver block must be enabled (RE
=1 in the USART_CR1 register) and the stop bit is checked to test if the smartcard has
detected a parity error. In the event of a parity error, the smartcard forces the data
signal low during the sampling - NACK signal-, which is flagged as a framing error.
Then, the FE flag is set with the RXNE at the end of the 1.5 stop bits. Sampling for 1.5
stop bits is done on the 16th, 17th and 18th samples (1 baud clock period after the
beginning of the stop bit). The 1.5 stop bits can be decomposed into 2 parts: one 0.5
baud clock period during which nothing happens, followed by 1 normal stop bit period
during which sampling occurs halfway through. Refer to
smartcard mode on page 741
•
2 stop bits: Sampling for 2 stop bits is done on the 8th, 9th and 10th samples of the
first stop bit. If a framing error is detected during the first stop bit the framing error flag
is set. The second stop bit is not checked for framing error. The RXNE flag is set at the
end of the first stop bit.
Universal synchronous/asynchronous receiver transmitter (USART/UART)
RM0366 Rev 5
for more details.
Section 26.5.13: USART
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