ST STM32F301 6 Series Reference Manual page 225

RM0366
Figure 50. Continuous conversion of a sequence, software trigger
(1)
ADCSTART
EOC
EOS
ADSTP
(2)
ADC state
READY CH1
ADC_DR
by SW
1. EXTEN=0x0, CONT=1
2. Channels selected = 1,9, 10, 17; AUTDLY=0.
Figure 51. Single conversions of a sequence, hardware trigger
ADSTART
EOC
EOS
(1)
TRGX
(2)
ADC state
ADC_DR
by s/w
1. TRGx (over-frequency) is selected as trigger source, EXTEN = 01, CONT = 0
2. Channels selected = 1, 2, 3, 4; AUTDLY=0.
Figure 52. Continuous conversions of a sequence, hardware trigger
ADSTART
EOC
EOS
ADSTP
(1)
TRGx
(2)
ADC
RDY
ADC_DR
by s/w
1. TRGx is selected as trigger source, EXTEN = 10, CONT = 1
2. Channels selected = 1, 2, 3, 4; AUTDLY=0.
CH9 CH10 CH17
D1 D9 D10
by HW
CH1 CH2
RDY
D1
by h/w triggered
CH1 CH2 CH3
D1 D2
by h/w
triggered
CH1
CH9 CH10
D17 D1
CH3 CH4 READY
D2 D3
ignored
CH4 CH1 CH2
D3 D4 D1
ignored
RM0366 Rev 5
Analog-to-digital converters (ADC)
CH1
STP READY
D9
Indicative timings
CH1 CH2 CH3
D4 D1 D2
Indicative timings
STOP
CH3 CH4 CH1
D2 D3 D4
Not in scale timings
CH9
D1
MS30550V1
CH4 RDY
D3 D4
MS31013V2
RDY
MS31014V2
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