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ST STM32F446 Series Reference Manual

Advanced arm-based 32-bit mcus

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RM0390

Reference manual

®

STM32F446xx advanced Arm

-based 32-bit MCUs

Introduction

This reference manual is addressed to application developers. It provides complete

information on how to use the STM32F446xx microcontroller memory and peripherals.

The STM32F446xx constitute a family of microcontrollers with different memory sizes,

packages and peripherals.

For ordering information, mechanical and electrical device characteristics refer to the

corresponding datasheets.

®

®

®

For information on the Arm

Cortex

-M4 with FPU core, refer to the Cortex

-M4 Technical

Reference Manual.

Related documents

Available from STMicroelectronics web site www.st.com:

• STM32F446xx datasheets

®

®

For information on the Cortex

-M4 with FPU, refer to the STM32F3xx/F4xxx Cortex

-M4

with FPU programming manual (PM0214).

February 2018

RM0390 Rev 4

1/1328

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Summary of Contents for ST STM32F446 Series

Page 1 For information on the Arm Cortex -M4 with FPU core, refer to the Cortex -M4 Technical Reference Manual. Related documents Available from STMicroelectronics web site www.st.com: • STM32F446xx datasheets ® ® For information on the Cortex -M4 with FPU, refer to the STM32F3xx/F4xxx Cortex with FPU programming manual (PM0214).
Page 2: Table Of Contents
Contents RM0390 Contents Documentation conventions ....... . . 51 List of abbreviations for registers ....... 51 Glossary .
Page 3 RM0390 Contents 3.5.3 Erase ........... 70 3.5.4 Programming .
Page 4: Syscfg External Interrupt Configuration Register
Contents RM0390 5.2.2 Brownout reset (BOR) ........99 5.2.3 Programmable voltage detector (PVD) .
Page 5 RM0390 Contents 6.3.4 RCC clock interrupt register (RCC_CIR) ..... . . 133 6.3.5 RCC AHB1 peripheral reset register (RCC_AHB1RSTR) ..136 6.3.6 RCC AHB2 peripheral reset register (RCC_AHB2RSTR) .
Page 6 Contents RM0390 7.3.4 I/O port data registers ........181 7.3.5 I/O data bitwise handling .
Page 7 RM0390 Contents 8.2.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) ........199 8.2.7 Compensation cell control register (SYSCFG_CMPCR) .
Page 8 Contents RM0390 9.5.7 DMA stream x peripheral address register (DMA_SxPAR) (x = 0..7) . 231 9.5.8 DMA stream x memory 0 address register (DMA_SxM0AR) (x = 0..7) ........231 9.5.9 DMA stream x memory 1 address register (DMA_SxM1AR) (x = 0..7) .
Page 9 RM0390 Contents 11.5 NOR Flash/PSRAM controller ....... . 258 11.5.1 External memory interface signals .
Page 10 Contents RM0390 12.3.10 QUADSPI configuration ........334 12.3.11 QUADSPI usage .
Page 11 RM0390 Contents 13.3.11 Discontinuous mode ........364 13.4 Data alignment .
Page 12 Contents RM0390 13.13.17 ADC common regular data register for dual and triple modes (ADC_CDR) ..........398 13.13.18 ADC register map .
Page 13 RM0390 Contents 14.5.6 DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) ........418 14.5.7 DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) .
Page 14 Contents RM0390 15.7 DCMI register description ........435 15.7.1 DCMI control register (DCMI_CR) .
Page 15 RM0390 Contents 16.3.20 Timer synchronization ........493 16.3.21 Debug mode .
Page 16 Contents RM0390 17.3.9 PWM mode ..........542 17.3.10 One-pulse mode .
Page 17 RM0390 Contents 18.3.1 Time-base unit ......... . . 585 18.3.2 Counter modes .
Page 18 Contents RM0390 18.5.8 TIM10/11/13/14 prescaler (TIMx_PSC) ......624 18.5.9 TIM10/11/13/14 auto-reload register (TIMx_ARR) ....624 18.5.10 TIM10/11/13/14 capture/compare register 1 (TIMx_CCR1) .
Page 19 RM0390 Contents 20.4.4 Status register (IWDG_SR) ....... . . 644 20.4.5 IWDG register map .
Page 20 Contents RM0390 22.6 RTC registers ..........670 22.6.1 RTC time register (RTC_TR) .
Page 21 RM0390 Contents 23.4.9 FMPI2C_TIMINGR register configuration examples ....724 23.4.10 SMBus specific features ........725 23.4.11 SMBus initialization .
Page 22 Contents RM0390 24.3.9 Packet error checking ........777 24.4 C interrupts .
Page 23 RM0390 Contents 25.5 USART interrupts ......... . 834 25.6 USART registers .
Page 24 Contents RM0390 26.6.1 S general description ........869 26.6.2 I2S full-duplex .
Page 25 RM0390 Contents 27.3.11 Interrupt Generation ........914 27.3.12 Register protection .
Page 26 Contents RM0390 28.4 SAI interrupts ..........958 28.5 SAI registers .
Page 27 RM0390 Contents 29.5.2 R1b ..........1011 29.5.3 R2 (CID, CSD register) .
Page 28 Contents RM0390 30.3.2 Control, status and configuration registers ....1033 30.3.3 Tx mailboxes ......... . . 1033 30.3.4 Acceptance filters .
Page 29 RM0390 Contents 31.4.1 OTG block diagram ........1082 31.4.2 USB OTG pin and internal signals .
Page 30 Contents RM0390 31.15.4 OTG USB configuration register (OTG_GUSBCFG) ... . . 1118 31.15.5 OTG reset register (OTG_GRSTCTL) ......1121 31.15.6 OTG core interrupt register (OTG_GINTSTS) .
Page 31 RM0390 Contents 31.15.30 OTG host channel x DMA address register (OTG_HCDMAx) (x = 0..15, where x = Channel number) ..... . . 1157 31.15.31 Device-mode registers .
Page 32 Contents RM0390 31.15.54 OTG device control OUT endpoint 0 control register (OTG_DOEPCTL0) ........1182 31.15.55 OTG device OUT endpoint x interrupt register (OTG_DOEPINTx) (x = 0..5[FS] /8[HS], where x = Endpoint number) .
Page 33 RM0390 Contents 32.5.3 Bit Rising Error (BRE) ........1271 32.5.4 Short Bit Period Error (SBPE) .
Page 34 Contents RM0390 33.8.5 SW-DP registers ........1295 33.8.6 SW-AP registers .
Page 35 RM0390 Contents 34.1 Unique device ID register (96 bits) ......1317 34.2 Flash memory size register ....... . . 1318 34.3 Package data register .
Page 36 List of tables RM0390 List of tables Table 1. STM32F446xx register boundary addresses ........57 Table 2.
Page 37 RM0390 List of tables Table 49. Non-multiplexed I/O NOR Flash memory ........260 Table 50.
Page 38 List of tables RM0390 Table 101. Data storage in monochrome progressive video format ......433 Table 102.
Page 39 RM0390 List of tables oversampling by 8............810 Table 149.
Page 40 List of tables RM0390 Table 192. Performance move field ..........1004 Table 193.
Page 41 RM0390 List of tables Table 244. SW-DP registers ............1295 ®...
Page 42 List of figures RM0390 List of figures Figure 1. System architecture for STM32F446xx devices ....... . . 54 Figure 2.
Page 43 RM0390 List of figures Figure 49. Wait configuration waveforms..........282 Figure 50.
Page 44 List of figures RM0390 Figure 101. DCMI block diagram ........... . 424 Figure 102.
Page 45 RM0390 List of figures Figure 151. Example of counter operation in encoder interface mode......487 Figure 152. Example of encoder interface mode with TI1FP1 polarity inverted....487 Figure 153.
Page 46 List of figures RM0390 Figure 203. Triggering timer 1 and 2 with timer 1 TI1 input ....... . . 558 Figure 204.
Page 47 RM0390 List of figures Figure 251. Transfer sequence flowchart for slave receiver with NOSTRETCH=0 ....710 Figure 252. Transfer sequence flowchart for slave receiver with NOSTRETCH=1 ....711 Figure 253.
Page 48 List of figures RM0390 Figure 303. USART interrupt mapping diagram ......... 835 Figure 304.
Page 49 RM0390 List of figures Figure 352. S/PDIF overrun error when RXSTEO = 1 ........913 Figure 353.
Page 50 List of figures RM0390 Figure 403. USB_FS peripheral-only connection........1088 Figure 404.
Page 51: Documentation Conventions
RM0390 Documentation conventions Documentation conventions List of abbreviations for registers The following abbreviations are used in register descriptions: read/write (rw) Software can read and write to this bit. read-only (r) Software can only read this bit. write-only (w) Software can only write to this bit. Reading this bit returns the reset value. read/clear write0 (rc_w0) Software can read as well as clear this bit by writing 0.
Page 52: Glossary
Documentation conventions RM0390 Glossary This section gives a brief definition of acronyms and abbreviations used in this document: • The CPU core integrates two debug ports: – JTAG debug port (JTAG-DP) provides a 5-pin standard interface based on the Joint Test Action Group (JTAG) protocol. –...
Page 53: Memory And Bus Architecture
RM0390 Memory and bus architecture Memory and bus architecture System architecture In STM32F446xx, the main system consists of 32-bit multilayer AHB bus matrix that interconnects: • Seven masters: ® – Cortex -M4 with FPU core I-bus, D-bus and S-bus – DMA1 memory bus –...
Page 54: I-Bus
Memory and bus architecture RM0390 Figure 1. System architecture for STM32F446xx devices 2.1.1 I-bus ® This bus connects the Instruction bus of the Cortex -M4 with FPU core to the BusMatrix. This bus is used by the core to fetch instructions. The target of this bus is a memory containing code (internal Flash memory/SRAM or external memories through the FMC).
Page 55: Dma Peripheral Bus
RM0390 Memory and bus architecture internal Flash, internal SRAMs (SRAM1, SRAM2) and external memories through the FMC and QUADSPI. 2.1.5 DMA peripheral bus This bus connects the DMA peripheral master bus interface to the BusMatrix. This bus is used by the DMA to access AHB peripherals or to perform memory-to-memory transfers. The targets of this bus are the AHB and APB peripherals plus data memories: internal Flash, internal SRAMs (SRAM1, SRAM2) and external memories through the FMC and the QUADSPI.
Page 56: Memory Organization
RM0390 Memory organization 2.2.1 Introduction Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space. The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word’s least significant byte and the highest numbered byte the most significant.
Page 57: Table 1. Stm32F446Xx Register Boundary Addresses
RM0390 All the memory map areas that are not allocated to on-chip memories and peripherals are considered “Reserved”. For the detailed mapping of available memory and register areas. The following table gives the boundary addresses of the peripherals available in the devices.
Page 58 RM0390 Table 1. STM32F446xx register boundary addresses (continued) Boundary address Peripheral Register map 0x4001 3000 - 0x4001 33FF SPI1 Section 26.7.10: SPI register map on page 896 0x4001 2C00 - 0x4001 2FFF SDMMC Section 29.8.16: SDIO register map on page 1030 0x4001 2000 - 0x4001 23FF ADC1 - ADC2 - ADC3 Section 13.13.18: ADC register map on page 398...
Page 59 RM0390 Table 1. STM32F446xx register boundary addresses (continued) Boundary address Peripheral Register map 0x4000 7400 - 0x4000 77FF Section 14.5.15: DAC register map on page 422 0x4000 7000 - 0x4000 73FF Section 5.5: PWR register map on page 115 Section 32.7.7: HDMI-CEC register map on 0x4000 6C00 - 0x4000 6FFF HDMI-CEC page 1283...
Page 60: Embedded Sram
RM0390 2.2.3 Embedded SRAM The STM32F446xx feature 4 Kbytes of backup SRAM (see Section 5.1.2: Battery backup domain) plus 128 Kbytes of system SRAM. The embedded SRAM can be accessed as bytes, half-words (16 bits) or full words (32 bits). Read and write operations are performed at CPU speed with 0 wait state.
Page 61: Boot Configuration
RM0390 A mapping formula shows how to reference each word in the alias region to a corresponding bit in the bit-band region. The mapping formula is: bit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number × 4) where: – bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit –...
Page 62: Table 3. Memory Mapping Vs. Boot Mode/Physical Remap In Stm32F446Xx
CAN and USB OTG FS require an external clock (HSE) multiple of 1 MHz (ranging from 4 to 26 MHz). The embedded bootloader code is located in system memory. It is programmed by ST during production. For additional information, refer to application note AN2606.
Page 63 RM0390 Table 3. Memory mapping vs. Boot mode/physical remap in STM32F446xx (continued) Boot/Remap in Boot/Remap in Boot/Remap in Addresses Remap in FMC main Flash memory embedded SRAM System memory FMC bank 1 0x0400 0000 - 0x07FF FFFF Reserved Reserved Reserved NOR/PSRAM 2 (128 MB Aliased) FMC bank 1...
Page 64: Embedded Flash Memory Interface
Embedded Flash memory interface RM0390 Embedded Flash memory interface Introduction The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms. The Flash memory interface accelerates code execution with a system of instruction prefetch and cache lines.
Page 65: Embedded Flash Memory
RM0390 Embedded Flash memory interface Embedded Flash memory The Flash memory has the following main features: • Capacity up to 512 KBytes • 128 bits wide data read • Byte, half-word, word and double word write • Sector and mass erase •...
Page 66: Read Interface
Embedded Flash memory interface RM0390 Read interface 3.4.1 Relation between CPU clock frequency and Flash memory read time To correctly read data from Flash memory, the number of wait states (LATENCY) must be correctly programmed in the Flash access control register (FLASH_ACR) according to the frequency of the CPU clock (HCLK) and the supply voltage of the device.
Page 67: Adaptive Real-Time Memory Accelerator (Art Accelerator™)
RM0390 Embedded Flash memory interface Increasing the CPU frequency Program the new number of wait states to the LATENCY bits in the FLASH_ACR register Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register Modify the CPU clock source by writing the SW bits in the RCC_CFGR register If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR...
Page 68: Figure 4. Sequential 32-Bit Instruction Execution
Embedded Flash memory interface RM0390 Figure 4 shows the execution of sequential 32-bit instructions with and without prefetch when 3 WSs are needed to access the Flash memory. Figure 4. Sequential 32-bit instruction execution 68/1328 RM0390 Rev 4...
Page 69: Erase And Program Operations
RM0390 Embedded Flash memory interface When the code is not sequential (branch), the instruction may not be present in the currently used instruction line or in the prefetched instruction line. In this case (miss), the penalty in terms of number of cycles is at least equal to the number of wait states. Instruction cache memory To limit the time lost due to jumps, it is possible to retain 64 lines of 128 bits in an instruction cache memory.
Page 70: Program/Erase Parallelism
Embedded Flash memory interface RM0390 Note: The FLASH_CR register is not accessible in write mode when the BSY bit in the FLASH_SR register is set. Any attempt to write to it with the BSY bit set will cause the AHB bus to stall until the BSY bit is cleared.
Page 71: Programming
RM0390 Embedded Flash memory interface Mass Erase To perform Mass Erase, the following sequence is recommended: Check that no Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register Set the MER bit in the FLASH_CR register Set the STRT bit in the FLASH_CR register Wait for the BSY bit to be cleared.
Page 72: Interrupts
Embedded Flash memory interface RM0390 If an erase operation in Flash memory also concerns data in the data or instruction cache, you have to make sure that these data are rewritten before they are accessed during code execution. If this cannot be done safely, it is recommended to flush the caches by setting the DCRST and ICRST bits in the FLASH_CR register.
Page 73: Table 9. Description Of The Option Bytes
RM0390 Embedded Flash memory interface Table 9. Description of the option bytes Option bytes (word, address 0x1FFF C000) RDP: Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0xAA: Level 0, no protection Bits 15:8 0xCC: Level 2, chip protection (debug and boot from RAM features disabled) Others: Level 1, read protection of memories (debug features limited)
Page 74: Programming User Option Bytes
Embedded Flash memory interface RM0390 Table 9. Description of the option bytes (continued) nWRP: Flash memory write protection option bytes Sectors 0 to 7 can be write protected. nWRPi If SPRMOD is reset (default value) : 0: Write protection active on sector i. Bits 7:0 1: Write protection not active on sector i.
Page 75 RM0390 Embedded Flash memory interface Flash memory are possible in all boot configurations (Flash user boot, debug or boot from RAM). • Level 1: read protection enabled It is the default read protection level after option byte erase. The read protection Level 1 is activated by writing any value (except for 0xAA and 0xCC used to set Level 0 and Level 2, respectively) into the RDP option byte.
Page 76: Table 10. Access Versus Read Protection Level
Embedded Flash memory interface RM0390 Table 10. Access versus read protection level Debug features, Boot from RAM or Booting from Flash memory Protection from System memory bootloader Memory area Level Read Write Erase Read Write Erase Level 1 Main Flash Memory Level 2 Level 1 Option Bytes...
Page 77: Write Protections
RM0390 Embedded Flash memory interface Figure 5 shows how to go from one RDP level to another. Figure 5. RDP levels 3.6.4 Write protections Up to 7 user sectors in Flash memory can be protected against unwanted write operations due to loss of program counter contexts. When the non-write protection nWRPi bit (0 ≤ i ≤ 7) in the FLASH_OPTCR or FLASH_OPTCR1 registers is low, the corresponding sector cannot be erased or programmed.
Page 78: Proprietary Code Readout Protection (Pcrop)
Embedded Flash memory interface RM0390 If an erase operation is requested, the WRPERR bit is set when: • Mass, bank, sector erase are configured (MER and SER = 1) • A sector erase is requested and the Sector Number SNB field is not valid •...
Page 79: One-Time Programmable Bytes
RM0390 Embedded Flash memory interface Figure 6. PCROP levels The deactivation of the SPRMOD and/or the unprotection of PCROPed user sectors can only occur when, at the same time, the RDP level changes from 1 to 0. If this condition is not respected, the user option byte modification is canceled and the write error WRPERR flag is set.
Page 80: Flash Interface Registers
Embedded Flash memory interface RM0390 Table 11. OTP area organization (continued) Block [128:96] [95:64] [63:32] [31:0] Address byte 0 OTP15 OTP15 OTP15 OTP15 0x1FFF 79E0 OTP15 OTP15 OTP15 OTP15 0x1FFF 79F0 LOCKB15 ... LOCKB11 ... LOCKB7 ... LOCKB3 ... Lock block 0x1FFF 7A00 LOCKB12 LOCKB8...
Page 81: Flash Key Register (Flash_Keyr)
RM0390 Embedded Flash memory interface Bit 9 ICEN: Instruction cache enable 0: Instruction cache is disabled 1: Instruction cache is enabled Bit 8 PRFTEN: Prefetch enable 0: Prefetch is disabled 1: Prefetch is enabled Bits 7:4 Reserved, must be kept cleared. Bits 3:0 LATENCY: Latency These bits represent the ratio of the CPU clock period to the Flash memory access time.
Page 82: Flash Status Register (Flash_Sr)
Embedded Flash memory interface RM0390 OPTKEYR[31:16 OPTKEYR[15:0] Bits 31:0 OPTKEYR: Option byte key The following values must be programmed consecutively to unlock the FLASH_OPTCR register and allow programming it: OPTKEY1 = 0x08192A3B OPTKEY2 = 0x4C5D6E7F 3.8.4 Flash status register (FLASH_SR) The Flash status register gives information on ongoing program and erase operations.
Page 83: Flash Control Register (Flash_Cr)
RM0390 Embedded Flash memory interface Bit 5 PGAERR: Programming alignment error Set by hardware when the data to program cannot be contained in the same 128-bit Flash memory row. Cleared by writing 1. Bit 4 WRPERR: Write protection error Set by hardware when an address to be erased/programmed belongs to a write-protected part of the Flash memory.
Page 84 Embedded Flash memory interface RM0390 Bit 24 EOPIE: End of operation interrupt enable This bit enables the interrupt generation when the EOP bit in the FLASH_SR register goes to 1. 0: Interrupt generation disabled 1: Interrupt generation enabled Bits 23:17 Reserved, must be kept cleared. Bit 16 STRT: Start This bit triggers an erase operation when set.
Page 85: Flash Option Control Register (Flash_Optcr)
RM0390 Embedded Flash memory interface 3.8.6 Flash option control register (FLASH_OPTCR) The FLASH_OPTCR register is used to modify the user option bytes. Address offset: 0x14 Reset value: 0x0FFF AAED. The option bits are loaded with values from Flash memory at reset release.
Page 86 Embedded Flash memory interface RM0390 Bits 7:5 USER: User option bytes These bits contain the value of the user option byte after reset. They can be written to program a new user option byte value into Flash memory. Bit 7: nRST_STDBY Bit 6: nRST_STOP Bit 5: WDG_SW Note: When changing the WDG mode from hardware to software or from software to...
Page 87: Flash Interface Register Map
RM0390 Embedded Flash memory interface 3.8.7 Flash interface register map Table 12. Flash register map and reset value Offset Register FLASH_ACR LATENCY 0x00 Reset value FLASH_KEYR KEY[31:16] KEY[15:0] 0x04 Reset value 0 0 0 FLASH_ OPTKEYR[31:16] OPTKEYR[15:0] OPTKEYR 0x08 Reset value 0 0 0 FLASH_SR 0x0C...
Page 88: Crc Calculation Unit
CRC calculation unit RM0390 CRC calculation unit CRC introduction The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity.
Page 89: Crc Registers
RM0390 CRC calculation unit Each write operation into the data register creates a combination of the previous CRC value and the new one (CRC computation is done on the whole 32-bit data word, and not byte per byte). The write operation is stalled until the end of the CRC computation, thus allowing back-to- back write accesses or consecutive write and read accesses.
Page 90: Independent Data Register (Crc_Idr)
CRC calculation unit RM0390 4.4.2 Independent data register (CRC_IDR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. IDR[7:0] Bits 31:8 Reserved, must be kept at reset value.
Page 91: Crc Register Map
RM0390 CRC calculation unit 4.4.4 CRC register map Table 13. CRC calculation unit register map and reset values Offset Register CRC_DR Data register 0x00 Reset value 0xFFFF FFFF CRC_IDR Independent data register 0x04 Reset value 0x0000 CRC_CR 0x08 Reset value RM0390 Rev 4 91/1328...
Page 92: Power Controller (Pwr)
Power controller (PWR) RM0390 Power controller (PWR) Power supplies The device requires a 1.8 to 3.6 V operating voltage supply (V ). An embedded linear voltage regulator is used to supply the internal 1.2 V digital power. The real-time clock (RTC), the RTC backup registers, and the backup SRAM (BKP SRAM) can be powered from the V voltage when the main V supply is powered off.
Page 93: Independent A/D Converter Supply And Reference Voltage
RM0390 Power controller (PWR) 5.1.1 Independent A/D converter supply and reference voltage To improve conversion accuracy, the ADC has an independent power supply which can be separately filtered and shielded from noise on the PCB. • The ADC voltage supply input is available on a separate V pin.
Page 94 Power controller (PWR) RM0390 Note: Due to the fact that the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is restricted: the speed has to be limited to 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g.
Page 95: Voltage Regulator
RM0390 Power controller (PWR) regulator can be ON or OFF depending whether the application needs the backup SRAM function in Standby and V modes or not. The power-down of this regulator is controlled by a dedicated bit, the BRE control bit of the PWR_CSR register. The backup SRAM is not mass erased by a tamper event.
Page 96: Table 14. Voltage Regulator Configuration Mode Versus Device Operating Mode
Power controller (PWR) RM0390 scale 3 is automatically selected.(see Section 5.4.1: PWR power control register (PWR_CR). 2 operating modes are available: – Normal mode: The CPU and core logic operate at maximum frequency at a given voltage scaling (scale 1, scale 2 or scale 3) –...
Page 97 RM0390 Power controller (PWR) Entering Over-drive mode It is recommended to enter Over-drive mode when the application is not running critical tasks and when the system clock source is either HSI or HSE. To optimize the configuration time, enable the Over-drive mode during the PLL lock phase. To enter Over-drive mode, follow the sequence below: Select HSI or HSE as system clock.
Page 98: Power Supply Supervisor
Power controller (PWR) RM0390 Example of sequence 2: Select HSI or HSE as system clock source. Disable the peripheral clocks that are not generated by the System PLL (I2S clock, SAI1 and SAI2 clocks, USB_48MHz clock,..). Reset the ODSW bit in the PWR_CR register to switch back the voltage regulator to Normal mode.
Page 99: Brownout Reset (Bor)
RM0390 Power controller (PWR) 5.2.2 Brownout reset (BOR) During power on, the Brownout reset (BOR) keeps the device under reset until the supply voltage reaches the specified V threshold. is configured through device option bytes. By default, BOR is off. 3 programmable threshold levels can be selected: •...
Page 100: Low-Power Modes
Power controller (PWR) RM0390 internally connected to the EXTI line16 and can generate an interrupt if enabled through the EXTI registers. The PVD output interrupt can be generated when V drops below the PVD threshold and/or when V rises above the PVD threshold depending on EXTI line16 rising/falling edge configuration.
Page 101: Slowing Down System Clocks
RM0390 Power controller (PWR) Table 15. Low-power mode summary Effect on Effect on 1.2 V Mode name Entry Wakeup domain Voltage regulator domain clocks clocks WFI or Return CPU CLK OFF Sleep Any interrupt from ISR no effect on (Sleep now other clocks or None or Sleep-on-...
Page 102: Low Power Mode
Power controller (PWR) RM0390 5.3.3 Low power mode Entering low power mode Low power modes are entered by the MCU executing the WFI (Wait For Interrupt), or WFE ® (Wait For Event) instructions, or when the SLEEPONEXIT bit in the Cortex -M4 System Control register is set on Return from ISR.
Page 103: Stop Mode
RM0390 Power controller (PWR) Exiting Sleep mode The Sleep mode is exited according to Exiting low power mode. Refer to Table 16 for details on how to exit the Sleep mode. Table 16. Sleep-now entry and exit Sleep-now mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: –...
Page 104: Table 17. Stop Operating Modes
Power controller (PWR) RM0390 Table 17. Stop operating modes UDEN[1:0] MRUDS LPUDS LPDS FPDS Voltage Regulator Mode Wakeup latency bits STOP MR HSI RC startup time (Main Regulator) HSI RC startup time + STOP MR- FPD Flash wakeup time from power- down mode HSI RC startup time + Normal...
Page 105 RM0390 Power controller (PWR) If the Over-drive mode was enabled before entering Stop mode, it is automatically disabled during when the Stop mode is activated. In Stop mode, the following features can be selected by programming individual control bits: • Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option.
Page 106: Standby Mode
Power controller (PWR) RM0390 Table 18. Stop mode entry and exit for STM32F446xx Stop mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: ® – Set SLEEPDEEP bit in Cortex -M4 with FPU System Control register – Clear PDDS bit in Power Control register (PWR_CR) –...
Page 107: Table 19. Standby Mode Entry And Exit
RM0390 Power controller (PWR) Refer to Table 19 for more details on how to enter Standby mode. In Standby mode, the following features can be selected by programming individual control bits: • Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option.
Page 108: Programming The Rtc Alternate Functions To Wake Up The Device From The Stop And Standby Modes
Power controller (PWR) RM0390 I/O states in Standby mode In Standby mode, all I/O pins are high impedance except for: • Reset pad (still available) • RTC_AF1 pin (PC13) if configured for tamper, time stamp, RTC Alarm out, or RTC clock calibration out •...
Page 109 RM0390 Power controller (PWR) RTC alternate functions to wake up the device from the Stop mode • To wake up the device from the Stop mode with an RTC alarm event, it is necessary to: Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt or Event modes) Enable the RTC Alarm Interrupt in the RTC_CR register Configure the RTC to generate the RTC alarm...
Page 110 Power controller (PWR) RM0390 Safe RTC alternate function wakeup flag clearing sequence If the selected RTC alternate function is set before the PWR wakeup flag (WUTF) is cleared, it will not be detected on the next event as detection is made once on the rising edge. To avoid bouncing on the pins onto which the RTC alternate functions are mapped, and exit correctly from the Stop and Standby modes, it is recommended to follow the sequence below before entering the Standby mode:...
Page 111: Power Control Registers
RM0390 Power controller (PWR) Power control registers 5.4.1 PWR power control register (PWR_CR) Address offset: 0x00 Reset value: 0x0000 C000 (reset by wakeup from Standby mode) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FISSR FMSSR UDEN[1:0] ODSWEN ODEN VOS[1:0] ADCDC1...
Page 112 Power controller (PWR) RM0390 Bit 16 ODEN: Over-drive enable This bit is set by software. It is cleared automatically by hardware after exiting from Stop mode. It is used to enabled the Over-drive mode in order to reach a higher frequency. To set or reset the ODEN bit, the HSI or HSE must be selected as system clock.
Page 113: Pwr Power Control/Status Register (Pwr_Csr)
RM0390 Power controller (PWR) Bits 7:5 PLS[2:0]: PVD level selection These bits are written by software to select the voltage threshold detected by the Power Voltage Detector 000: 2.0 V 001: 2.1 V 010: 2.3 V 011: 2.5 V 100: 2.6 V 101: 2.7 V 110: 2.8 V 111: 2.9 V...
Page 114 Power controller (PWR) RM0390 Bits 31:20 Reserved, must be kept at reset value. Bits 19:18 UDRDY[1:0]: Under-drive ready flag These bits are set by hardware when MCU entered stop Under-drive mode and exited. When the under-drive mode is enabled, these bits are not set as long as the MCU has not entered stop mode yet.
Page 115: Pwr Register Map
RM0390 Power controller (PWR) Bit 3 BRR: Backup regulator ready Set by hardware to indicate that the Backup Regulator is ready. 0: Backup Regulator not ready 1: Backup Regulator ready Note: This bit is not reset when the device wakes up from Standby mode or by a system reset or power reset.
Page 116: Reset And Clock Control (Rcc)
Reset and clock control (RCC) RM0390 Reset and clock control (RCC) Reset There are three types of reset, defined as system Reset, power Reset and backup domain Reset. 6.1.1 System reset A system reset sets all registers to their reset values except the reset flags in the clock controller CSR register and the registers in the Backup domain (see Figure 13).
Page 117: Backup Domain Reset
RM0390 Reset and clock control (RCC) These sources act on the NRST pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at address in the memory map. 0x0000_0004 The system reset signal provided to the device is output on the NRST pin. The pulse generator guarantees a minimum reset pulse duration of 20 µs for each internal reset source.
Page 118: Figure 14. Clock Tree
Reset and clock control (RCC) RM0390 Figure 14. Clock tree 1. For full details about the internal and external clock source characteristics, refer to the Electrical characteristics section in the device datasheet. 2. When TIMPRE bit of the RCC_DCKCFGR register is reset, if APBx prescaler is 1, then TIMxCLK = PCLKx, 118/1328 RM0390 Rev 4...
Page 119 RM0390 Reset and clock control (RCC) otherwise TIMxCLK = 2x PCLKx. 3. When TIMPRE bit in the RCC_DCKCFGR register is set, if APBx prescaler is 1,2 or 4, then TIMxCLK = HCLK, otherwise TIMxCLK = 4x PCLKx. The clock controller provides a high degree of flexibility to the application in the choice of the external crystal or the oscillator to run the core and peripherals at the highest frequency and, guarantee the appropriate frequency for peripherals that need a specific clock like USB OTG FS and HS, I2S, SAI, and SDIO.
Page 120: Hse Clock
Reset and clock control (RCC) RM0390 The RCC feeds the external clock of the Cortex System Timer (SysTick) with the AHB clock (HCLK) divided by 8. The SysTick can work either with this clock or with the Cortex clock (HCLK), configurable in the SysTick control and status register. ®...
Page 121: Hsi Clock
Calibration RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at T = 25 °C. After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the...
Page 122: Lse Clock
Reset and clock control (RCC) RM0390 The PLLI2S and PLLSAI use the same input clock as PLL (PLLSRC bit is common to both PLLs). However, the PLLI2S and PLLSAI have dedicated enable/disable and division factors (M, N, P, R and R) configuration bits. Once the PLLI2S and PLLSAI are enabled, the configuration parameters cannot be changed.
Page 123: Clock Security System (Css)
RM0390 Reset and clock control (RCC) control register (RCC_CR) indicate which clock(s) is (are) ready and which clock is currently used as the system clock. 6.2.7 Clock security system (CSS) The clock security system can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.
Page 124: Watchdog Clock
Reset and clock control (RCC) RM0390 The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not. As a consequence: • If LSE is selected as the RTC clock: – The RTC continues to work even if the V supply is switched off, provided the supply is maintained.
Page 125: Internal/External Clock Measurement Using Tim5/Tim11
RM0390 Reset and clock control (RCC) The selected clock to output onto MCO must not exceed 100 MHz (the maximum I/O speed). 6.2.11 Internal/external clock measurement using TIM5/TIM11 It is possible to indirectly measure the frequencies of all on-board clock source generators by means of the input capture of TIM5 channel4 and TIM11 channel1 as shown in Figure 16 Figure...
Page 126: Figure 17. Frequency Measurement With Tim11 In Input Capture Mode
Reset and clock control (RCC) RM0390 Internal/external clock measurement using TIM11 channel1 TIM11 has an input multiplexer which allows choosing whether the input capture is triggered by the I/O, by SPDIF-Rx Frame Synch or by an internal clock. This selection is performed through TI1_RMP [1:0] bits in the TIM11_OR register.
Page 127: Rcc Registers
RM0390 Reset and clock control (RCC) RCC registers Refer to for a list of abbreviations used in Section 1.1: List of abbreviations for registers register descriptions. 6.3.1 RCC clock control register (RCC_CR) Address offset: 0x00 Reset value: 0x0000 XX83 where X is undefined. Access: no wait state, word, half-word and byte access PLLSAI PLLSAI...
Page 128 Reset and clock control (RCC) RM0390 Bits 23:20 Reserved, must be kept at reset value. Bit 19 CSSON: Clock security system enable Set and cleared by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if an oscillator failure is detected.
Page 129: Rcc Pll Configuration Register (Rcc_Pllcfgr)
RM0390 Reset and clock control (RCC) 6.3.2 RCC PLL configuration register (RCC_PLLCFGR) Address offset: 0x04 Reset value: 0x2400 3010 Access: no wait state, word, half-word and byte access. This register is used to configure the PLL clock outputs according to the formulas: •...
Page 130 Reset and clock control (RCC) RM0390 Bits 21:18 Reserved, must be kept at reset value. Bits 17:16 PLLP[1:0]: Main PLL (PLL) division factor for main system clock Set and cleared by software to control the frequency of the general PLL output clock. These bits can be written only if PLL is disabled.
Page 131: Rcc Clock Configuration Register (Rcc_Cfgr)
RM0390 Reset and clock control (RCC) 6.3.3 RCC clock configuration register (RCC_CFGR) Address offset: 0x08 Reset value: 0x0000 0000 Access: 0 ≤ wait state ≤ 2, word, half-word and byte access 1 or 2 wait states inserted only if the access occurs during a clock source switch. MCO2[1:0] MCO2 PRE[2:0] MCO1 PRE[2:0]...
Page 132 Reset and clock control (RCC) RM0390 Bits 20:16 RTCPRE: HSE division factor for RTC clock Set and cleared by software to divide the HSE clock input clock to generate a 1 MHz clock for RTC. Caution: The software has to set these bits correctly to ensure that the clock supplied to the RTC is 1 MHz.
Page 133: Rcc Clock Interrupt Register (Rcc_Cir)
RM0390 Reset and clock control (RCC) Bits 7:4 HPRE: AHB prescaler Set and cleared by software to control AHB clock division factor. Caution: The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after HPRE write. Caution: The AHB clock frequency must be at least 25 MHz when the Ethernet is used.
Page 134 Reset and clock control (RCC) RM0390 Bits 31:24 Reserved, must be kept at reset value. Bit 23 CSSC: Clock security system interrupt clear This bit is set by software to clear the CSSF flag. 0: No effect 1: Clear CSSF flag Bit 22 PLLSAIRDYC: PLLSAI Ready Interrupt Clear This bit is set by software to clear PLLSAIRDYF flag.
Page 135 RM0390 Reset and clock control (RCC) Bit 12 PLLRDYIE: Main PLL (PLL) ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by PLL lock. 0: PLL lock interrupt disabled 1: PLL lock interrupt enabled Bit 11 HSERDYIE: HSE ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization.
Page 136: Rcc Ahb1 Peripheral Reset Register (Rcc_Ahb1Rstr)
Reset and clock control (RCC) RM0390 Bit 3 HSERDYF: HSE ready interrupt flag This bit is set by hardware when External High Speed clock becomes stable and HSERDYDIE is set. It is cleared by software by setting the HSERDYC bit. 0: No clock ready interrupt caused by the HSE oscillator 1: Clock ready interrupt caused by the HSE oscillator Bit 2 HSIRDYF: HSI ready interrupt flag...
Page 137 RM0390 Reset and clock control (RCC) Bit 22 DMA2RST: DMA2 reset This bit is set and cleared by software. 0: does not reset DMA2 1: resets DMA2 Bit 21 DMA1RST: DMA2 reset This bit is set and cleared by software. 0: does not reset DMA2 1: resets DMA2 Bits 20:13 Reserved, must be kept at reset value.
Page 138: Rcc Ahb2 Peripheral Reset Register (Rcc_Ahb2Rstr)
Reset and clock control (RCC) RM0390 6.3.6 RCC AHB2 peripheral reset register (RCC_AHB2RSTR) Address offset: 0x14 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 139: Rcc Apb1 Peripheral Reset Register (Rcc_Apb1Rstr)
RM0390 Reset and clock control (RCC) Bit 0 FMCRST: Flexible memory controller module reset Set and cleared by software. 0: does not reset the FMC module 1: resets the FMC module 6.3.8 RCC APB1 peripheral reset register (RCC_APB1RSTR) Address offset: 0x20 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access.
Page 140 Reset and clock control (RCC) RM0390 Bit 23 I2C3RST: I2C3 reset Set and cleared by software. 0: does not reset I2C3 1: resets I2C3 Bit 22 I2C2RST: I2C2 reset Set and cleared by software. 0: does not reset I2C2 1: resets I2C2 Bit 21 I2C1RST: I2C1 reset Set and cleared by software.
Page 141 RM0390 Reset and clock control (RCC) Bit 8 TIM14RST: TIM14 reset Set and cleared by software. 0: does not reset TIM14 1: resets TIM14 Bit 7 TIM13RST: TIM13 reset Set and cleared by software. 0: does not reset TIM13 1: resets TIM13 Bit 6 TIM12RST: TIM12 reset Set and cleared by software.
Page 142: Rcc Apb2 Peripheral Reset Register (Rcc_Apb2Rstr)
Reset and clock control (RCC) RM0390 6.3.9 RCC APB2 peripheral reset register (RCC_APB2RSTR) Address offset: 0x24 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. SAI2 SAI1 TIM11 TIM10 TIM9 Res. Res. Res. Res. Res. Res. Res.
Page 143 RM0390 Reset and clock control (RCC) Bit 12 SPI1RST: SPI1 reset This bit is set and cleared by software. 0: does not reset SPI1 1: resets SPI1 Bit 11 SDIORST: SDIO reset This bit is set and cleared by software. 0: does not reset the SDIO module 1: resets the SDIO module Bits 10:9 Reserved, must be kept at reset value.
Page 144: Rcc Ahb1 Peripheral Clock Enable Register (Rcc_Ahb1Enr)
Reset and clock control (RCC) RM0390 6.3.10 RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) Address offset: 0x30 Reset value: 0x0010 0000 Access: no wait state, word, half-word and byte access. OTGHS OTGHS DMA2 DMA1 Res. Res. Res. Res. Res. Res. Res.
Page 145: Rcc Ahb2 Peripheral Clock Enable Register (Rcc_Ahb2Enr)
RM0390 Reset and clock control (RCC) Bit 7 GPIOHEN: IO port H clock enable This bit is set and cleared by software. 0: IO port H clock disabled 1: IO port H clock enabled Bit 6 GPIOGEN: IO port G clock enable This bit is set and cleared by software.
Page 146: Rcc Ahb3 Peripheral Clock Enable Register (Rcc_Ahb3Enr)
Reset and clock control (RCC) RM0390 Bits 31:8 Reserved, must be kept at reset value. Bit 7 OTGFSEN: USB OTG FS clock enable This bit is set and cleared by software. 0: USB OTG FS clock disabled 1: USB OTG FS clock enabled Bits 6:1 Reserved, must be kept at reset value.
Page 147 RM0390 Reset and clock control (RCC) CAN2 CAN1 FMPI2C1 I2C3 I2C2 I2C1 UART5 UART4 USART3 USART2 SPDIFRX Res. Res. SPI3 SPI2 WWDG TIM14 TIM13 TIM12 TIM7 TIM6 TIM5 TIM4 TIM3 TIM2 Res. Res. Res. Res. Bits 31:30 Reserved, must be kept at reset value. Bit 29 DACEN: DAC interface clock enable This bit is set and cleared by software.
Page 148 Reset and clock control (RCC) RM0390 Bit 20 UART5EN: UART5 clock enable This bit is set and cleared by software. 0: UART5 clock disabled 1: UART5 clock enabled Bit 19 UART4EN: UART4 clock enable This bit is set and cleared by software. 0: UART4 clock disabled 1: UART4 clock enabled Bit 18 USART3EN: USART3 clock enable...
Page 149: Rcc Apb2 Peripheral Clock Enable Register (Rcc_Apb2Enr)
RM0390 Reset and clock control (RCC) Bit 5 TIM7EN: TIM7 clock enable This bit is set and cleared by software. 0: TIM7 clock disabled 1: TIM7 clock enabled Bit 4 TIM6EN: TIM6 clock enable This bit is set and cleared by software. 0: TIM6 clock disabled 1: TIM6 clock enabled Bit 3 TIM5EN: TIM5 clock enable...
Page 150 Reset and clock control (RCC) RM0390 Bits 31:24 Reserved, must be kept at reset value. Bit 23 SAI2EN: SAI2 clock enable This bit is set and cleared by software. 0: SAI2 clock disabled 1: SAI2 clock enabled Bit 22 SAI1EN: SAI1 clock enable This bit is set and cleared by software.
Page 151: Rcc Ahb1 Peripheral Clock Enable In Low Power Mode Register (Rcc_Ahb1Lpenr)
RM0390 Reset and clock control (RCC) Bit 9 ADC2EN: ADC2 clock enable This bit is set and cleared by software. 0: ADC2 clock disabled 1: ADC2 clock enabled Bit 8 ADC1EN: ADC1 clock enable This bit is set and cleared by software. 0: ADC1 clock disabled 1: ADC1 clock enabled Bits 7:6 Reserved, must be kept at reset value.
Page 152 Reset and clock control (RCC) RM0390 Bit 31 Reserved, must be kept at reset value. Bit 30 OTGHSULPILPEN: USB OTG HS ULPI clock enable during Sleep mode This bit is set and cleared by software. 0: USB OTG HS ULPI clock disabled during Sleep mode 1: USB OTG HS ULPI clock enabled during Sleep mode Bit 29 OTGHSLPEN: USB OTG HS clock enable during Sleep mode This bit is set and cleared by software.
Page 153: Rcc Ahb2 Peripheral Clock Enable In Low Power Mode Register (Rcc_Ahb2Lpenr)
RM0390 Reset and clock control (RCC) Bit 6 GPIOGLPEN: IO port G clock enable during Sleep mode This bit is set and cleared by software. 0: IO port G clock disabled during Sleep mode 1: IO port G clock enabled during Sleep mode Bit 5 GPIOFLPEN: IO port F clock enable during Sleep mode This bit is set and cleared by software.
Page 154: Rcc Ahb3 Peripheral Clock Enable In Low Power Mode Register (Rcc_Ahb3Lpenr)
Reset and clock control (RCC) RM0390 Bits 31:8 Reserved, must be kept at reset value. Bit 7 OTGFSLPEN: USB OTG FS clock enable during Sleep mode This bit is set and cleared by software. 0: USB OTG FS clock disabled during Sleep mode 1: USB OTG FS clock enabled during Sleep mode Bits 6:1 Reserved, must be kept at reset value.
Page 155 RM0390 Reset and clock control (RCC) CECLP CAN2 CAN1 FMPI2C1 I2C3 I2C2 I2C1 UART5 UART4 USART3 USART2 SPDIFRX Res. Res. LPEN LPEN LPEN LPEN LPEN LPEN LPEN LPEN LPEN LPEN LPEN LPEN LPEN SPI3 SPI2 WWDG TIM14 TIM13 TIM12 TIM7 TIM6 TIM5 TIM4...
Page 156 Reset and clock control (RCC) RM0390 Bit 20 UART5LPEN: UART5 clock enable during Sleep mode This bit is set and cleared by software. 0: UART5 clock disabled during Sleep mode 1: UART5 clock enabled during Sleep mode Bit 19 UART4LPEN: UART4 clock enable during Sleep mode This bit is set and cleared by software.
Page 157 RM0390 Reset and clock control (RCC) Bit 5 TIM7LPEN: TIM7 clock enable during Sleep mode This bit is set and cleared by software. 0: TIM7 clock disabled during Sleep mode 1: TIM7 clock enabled during Sleep mode Bit 4 TIM6LPEN: TIM6 clock enable during Sleep mode This bit is set and cleared by software.
Page 158: Rcc Apb2 Peripheral Clock Enabled In Low Power Mode Register (Rcc_Apb2Lpenr)
Reset and clock control (RCC) RM0390 6.3.19 RCC APB2 peripheral clock enabled in low power mode register (RCC_APB2LPENR) Address offset: 0x64 Reset value: 0x0x00C7 FF33 Access: no wait state, word, half-word and byte access. SAI2 SAI1 TIM11 TIM10 TIM9 Res. Res.
Page 159: Rcc Backup Domain Control Register (Rcc_Bdcr)
RM0390 Reset and clock control (RCC) Bit 13 SPI4LPEN: SPI4 clock enable during Sleep mode This bit is set and cleared by software. 0: SPI4 clock disabled during Sleep mode 1: SPI4 clock enabled during Sleep mode Bit 12 SPI1LPEN: SPI1 clock enable during Sleep mode This bit is set and cleared by software.
Page 160 Reset and clock control (RCC) RM0390 Reset value: 0x0000 0000, reset by Backup domain reset. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access Wait states are inserted in case of successive accesses to this register. The LSEON, LSEBYP, RTCSEL and RTCEN bits in the RCC Backup domain control register (RCC_BDCR) are in the Backup domain.
Page 161: Rcc Clock Control & Status Register (Rcc_Csr)
RM0390 Reset and clock control (RCC) Bit 2 LSEBYP: External low-speed oscillator bypass This bit is set and cleared by software to bypass the oscillator. This bit can be written only when the LSE clock is disabled. 0: LSE oscillator not bypassed 1: LSE oscillator bypassed Bit 1 LSERDY: External low-speed oscillator ready This bit is set and cleared by hardware to indicate when the external 32 kHz oscillator is...
Page 162: Rcc Spread Spectrum Clock Generation Register (Rcc_Sscgr)
Reset and clock control (RCC) RM0390 Bit 28 SFTRSTF: Software reset flag This bit is set by hardware when a software reset occurs. Cleared by writing to the RMVF bit. 0: No software reset occurred 1: Software reset occurred Bit 27 PORRSTF: POR/PDR reset flag This bit is set by hardware when a POR/PDR reset occurs.
Page 163: Rcc Plli2S Configuration Register (Rcc_Plli2Scfgr)
RM0390 Reset and clock control (RCC) SSCGEN SPREADSEL Res. Res. INCSTEP INCSTEP MODPER Bit 31 SSCGEN: Spread spectrum modulation enable This bit is set and cleared by software. 0: Spread spectrum modulation DISABLE. (To write after clearing CR[24]=PLLON bit) 1: Spread spectrum modulation ENABLE. (To write before setting CR[24]=PLLON bit) Bit 30 SPREADSEL: Spread Select This bit is set and cleared by software.
Page 164 Reset and clock control (RCC) RM0390 Bit 31 Reserved, must be kept at reset value. Bits 30:28 PLLI2SR[2:0]: PLLI2S division factor for I2S clocks These bits are set and cleared by software to control the I2S clock frequency. These bits should be written only if the PLLI2S is disabled.
Page 165 RM0390 Reset and clock control (RCC) Bit 15 Reserved, must be kept at reset value. Bits 14:6 PLLI2SN[8:0]: PLLI2S multiplication factor for VCO These bits are set and cleared by software to control the multiplication factor of the VCO. These bits can be written only when the PLLI2S is disabled. Only half-word and word accesses are allowed to write these bits.
Page 166: Rcc Pll Configuration Register (Rcc_Pllsaicfgr)
Reset and clock control (RCC) RM0390 6.3.24 RCC PLL configuration register (RCC_PLLSAICFGR) Address offset: 0x88 Reset value: 0x2400 3000 Access: no wait state, word, half-word and byte access. This register is used to configure the PLLSAI clock outputs according to the formulas: •...
Page 167: Rcc Dedicated Clock Configuration Register (Rcc_Dckcfgr)
RM0390 Reset and clock control (RCC) Bit 15 Reserved, must be kept at reset value. Bits 14:6 PLLSAIN: PLLSAI division factor for VCO Set and reset by software to control the multiplication factor of the VCO. These bits should be written when the PLLSAI is disabled.
Page 168 Reset and clock control (RCC) RM0390 Res. Res. Res. I2S2SRC I2S1SRC TIMPRE SAI2SRC SAI1SRC Res. Res. Res. Res. Res. Res. Res. PLLSAIDIVQ Res. Res. Res. PLLIS2DIVQ Bits 31:29 Reserved, must be kept at reset value. Bits 28:27 I2S2SRC: I2S APB2 clock source selection Set and reset by software to control the frequency of the APB2 I2S clock.
Page 169: Rcc Clocks Gated Enable Register (Ckgatenr)
RM0390 Reset and clock control (RCC) Bits 12:8 PLLSAIDIVQ[4:0]: PLLSAI division factor for SAIs clock These bits are set and reset by software to control the SAIs clock frequency. They should be written only if PLLSAI is disabled. SAI1 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ with 1 ≤ PLLSAIDIVQ ≤ 31 00000: PLLSAIDIVQ = /1 00001: PLLSAIDIVQ = /2 00010: PLLSAIDIVQ = /3...
Page 170: Rcc Dedicated Clocks Configuration Register 2 (Dckcfgr2)
Reset and clock control (RCC) RM0390 Bit 4 SRAM_CKEN: SRQAM controller clock enable 0: the clock gating is enabled 1: the clock gating is disabled, the clock is always enabled. Bit 3 SPARE_CKEN: Spare clock enable 0: the clock gating is enabled 1: the clock gating is disabled, the clock is always enabled.
Page 171 RM0390 Reset and clock control (RCC) Bits 25:24 Reserved, must be kept at reset value. Bits 23:22 FMPI2C1SEL[1:0]: I2C4 kernel clock source selection 00: APB clock selected as FMPI2C1 clock 01: System clock selected as FMPI2C1 clock 10: HSI clock selected as FMPI2C1 clock 11: APB clock selected as FMPI2C1 clock (same as “00”) Bits 21:0 Reserved, must be kept at reset value.
Page 172: Rcc Register Map
Reset and clock control (RCC) RM0390 6.3.28 RCC register map Table 21 gives the register map and reset values. Table 21. RCC register map and reset values Addr. Register offset name RCC_CR HSICAL[7:0] HSITRIM[4:0] 0x00 Reset value RCC_PLL PLLR PLLP PLLQ[3:0] PLLN[8:0] PLLM[5:0]...
Page 173 RM0390 Reset and clock control (RCC) Table 21. RCC register map and reset values (continued) Addr. Register offset name RCC_APB2 RSTR 0x24 Reset value Reserved 0x28 Reset value Reserved 0x2C Reset value RCC_ AHB1ENR 0x30 Reset value RCC_ AHB2ENR 0x34 Reset value RCC_ AHB3ENR...
Page 174 Reset and clock control (RCC) RM0390 Table 21. RCC register map and reset values (continued) Addr. Register offset name RCC_AHB1 LPENR 0x50 Reset value RCC_AHB2 LPENR 0x54 Reset value RCC_AHB3 LPENR 0x58 Reset value Reserved 0x5C Reset value RCC_APB1 LPENR 0x60 Reset value RCC_APB2...
Page 175 RM0390 Reset and clock control (RCC) Table 21. RCC register map and reset values (continued) Addr. Register offset name Reserved 0x78 Reset value Reserved 0x7C Reset value RCC_SS INCSTEP MODPER 0x80 Reset value PLLI RCC_PLLI2 PLLI2SR PLLI2SQ PLLI2SN[8:0] PLLI2SM[5:0] SCFGR [2:0] [3:0] 0x84...
Page 176: General-Purpose I/Os (Gpio)
General-purpose I/Os (GPIO) RM0390 General-purpose I/Os (GPIO) GPIO introduction Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers (GPIOx_IDR and GPIOx_ODR), a 32-bit set/reset register (GPIOx_BSRR), a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function selection register (GPIOx_AFRH and GPIOx_AFRL).
Page 177: Table 22. Port Bit Configuration Table
RM0390 General-purpose I/Os (GPIO) Figure 18 shows the basic structure of a 5 V tolerant I/O port bit, Table 22 gives the possible port bit configurations. Figure 18. Basic structure of a 5 V tolerant I/O port bit 1. V is a potential specific to 5 V tolerant I/Os and different from V DD_FT Table 22.
Page 178: General-Purpose I/O (Gpio)
General-purpose I/Os (GPIO) RM0390 Table 22. Port bit configuration table (continued) MODER(i)[1:0] OTYPER(i) OSPEEDR(i)[B:A] PUPDR(i)[1:0] I/O configuration Input Floating Input Input Reserved (input floating) Input / output Analog Reserved 1. GP = general-purpose, PP = push-pull, PU = pull-up, PD = pull-down, OD = open-drain, AF = alternate function.
Page 179: Table 23. Flexible Swj-Dp Pin Assignment
RM0390 General-purpose I/Os (GPIO) In addition to this flexible I/O multiplexing architecture, each peripheral has alternate functions mapped onto different I/O pins to optimize the number of peripherals available in smaller packages. To use an I/O in a given configuration, proceed as follows: •...
Page 180: I/O Port Control Registers
General-purpose I/Os (GPIO) RM0390 Figure 19. Selecting an alternate function on STM32F446xx 1. Configured in FS. 7.3.3 I/O port control registers Each of the GPIOs has four 32-bit memory-mapped control registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os. The 180/1328 RM0390 Rev 4...
Page 181: I/O Port Data Registers
RM0390 General-purpose I/Os (GPIO) GPIOx_MODER register is used to select the I/O direction (input, output, AF, analog). The GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type (push- pull or open-drain) and speed (the I/O speed pins are directly connected to the corresponding GPIOx_OSPEEDR register bits whatever the I/O direction).
Page 182: I/O Alternate Function Input/Output
General-purpose I/Os (GPIO) RM0390 For more details refer to LCKR register description in Section 7.4.8: GPIO port configuration lock register (GPIOx_LCKR) (x = A..H). 7.3.7 I/O alternate function input/output Two registers are provided to select one out of the sixteen alternate function inputs/outputs available for each I/O.
Page 183: Output Configuration
RM0390 General-purpose I/Os (GPIO) Figure 20. Input floating/pull up/pull down configurations 7.3.10 Output configuration When the I/O port is programmed as output: • The output buffer is enabled: – Open drain mode: A “0” in the Output register activates the N-MOS whereas a “1” in the Output register leaves the port in Hi-Z (the P-MOS is never activated) –...
Page 184: Alternate Function Configuration
General-purpose I/Os (GPIO) RM0390 Figure 21. Output configuration 7.3.11 Alternate function configuration When the I/O port is programmed as alternate function: • The output buffer can be configured as open-drain or push-pull • The output buffer is driven by the signal coming from the peripheral (transmitter enable and data) •...
Page 185: Analog Configuration
RM0390 General-purpose I/Os (GPIO) 7.3.12 Analog configuration When the I/O port is programmed as analog configuration: • The output buffer is disabled • The Schmitt trigger input is deactivated, providing zero consumption for every analog value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0). •...
Page 186: Selection Of Rtc Additional_Af1 And Rtc_Af2 Alternate Functions
General-purpose I/Os (GPIO) RM0390 7.3.15 Selection of RTC additional_AF1 and RTC_AF2 alternate functions The STM32F446xx feature two GPIO pins RTC_AF1 and RTC_AF2 that can be used for the detection of a tamper or time stamp event, or RTC_ALARM, or RTC_CALIB RTC outputs. •...
Page 187: Gpio Registers
RM0390 General-purpose I/Os (GPIO) Table 25. RTC_AF2 pin Time TAMP1INSEL TSINSEL ALARMOUTTYPE Tamper Pin configuration and function stamp TAMPER1 TIMESTAMP RTC_ALARM enabled enabled pin selection pin selection configuration TAMPER1 input floating Don’t care Don’t care TIMESTAMP and TAMPER1 input Don’t care floating TIMESTAMP input floating Don’t care...
Page 188: Gpio Port Output Type Register (Gpiox_Otyper) (X = A..h
General-purpose I/Os (GPIO) RM0390 7.4.2 GPIO port output type register (GPIOx_OTYPER) (x = A..H) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OT15 OT14 OT13 OT12 OT11 OT10...
Page 189: Gpio Port Pull-Up/Pull-Down Register (Gpiox_Pupdr) (X = A..h
RM0390 General-purpose I/Os (GPIO) 7.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A..H) Address offset: 0x0C Reset values: • 0x6400 0000 for port A • 0x0000 0100 for port B • 0x0000 0000 for other ports PUPDR15[1:0] PUPDR14[1:0] PUPDR13[1:0] PUPDR12[1:0] PUPDR11[1:0] PUPDR10[1:0] PUPDR9[1:0]...
Page 190: Gpio Port Output Data Register (Gpiox_Odr) (X = A..h
General-purpose I/Os (GPIO) RM0390 7.4.6 GPIO port output data register (GPIOx_ODR) (x = A..H) Address offset: 0x14 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ODR15 ODR14 ODR13 ODR12 ODR11 ODR10 ODR9 ODR8 ODR7...
Page 191 RM0390 General-purpose I/Os (GPIO) Note: A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this write sequence. Each lock bit freezes a specific configuration register (control and alternate function registers).
Page 192: Gpio Alternate Function Low Register (Gpiox_Afrl) (X = A
General-purpose I/Os (GPIO) RM0390 7.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A..H) Address offset: 0x20 Reset value: 0x0000 0000 AFRL7[3:0] AFRL6[3:0] AFRL5[3:0] AFRL4[3:0] AFRL3[3:0] AFRL2[3:0] AFRL1[3:0] AFRL0[3:0] Bits 31:0 AFRLy: Alternate function selection for port x bit y (y = 0..7) These bits are written by software to configure alternate function I/Os AFRLy selection: 0000: AF0...
Page 193: Gpio Register Map
RM0390 General-purpose I/Os (GPIO) 7.4.11 GPIO register map The following table gives the GPIO register map and the reset values. Table 26. GPIO register map and reset values Offset Register GPIOA_ MODER 0x00 Reset value GPIOB_ MODER 0x00 Reset value GPIOx_MODER (where x = C..H) 0x00...
Page 194 General-purpose I/Os (GPIO) RM0390 Table 26. GPIO register map and reset values (continued) Offset Register GPIOx_PUPDR (where x = C..H) 0x0C Reset value GPIOx_IDR (where x = A..H) 0x10 Reset value GPIOx_ODR (where x = A..H) 0x14 Reset value GPIOx_BSRR (where x = A..H) 0x18 Reset value...
Page 195: System Configuration Controller (Syscfg)
RM0390 System configuration controller (SYSCFG) System configuration controller (SYSCFG) The system configuration controller is mainly used to remap the memory accessible in the code area and to manage the external interrupt line connection to the GPIOs. I/O compensation cell By default the I/O compensation cell is not used. However when the I/O output buffer speed is configured in 50 MHz or 100 MHz mode, it is recommended to use the compensation cell for slew rate control on I/O t commutation to reduce the I/O noise on power...
Page 196 System configuration controller (SYSCFG) RM0390 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWP_FMC Res. Res. Res. Res. Res. Res. Res. MEM_MODE[2:0] Bits 31:12 Reserved, must be kept at reset value. Bits 11:10 SWP_FMC: FMC memory mapping swap Set and cleared by software.
Page 197: Syscfg Peripheral Mode Configuration Register (Syscfg_Pmc)
RM0390 System configuration controller (SYSCFG) 8.2.2 SYSCFG peripheral mode configuration register (SYSCFG_PMC) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ADCxDC2 Res. Res. Res. Res. Res. Res. Res. Res.
Page 198: Syscfg External Interrupt Configuration Register 2
System configuration controller (SYSCFG) RM0390 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 0 to 3) These bits are written by software to select the source input for the EXTIx external interrupt. Note: 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin...
Page 199: Syscfg External Interrupt Configuration Register 3
RM0390 System configuration controller (SYSCFG) 8.2.5 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) Address offset: 0x10 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EXTI11[3:0] EXTI10[3:0] EXTI9[3:0] EXTI8[3:0] Bits 31:16 Reserved, must be kept at reset value.
Page 200: Compensation Cell Control Register (Syscfg_Cmpcr)
System configuration controller (SYSCFG) RM0390 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 12 to 15) These bits are written by software to select the source input for the EXTIx external interrupt.
Page 201 RM0390 System configuration controller (SYSCFG) Bits 31:2 Reserved, must be kept at reset value. Bit 1 FMPI2C1_SDA Set and cleared by software. When set it forces FM+ drive capability on FMPI2C1_SDA pin selected through GPIO port mode register and GPIO alternate function selection bits Bit 0 FMPI2C1_SCL Set and cleared by software.
Page 202: Syscfg Register Maps
System configuration controller (SYSCFG) RM0390 8.2.9 SYSCFG register maps The following table summarizes the SYSCFG register map and the reset values. Table 27. SYSCFG register map and reset values Offset Register SYSCFG_ MEM_ MEMRMP MODE 0x00 Reset value SYSCFG_PMC 0x04 Reset value SYSCFG_EXTICR1 EXTI3[3:0]...
Page 203: Direct Memory Access Controller (Dma)
RM0390 Direct memory access controller (DMA) Direct memory access controller (DMA) DMA introduction Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory and between memory and memory. Data can be quickly moved by DMA without any CPU action.
Page 204 Direct memory access controller (DMA) RM0390 – DMA flow controller: the number of data items to be transferred is software- programmable from 1 to 65535 – Peripheral flow controller: the number of data items to be transferred is unknown and controlled by the source or the destination peripheral that signals the end of the transfer by hardware •...
Page 205: Dma Functional Description
RM0390 Direct memory access controller (DMA) DMA functional description 9.3.1 DMA block diagram Figure 24 shows the block diagram of a DMA. Figure 24. DMA block diagram 9.3.2 DMA overview The DMA controller performs direct memory transfer: as an AHB master, it can take the control of the AHB bus matrix to initiate AHB transactions.
Page 206: Dma Transactions
Direct memory access controller (DMA) RM0390 9.3.3 DMA transactions A DMA transaction consists of a sequence of a given number of data transfers. The number of data items to be transferred and their width (8-bit, 16-bit or 32-bit) are software- programmable.
Page 207: Table 28. Dma1 Request Mapping
RM0390 Direct memory access controller (DMA) Table 28. DMA1 request mapping Peripheral Stream 0 Stream 1 Stream 2 Stream 3 Stream 4 Stream 5 Stream 6 Stream 7 requests Channel 0 SPI3_RX SPDIFRX_DT SPI3_RX SPI2_RX SPI2_TX SPI3_TX SPDIFRX_CS SPI3_TX Channel 1 I2C1_RX I2C3_RX TIM7_UP...
Page 208: Arbiter
Direct memory access controller (DMA) RM0390 9.3.5 Arbiter An arbiter manages the 8 DMA stream requests based on their priority for each of the two AHB master ports (memory and peripheral ports) and launches the peripheral/memory access sequences. Priorities are managed in two stages: •...
Page 209: Figure 26. Peripheral-To-Memory Mode
RM0390 Direct memory access controller (DMA) When the data width (programmed in the PSIZE or MSIZE bits in the DMA_SxCR register) is a half-word or a word, respectively, the peripheral or memory address written into the DMA_SxPAR or DMA_SxM0AR/M1AR registers has to be aligned on a word or half-word address boundary, respectively.
Page 210: Figure 27. Memory-To-Peripheral Mode
Direct memory access controller (DMA) RM0390 Each time a peripheral request occurs, the contents of the FIFO are drained and stored into the destination. When the level of the FIFO is lower than or equal to the predefined threshold level, the FIFO is fully reloaded with data from the memory. The transfer stops once the DMA_SxNDTR register reaches zero, when the peripheral requests the end of transfers (in case of a peripheral flow controller) or when the EN bit in the DMA_SxCR register is cleared by software.
Page 211: Pointer Incrementation
RM0390 Direct memory access controller (DMA) The stream has access to the AHB source or destination port only if the arbitration of the corresponding stream is won. This arbitration is performed using the priority defined for each stream using the PL[1:0] bits in the DMA_SxCR register. Note: When memory-to-memory mode is used, the circular and direct modes are not allowed.
Page 212: Circular Mode
Direct memory access controller (DMA) RM0390 9.3.9 Circular mode The circular mode is available to handle circular buffers and continuous data flows (e.g. ADC scan mode). This feature can be enabled using the CIRC bit in the DMA_SxCR register. When the circular mode is activated, the number of data items to be transferred is automatically reloaded with the initial value programmed during the stream configuration phase, and the DMA requests continue to be served.
Page 213: Programmable Data Width, Packing/Unpacking, Endianness
RM0390 Direct memory access controller (DMA) memory 0 to 1 (or from 1 to 0) depending on the value of CT in the DMA_SxCR register in accordance with one of the two above conditions. For all the other modes (except the double-buffer mode), the memory address registers are write-protected as soon as the stream is enabled.
Page 214: Table 32. Packing/Unpacking And Endian Behavior (Bit Pinc = Minc = 1)
Direct memory access controller (DMA) RM0390 Table 32. Packing/unpacking and endian behavior (bit PINC = MINC = 1) Number Peripheral port address / byte lane of data Memory Memory port Peripheral memory peripheral items to transfer address / byte transfer port port PINCOS = 1...
Page 215: Single And Burst Transfers
RM0390 Direct memory access controller (DMA) 9.3.12 Single and burst transfers The DMA controller can generate single transfers or incremental burst transfers of 4, 8 or 16 beats. The size of the burst is configured by software independently for the two AHB ports by using the MBURST[1:0] and PBURST[1:0] bits in the DMA_SxCR register.
Page 216: Table 34. Fifo Threshold Configurations
Direct memory access controller (DMA) RM0390 Figure 29. FIFO structure FIFO threshold and burst configuration Caution is required when choosing the FIFO threshold (bits FTH[1:0] of the DMA_SxFCR register) and the size of the memory burst (MBURST[1:0] of the DMA_SxCR register): The content pointed by the FIFO threshold must exactly match an integer number of memory burst transfers.
Page 217 RM0390 Direct memory access controller (DMA) Table 34. FIFO threshold configurations (continued) MSIZE FIFO level MBURST = INCR4 MBURST = INCR8 MBURST = INCR16 Forbidden 1 burst of 4 beats Forbidden Half-word Forbidden Full 2 bursts of 4 beats 1 burst of 8 beats Forbidden Forbidden Word...
Page 218: Dma Transfer Completion
Direct memory access controller (DMA) RM0390 value. The software may read the DMA_SxNDTR register to determine the memory area that contains the good data (start address and last address). If the number of remaining data items in the FIFO is lower than a burst size (if the MBURST bits in DMA_SxCR register are set to configure the stream to manage burst on the AHB memory port), single transactions are generated to complete the FIFO flush.
Page 219: Dma Transfer Suspension
RM0390 Direct memory access controller (DMA) 9.3.15 DMA transfer suspension At any time, a DMA transfer can be suspended to be restarted later on or to be definitively disabled before the end of the DMA transfer. There are two cases: •...
Page 220: Summary Of The Possible Dma Configurations
Direct memory access controller (DMA) RM0390 triggered in the case of a peripheral-to-memory DMA transfer. The TCIFx flag of the corresponding stream is set in the status register to indicate the DMA completion. To know the number of data items transferred during the DMA transfer, read the DMA_SxNDTR register and apply the following formula: –...
Page 221: Stream Configuration Procedure
RM0390 Direct memory access controller (DMA) 9.3.18 Stream configuration procedure The following sequence must be followed to configure a DMA stream x (where x is the stream number): If the stream is enabled, disable it by resetting the EN bit in the DMA_SxCR register, then read this bit in order to confirm that there is no ongoing stream operation.
Page 222: Error Management
Direct memory access controller (DMA) RM0390 9.3.19 Error management The DMA controller can detect the following errors: • Transfer error: the transfer error interrupt flag (TEIFx) is set when: – a bus error occurs during a DMA read or a write access –...
Page 223: Dma Interrupts
RM0390 Direct memory access controller (DMA) DMA interrupts For each DMA stream, an interrupt can be produced on the following events: • Half-transfer reached • Transfer complete • Transfer error • FIFO error (overrun, underrun or FIFO level error) • Direct mode error Separate interrupt enable control bits are available for flexibility as shown in Table...
Page 224: Dma Registers
Direct memory access controller (DMA) RM0390 DMA registers The DMA registers have to be accessed by words (32 bits). 9.5.1 DMA low interrupt status register (DMA_LISR) Address offset: 0x00 Reset value: 0x0000 0000 Res. Res. Res. Res. TCIF3 HTIF3 TEIF3 DMEIF3 Res.
Page 225: Dma High Interrupt Status Register (Dma_Hisr)
RM0390 Direct memory access controller (DMA) 9.5.2 DMA high interrupt status register (DMA_HISR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. TCIF7 HTIF7 TEIF7 DMEIF7 Res. FEIF7 TCIF6 HTIF6 TEIF6 DMEIF6 Res. FEIF6 Res. Res. Res. Res. TCIF5 HTIF5 TEIF5...
Page 226: Dma Low Interrupt Flag Clear Register (Dma_Lifcr)
Direct memory access controller (DMA) RM0390 9.5.3 DMA low interrupt flag clear register (DMA_LIFCR) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. CTCIF3 CHTIF3 CTEIF3 CDMEIF3 Res. CFEIF3 CTCIF2 CHTIF2 CTEIF2 CDMEIF2 Res. CFEIF2 Res. Res. Res. Res.
Page 227: Dma Stream X Configuration Register (Dma_Sxcr) (X = 0
RM0390 Direct memory access controller (DMA) Bits 24, 18, 8, 2 CDMEIFx: stream x clear direct mode error interrupt flag (x = 7..4) Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_HISR register. Bits 23, 17, 7, 1 Reserved, must be kept at reset value. Bits 22, 16, 6, 0 CFEIFx: stream x clear FIFO error interrupt flag (x = 7..4) Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_HISR register.
Page 228 Direct memory access controller (DMA) RM0390 Bit 19 CT: current target (only in double-buffer mode) This bit is set and cleared by hardware. It can also be written by software. 0: current target memory is Memory 0 (addressed by the DMA_SxM0AR pointer) 1: current target memory is Memory 1 (addressed by the DMA_SxM1AR pointer) This bit can be written only if EN is ‘0’...
Page 229 RM0390 Direct memory access controller (DMA) Bit 9 PINC: peripheral increment mode This bit is set and cleared by software. 0: peripheral address pointer is fixed 1: peripheral address pointer is incremented after each data transfer (increment is done according to PSIZE) This bit is protected and can be written only if EN is ‘0’.
Page 230: Dma Stream X Number Of Data Register (Dma_Sxndtr) (X = 0
Direct memory access controller (DMA) RM0390 Bit 0 EN: stream enable / flag stream ready when read low This bit is set and cleared by software. 0: stream disabled 1: stream enabled This bit may be cleared by hardware: – on a DMA end of transfer (stream ready to be configured) –...
Page 231: Dma Stream X Peripheral Address Register (Dma_Sxpar) (X = 0
RM0390 Direct memory access controller (DMA) 9.5.7 DMA stream x peripheral address register (DMA_SxPAR) (x = 0..7) Address offset: 0x18 + 0x18 * stream number Reset value: 0x0000 0000 PAR[31:16] PAR[15:0] Bits 31:0 PAR[31:0]: peripheral address Base address of the peripheral data register from/to which the data is read/written. These bits are write-protected and can be written only when bit EN = '0' in the DMA_SxCR register.
Page 232: Dma Stream X Memory 1 Address Register (Dma_Sxm1Ar) (X = 0
Direct memory access controller (DMA) RM0390 9.5.9 DMA stream x memory 1 address register (DMA_SxM1AR) (x = 0..7) Address offset: 0x20 + 0x18 * stream number Reset value: 0x0000 0000 M1A[31:16] M1A[15:0] Bits 31:0 M1A[31:0]: memory 1 address (used in case of double-buffer mode) Base address of memory area 1 from/to which the data is read/written.
Page 233 RM0390 Direct memory access controller (DMA) Bit 2 DMDIS: direct mode disable This bit is set and cleared by software. It can be set by hardware. 0: direct mode enabled 1: direct mode disabled This bit is protected and can be written only if EN is ‘0’. This bit is set by hardware if the memory-to-memory mode is selected (DIR bit in DMA_SxCR are “10”) and the EN bit in the DMA_SxCR register is ‘1’...
Page 234: Dma Register Map
Direct memory access controller (DMA) RM0390 9.5.11 DMA register map Table 37 summarizes the DMA registers. Table 37. DMA register map and reset values Offset Register name DMA_LISR 0x0000 Reset value DMA_HISR 0x0004 Reset value DMA_LIFCR 0x0008 Reset value DMA_HIFCR 0x000C Reset value DMA_S0CR...
Page 235 RM0390 Direct memory access controller (DMA) Table 37. DMA register map and reset values (continued) Offset Register name DMA_S1M0AR M0A[31:0] 0x0034 Reset value DMA_S1M1AR M1A[31:0] 0x0038 Reset value DMA_S1FCR FS[2:0] 0x003C Reset value DMA_S2CR 0x0040 Reset value DMA_S2NDTR NDT[15:0] 0x0044 Reset value DMA_S2PAR PA[31:0]...
Page 236 Direct memory access controller (DMA) RM0390 Table 37. DMA register map and reset values (continued) Offset Register name DMA_S3FCR FS[2:0] 0x006C Reset value DMA_S4CR 0x0070 Reset value DMA_S4NDTR NDT[15:0] 0x0074 Reset value DMA_S4PAR PA[31:0] 0x0078 Reset value DMA_S4M0AR M0A[31:0] 0x007C Reset value DMA_S4M1AR M1A[31:0]...
Page 237 RM0390 Direct memory access controller (DMA) Table 37. DMA register map and reset values (continued) Offset Register name DMA_S6NDTR NDT[15:0] 0x00A4 Reset value DMA_S6PAR PA[31:0] 0x00A8 Reset value DMA_S6M0AR M0A[31:0] 0x00AC Reset value DMA_S6M1AR M1A[31:0] 0x00B0 Reset value DMA_S6FCR FS[2:0] 0x00B4 Reset value DMA_S7CR...
Page 238: Interrupts And Events
Interrupts and events RM0390 Interrupts and events 10.1 Nested vectored interrupt controller (NVIC) 10.1.1 NVIC features The nested vector interrupt controller NVIC includes the following features: ® • 96 maskable interrupt channels (not including the 16 interrupt lines of Cortex -M4 with FPU) •...
Page 239 RM0390 Interrupts and events Table 38. Vector table for STM32F446xx (continued) Type of Acronym Description Address priority settable BusFault Pre-fetch fault, memory access fault 0x0000 0014 settable UsageFault Undefined instruction or illegal state 0x0000 0018 0x0000 001C - Reserved 0x0000 002B settable SVCall System Service call via SWI instruction...
Page 240 Interrupts and events RM0390 Table 38. Vector table for STM32F446xx (continued) Type of Acronym Description Address priority TIM1 Break interrupt settable TIM1_BRK_TIM9 0x0000 00A0 and TIM9 global interrupt TIM1 Update interrupt settable TIM1_UP_TIM10 0x0000 00A4 and TIM10 global interrupt TIM1 Trigger and Commutation interrupts settable TIM1_TRG_COM_TIM11 0x0000 00A8...
Page 241 RM0390 Interrupts and events Table 38. Vector table for STM32F446xx (continued) Type of Acronym Description Address priority settable UART5 UART5 global interrupt 0x0000 0114 TIM6 global interrupt, settable TIM6_DAC 0x0000 0118 DAC1 and DAC2 underrun error interrupts settable TIM7 TIM7 global interrupt 0x0000 011C settable DMA2_Stream0...
Page 242: Exti Main Features
Interrupts and events RM0390 Table 38. Vector table for STM32F446xx (continued) Type of Acronym Description Address priority settable SPI4 SPI 4 global interrupt 0x0000 0190 Reserved 0x0000 0194 Reserved 0x0000 0198 settable SAI1 SAI1 global interrupt 0x0000 019C Reserved 0x0000 01A0 Reserved 0x0000 01A4 Reserved...
Page 243: Exti Block Diagram
RM0390 Interrupts and events 10.2.2 EXTI block diagram Figure 30 shows the block diagram. Figure 30. External interrupt/event controller block diagram 10.2.3 Wakeup event management The STM32F446xx microcontrollers are able to handle external or internal events in order to wake up the core (WFE). The wakeup event can be generated either by: •...
Page 244 Interrupts and events RM0390 generated. The pending bit corresponding to the interrupt line is also set. This request is reset by writing a ‘1’ in the pending register. To generate the event, the event line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the event request by writing a ‘1’...
Page 245: External Interrupt/Event Line Mapping
RM0390 Interrupts and events 10.2.5 External interrupt/event line mapping Up to 114 GPIOs are connected to the 16 external interrupt/event lines in the following manner: Figure 31. External interrupt/event GPIO mapping The seven other EXTI lines are connected as follows: •...
Page 246: Exti Registers
Interrupts and events RM0390 10.3 registers EXTI Refer to for a list of abbreviations used in register descriptions. Section 1.1 on page 51 10.3.1 Interrupt mask register (EXTI_IMR) Address offset: 0x00 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res.
Page 247: Rising Trigger Selection Register (Exti_Rtsr)
RM0390 Interrupts and events 10.3.3 Rising trigger selection register (EXTI_RTSR) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. TR22 TR21 TR20 Res. TR18 TR17 TR16 TR15 TR14 TR13 TR12 TR11 TR10 Bits 31:23 Reserved, must be kept at reset value. Bits 22:20 TRx: Rising trigger event configuration bit of line x 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line...
Page 248: Software Interrupt Event Register (Exti_Swier)
Interrupts and events RM0390 Note: The external wakeup lines are edge triggered, no glitch must be generated on these lines. If a falling edge occurs on the external interrupt line while writing to the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line.
Page 249: Exti Register Map
RM0390 Interrupts and events 10.3.7 EXTI register map Table 39 gives the EXTI register map and the reset values. Table 39. External interrupt/event controller register map and reset values Offset Register EXTI_IMR MR[22:0] 0x00 Reset value EXTI_EMR MR[22:0] 0x04 Reset value EXTI_RTSR TR[22:0] TR[22:0...
Page 250: Flexible Memory Controller (Fmc)
Flexible memory controller (FMC) RM0390 Flexible memory controller (FMC) The Flexible memory controller (FMC) includes three memory controllers: • The NOR/PSRAM memory controller • The NAND memory controller • The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller 11.1 FMC main features The FMC functional block makes the interface with: synchronous and asynchronous static memories, SDRAM memories, and NAND Flash memory.
Page 251: Fmc Block Diagram
RM0390 Flexible memory controller (FMC) The Write FIFO can be disabled by setting the WFDIS bit in the FMC_BCR1 register. At startup the FMC pins must be configured by the user application. The FMC I/O pins which are not used by the application can be used for other purposes. The FMC registers that define the external device type and associated characteristics are usually set at boot time and do not change until the next reset or power-up.
Page 252: Ahb Interface
Flexible memory controller (FMC) RM0390 11.3 AHB interface The AHB slave interface allows internal CPUs and other bus master peripherals to access the external memories. AHB transactions are translated into the external device protocol. In particular, if the selected external memory is 16- or 8-bit wide, 32-bit wide transactions on the AHB are split into consecutive 16- or 8-bit accesses.
Page 253 RM0390 Flexible memory controller (FMC) Therefore, some simple transaction rules must be followed: • AHB transaction size and memory data size are equal There is no issue in this case. • AHB transaction size is greater than the memory size: In this case, the FMC splits the AHB transaction into smaller consecutive memory accesses to meet the external data width.
Page 254: External Device Address Mapping
Flexible memory controller (FMC) RM0390 11.4 External device address mapping From the FMC point of view, the external memory is divided into fixed-size banks of 256 Mbytes each (see Figure 33): • Bank 1 used to address up to 4 NOR Flash memory or PSRAM devices. This bank is split into 4 NOR/PSRAM subbanks with 4 dedicated Chip Selects, as follows: –...
Page 255: Nor/Psram Address Mapping
RM0390 Flexible memory controller (FMC) 11.4.1 NOR/PSRAM address mapping HADDR[27:26] bits are used to select one of the four memory banks as shown in Table Table 40. NOR/PSRAM bank selection HADDR[27:26] Selected bank Bank 1 - NOR/PSRAM 1 Bank 1 - NOR/PSRAM 2 Bank 1 - NOR/PSRAM 3 Bank 1 - NOR/PSRAM 4 1.
Page 256: Sdram Address Mapping
Flexible memory controller (FMC) RM0390 Table 43. NAND bank selection Section name HADDR[17:16] Address range Address section 0x020000-0x03FFFF Command section 0x010000-0x01FFFF Data section 0x000000-0x0FFFF The application software uses the 3 sections to access the NAND Flash memory: • To sending a command to NAND Flash memory, the software must write the command value to any memory location in the command section.
Page 257: Table 46. Sdram Address Mapping With 8-Bit Data Bus Width
RM0390 Flexible memory controller (FMC) The HADDR[27:0] bits are translated to external SDRAM address depending on the SDRAM controller configuration: • Data size:8 or 16 bits • Row size:11, 12 or 13 bits • Column size: 8, 9, 10 or 11 bits •...
Page 258: Nor Flash/Psram Controller
Flexible memory controller (FMC) RM0390 (1)(2) Table 47. SDRAM address mapping with 16-bit data bus width HADDR(AHB address Lines) Row size Configuration Bank Res. Row[10:0] Column[7:0] [1:0] Bank Res. Row[10:0] Column[8:0] 11-bit row size [1:0] Bank configuration Res. Row[10:0] Column[9:0] [1:0] Bank Res.
Page 259: Table 48. Programmable Nor/Psram Access Parameters
RM0390 Flexible memory controller (FMC) The FMC supports a wide range of devices through a programmable timings among which: • Programmable wait states (up to 15) • Programmable bus turnaround cycles (up to 15) • Programmable output enable and write enable delays (up to 15) •...
Page 260: External Memory Interface Signals
Flexible memory controller (FMC) RM0390 11.5.1 External memory interface signals Table Table 50 Table 51 list the signals that are typically used to interface with NOR Flash memory, SRAM and PSRAM. Note: The prefix “N” identifies the signals that are active low. NOR Flash memory, non-multiplexed I/Os Table 49.
Page 261: Supported Memories And Transactions
RM0390 Flexible memory controller (FMC) PSRAM/SRAM, non-multiplexed I/Os Table 51. Non-multiplexed I/Os PSRAM/SRAM FMC signal name Function Clock (only for PSRAM synchronous access) A[25:0] Address bus D[15:0] Data bidirectional bus NE[x] Chip Select, x = 1..4 (called NCE by PSRAM (CellularRAM™ i.e. CRAM)) Output enable Write enable NL(= NADV)
Page 262: Table 53. Nor Flash/Psram: Example Of Supported Memories And Transactions
Flexible memory controller (FMC) RM0390 Table 53. NOR Flash/PSRAM: example of supported memories and transactions Allowed/ Memory Device Mode data Comments data size size allowed Asynchronous Asynchronous Asynchronous Asynchronous NOR Flash Asynchronous Split into 2 FMC accesses (muxed I/Os Asynchronous Split into 2 FMC accesses and nonmuxed I/Os)
Page 263: General Timing Rules
RM0390 Flexible memory controller (FMC) 11.5.3 General timing rules Signals synchronization • All controller output signals change on the rising edge of the internal clock (HCLK) • In synchronous mode (read or write), all output signals change on the rising edge of HCLK.
Page 264: Figure 34. Mode1 Read Access Waveforms
Flexible memory controller (FMC) RM0390 Mode 1 - SRAM/PSRAM (CRAM) The next figures show the read and write transactions for the supported modes followed by the required configuration of FMC_BCRx, and FMC_BTRx/FMC_BWTRx registers. Figure 34. Mode1 read access waveforms Figure 35. Mode1 write access waveforms 264/1328 RM0390 Rev 4...
Page 265: Table 54. Fmc_Bcrx Bit Fields
RM0390 Flexible memory controller (FMC) The one HCLK cycle at the end of the write transaction helps guarantee the address and data hold time after the NWE rising edge. Due to the presence of this HCLK cycle, the DATAST value must be greater than zero (DATAST > 0). Table 54.
Page 266: Figure 36. Modea Read Access Waveforms
Flexible memory controller (FMC) RM0390 Mode A - SRAM/PSRAM (CRAM) OE toggling Figure 36. ModeA read access waveforms 1. NBL[1:0] are driven low during the read access Figure 37. ModeA write access waveforms 266/1328 RM0390 Rev 4...
Page 267: Table 56. Fmc_Bcrx Bit Fields
RM0390 Flexible memory controller (FMC) The differences compared with Mode1 are the toggling of NOE and the independent read and write timings. Table 56. FMC_BCRx bit fields Bit number Bit name Value to set 31:22 Reserved 0x000 WFDIS As needed CCLKEN As needed CBURSTRW...
Page 268: Table 58. Fmc_Bwtrx Bit Fields
Flexible memory controller (FMC) RM0390 Table 58. FMC_BWTRx bit fields Bit number Bit name Value to set 31:30 Reserved 29:28 ACCMOD 27:24 DATLAT Don’t care 23:20 CLKDIV Don’t care 19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK). Duration of the second access phase (DATAST HCLK cycles) for write 15:8 DATAST...
Page 269: Figure 39. Mode2 Write Access Waveforms
RM0390 Flexible memory controller (FMC) Figure 39. Mode2 write access waveforms Figure 40. ModeB write access waveforms The differences with Mode1 are the toggling of NWE and the independent read and write timings when extended mode is set (Mode B). RM0390 Rev 4 269/1328...
Page 270: Table 59. Fmc_Bcrx Bit Fields
Flexible memory controller (FMC) RM0390 Table 59. FMC_BCRx bit fields Bit number Bit name Value to set 31:22 Reserved 0x000 WFDIS As needed CCLKEN As needed CBURSTRW 0x0 (no effect in asynchronous mode) 18:16 CPSIZE 0x0 (no effect in asynchronous mode) ASYNCWAIT Set to 1 if the memory supports this feature.
Page 271: Table 61. Fmc_Bwtrx Bit Fields
RM0390 Flexible memory controller (FMC) Table 61. FMC_BWTRx bit fields Bit number Bit name Value to set 31:30 Reserved 29:28 ACCMOD 0x1 if extended mode is set 27:24 DATLAT Don’t care 23:20 CLKDIV Don’t care 19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK). Duration of the access second phase (DATAST HCLK cycles) for 15:8 DATAST...
Page 272: Table 62. Fmc_Bcrx Bit Fields
Flexible memory controller (FMC) RM0390 Figure 42. ModeC write access waveforms The differences compared with Mode1 are the toggling of NOE and the independent read and write timings. Table 62. FMC_BCRx bit fields Bit number Bit name Value to set 31:22 Reserved 0x000...
Page 273: Table 63. Fmc_Btrx Bit Fields
RM0390 Flexible memory controller (FMC) Table 62. FMC_BCRx bit fields (continued) Bit number Bit name Value to set MTYP 0x02 (NOR Flash memory) MUXEN MBKEN Table 63. FMC_BTRx bit fields Bit number Bit name Value to set 31:30 Reserved 29:28 ACCMOD 27:24 DATLAT...
Page 274: Figure 43. Moded Read Access Waveforms
Flexible memory controller (FMC) RM0390 Mode D - asynchronous access with extended address Figure 43. ModeD read access waveforms Figure 44. ModeD write access waveforms 274/1328 RM0390 Rev 4...
Page 275: Table 65. Fmc_Bcrx Bit Fields
RM0390 Flexible memory controller (FMC) The differences with Mode1 are the toggling of NOE that goes on toggling after NADV changes and the independent read and write timings. Table 65. FMC_BCRx bit fields Bit number Bit name Value to set 31:22 Reserved 0x000...
Page 276: Table 67. Fmc_Bwtrx Bit Fields
Flexible memory controller (FMC) RM0390 Table 67. FMC_BWTRx bit fields Bit number Bit name Value to set 31:30 Reserved 29:28 ACCMOD 27:24 DATLAT Don’t care 23:20 CLKDIV Don’t care 19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK). Duration of the second access phase (DATAST + 1 HCLK cycles) for 15:8 DATAST...
Page 277: Table 68. Fmc_Bcrx Bit Fields
RM0390 Flexible memory controller (FMC) Figure 46. Muxed write access waveforms The difference with ModeD is the drive of the lower address byte(s) on the data bus. Table 68. FMC_BCRx bit fields Bit number Bit name Value to set 31:22 Reserved 0x000 WFDIS...
Page 278: Table 69. Fmc_Btrx Bit Fields
Flexible memory controller (FMC) RM0390 Table 68. FMC_BCRx bit fields (continued) Bit number Bit name Value to set MTYP 0x2 (NOR Flash memory) or 0x1(PSRAM) MUXEN MBKEN Table 69. FMC_BTRx bit fields Bit number Bit name Value to set 31:30 Reserved 29:28 ACCMOD...
Page 279: Figure 47. Asynchronous Wait During A Read Access Waveforms
RM0390 Flexible memory controller (FMC) The memory asserts the WAIT signal aligned to NOE/NWE which toggles: DATAST ≥ × HCLK max_wait_assertion_time The memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling): > max_wait_assertion_time address_phase hold_phase then: ≥ ×...
Page 280: Synchronous Transactions
Flexible memory controller (FMC) RM0390 Figure 48. Asynchronous wait during a write access waveforms 1. NWAIT polarity depends on WAITPOL bit setting in FMC_BCRx register. 11.5.5 Synchronous transactions The memory clock, FMC_CLK, is a submultiple of HCLK. It depends on the value of CLKDIV and the MWID/ AHB data size, following the formula given below: FMC_CLK divider ratio max CLKDIV...
Page 281 RM0390 Flexible memory controller (FMC) Caution: Some NOR Flash memories include the NADV Low cycle in the data latency count, so that the exact relation between the NOR Flash latency and the FMC DATLAT parameter can be either: • NOR Flash latency = (DATLAT + 2) CLK clock cycles •...
Page 282: Figure 49. Wait Configuration Waveforms
Flexible memory controller (FMC) RM0390 Figure 49. Wait configuration waveforms 282/1328 RM0390 Rev 4...
Page 283: Table 70. Fmc_Bcrx Bit Fields
RM0390 Flexible memory controller (FMC) Figure 50. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) 1. Byte lane outputs (NBL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM) access, they are held low. Table 70.
Page 284: Table 71. Fmc_Btrx Bit Fields
Flexible memory controller (FMC) RM0390 Table 70. FMC_BCRx bit fields (continued) Bit number Bit name Value to set WAITPOL To be set according to memory BURSTEN Reserved FACCEN Set according to memory support (NOR Flash memory) MWID As needed MTYP 0x1 or 0x2 MUXEN As needed...
Page 285: Table 72. Fmc_Bcrx Bit Fields
RM0390 Flexible memory controller (FMC) Figure 51. Synchronous multiplexed write mode waveforms - PSRAM (CRAM) 1. The memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed to 0. 2. Byte Lane (NBL) outputs are not shown, they are held low while NEx is active. Table 72.
Page 286: Table 73. Fmc_Btrx Bit Fields
Flexible memory controller (FMC) RM0390 Table 72. FMC_BCRx bit fields (continued) Bit number Bit name Value to set WREN WAITCFG Reserved WAITPOL to be set according to memory BURSTEN no effect on synchronous write Reserved FACCEN Set according to memory support MWID As needed MTYP...
Page 287: Nor/Psram Controller Registers
RM0390 Flexible memory controller (FMC) 11.5.6 NOR/PSRAM controller registers SRAM/NOR-Flash chip-select control registers 1..4 (FMC_BCR1..4) Address offset: 8 * (x – 1), x = 1...4 Reset value: 0x0000 30DB for Bank1 and 0x0000 30D2 for Bank 2 to 4 This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.
Page 288 Flexible memory controller (FMC) RM0390 Bits 18:16 CPSIZE[2:0]: CRAM page size. These are used for CellularRAM™ 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size).
Page 289 RM0390 Flexible memory controller (FMC) Bit 8 BURSTEN: Burst enable bit. This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in burst mode: 0: Burst mode disabled (default after reset). Read accesses are performed in asynchronous mode. 1: Burst mode enable.
Page 290 Flexible memory controller (FMC) RM0390 Res. Res. ACCMOD DATLAT CLKDIV BUSTURN DATAST ADDHLD ADDSET Bits 31:30 Reserved, must be kept at reset value Bits 29:28 ACCMOD[1:0]: Access mode Specifies the asynchronous access modes as shown in the timing diagrams. These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1.
Page 291 RM0390 Flexible memory controller (FMC) Bits 19:16 BUSTURN[3:0]: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read (and read-to- write) transaction. This delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time needed by the memory to free the data bus after a read access (tEHQZ).
Page 292 Flexible memory controller (FMC) RM0390 Bits 7:4 ADDHLD[3:0]: Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure 34 Figure 46), used in mode D or multiplexed accesses: 0000: Reserved 0001: ADDHLD phase duration =1 ×...
Page 293 RM0390 Flexible memory controller (FMC) Bits 29:28 ACCMOD[1:0]: Access mode. Specifies the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. 00: access mode A 01: access mode B 10: access mode C 11: access mode D...
Page 294: Nand Flash Controller
Flexible memory controller (FMC) RM0390 Bits 3:0 ADDSET[3:0]: Address setup phase duration. These bits are written by software to define the duration of the address setup phase in HCLK cycles (refer to Figure 34 Figure 46), used in asynchronous accesses: 0000: ADDSET phase duration = 0 ×...
Page 295: Table 76. 16-Bit Nand Flash
RM0390 Flexible memory controller (FMC) Table 75. 8-bit NAND Flash (continued) FMC signal name Function D[7:0] 8-bit multiplexed, bidirectional address/data bus Chip Select NOE(= NRE) Output enable (memory signal name: read enable, NRE) Write enable NWAIT/INT NAND Flash ready/busy input signal to the FMC Theoretically, there is no capacity limitation as the FMC can manage as many address cycles as needed.
Page 296: Nand Flash Supported Memories And Transactions
Flexible memory controller (FMC) RM0390 11.6.2 NAND Flash supported memories and transactions Table 77 shows the supported devices, access modes and transactions. Transactions not allowed (or not supported) by the NAND Flash controller are shown in gray. Table 77. Supported memories and transactions Memory Allowed/ Device...
Page 297: Nand Flash Operations
RM0390 Flexible memory controller (FMC) Figure 52. NAND Flash controller waveforms for common memory access 1. NOE remains high (inactive) during write accesses. NWE remains high (inactive) during read accesses. 2. For write access, the hold phase delay is (MEMHOLD) HCLK cycles and for read access is (MEMHOLD + 2) HCLK cycles.
Page 298: Nand Flash Prewait Functionality
Flexible memory controller (FMC) RM0390 to implement the prewait functionality needed by some NAND Flash memories (see details in Section 11.6.5: NAND Flash prewait functionality). The controller waits for the NAND Flash memory to be ready (R/NB signal high), before starting a new access to the same or another memory bank.
Page 299: Computation Of The Error Correction Code (Ecc) In Nand Flash Memory
RM0390 Flexible memory controller (FMC) When this functionality is required, it can be ensured by programming the MEMHOLD value to meet the t timing. However any CPU read access to the NAND Flash memory has a hold delay of (MEMHOLD + 2) HCLK cycles and CPU write access has a hold delay of (MEMHOLD) HCLK cycles inserted between the rising edge of the NWE signal and the next access.
Page 300: Nand Flash Controller Registers
Flexible memory controller (FMC) RM0390 To perform an ECC computation: Enable the ECCEN bit in the FMC_PCR register. Write data to the NAND Flash memory page. While the NAND page is written, the ECC block computes the ECC value. Read the ECC value available in the FMC_ECCR register and store it in a variable. Clear the ECCEN bit and then enable it in the FMC_PCR register before reading back the written data from the NAND page.
Page 301 RM0390 Flexible memory controller (FMC) Bits 12:9 TCLR[3:0]: CLE to RE delay. Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period 0000: 1 HCLK cycle (default) 1111: 16 HCLK cycles Note: SET is MEMSET or ATTSET according to the addressed space.
Page 302 Flexible memory controller (FMC) RM0390 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FEMPT IFEN ILEN IREN Bits 31:7 Reserved, must be kept at reset value Bit 6 FEMPT: FIFO empty.
Page 303 RM0390 Flexible memory controller (FMC) MEMHIZx MEMHOLDx MEMWAITx MEMSETx Bits 31:24 MEMHIZ[7:0]: Common memory x data bus Hi-Z time Defines the number of HCLK clock cycles during which the data bus is kept Hi-Z after the start of a NAND Flash write access to common memory space on socket. This is only valid for write transactions: 0000 0000: 1 HCLK cycle 1111 1110: 255 HCLK cycles...
Page 304 Flexible memory controller (FMC) RM0390 ATTHIZ ATTHOLD ATTWAIT ATTSET Bits 31:24 ATTHIZ[7:0]: Attribute memory data bus Hi-Z time Defines the number of HCLK clock cycles during which the data bus is kept in Hi-Z after the start of a NAND Flash write access to attribute memory space on socket. Only valid for writ transaction: 0000 0000: 0 HCLK cycle 1111 1110: 255 HCLK cycles...
Page 305: Table 78. Ecc Result Relevant Bits
RM0390 Flexible memory controller (FMC) ECC result registers (FMC_ECCR) Address offset: 0x94 Reset value: 0x0000 0000 This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads the data from a NAND Flash memory page at the correct address (refer to Section 11.6.6: Computation of the error correction code (ECC) in NAND Flash...
Page 306: Sdram Controller
Flexible memory controller (FMC) RM0390 11.7 SDRAM controller 11.7.1 SDRAM controller main features The main features of the SDRAM controller are the following: • Two SDRAM banks with independent configuration • 8-bit, 16-bit data bus width • 13-bits Address Row, 11-bits Address Column, 4 internal banks: 4x16Mx16bit (128 MB), 4x16Mx8bit (64 MB) •...
Page 307: Sdram Controller Functional Description
RM0390 Flexible memory controller (FMC) 11.7.3 SDRAM controller functional description All SDRAM controller outputs (signals, address and data) change on the falling edge of the memory clock (FMC_SDCLK). SDRAM initialization The initialization sequence is managed by software. If the two banks are used, the initialization sequence must be generated simultaneously to Bank 1and Bank 2 by setting the Target Bank bits CTB1 and CTB2 in the FMC_SDCMR register: Program the memory device features into the FMC_SDCRx register.
Page 308: Figure 54. Burst Write Sdram Access Waveforms
Flexible memory controller (FMC) RM0390 Note: If two SDRAM devices are connected to the FMC, all the accesses performed at the same time to both devices by the Command Mode register (Load Mode Register command) are issued using the timing parameters configured for SDRAM Bank 1 (TMRD andTRAS timings) in the FMC_SDTR1 register.
Page 309: Figure 55. Burst Read Sdram Access
RM0390 Flexible memory controller (FMC) Figure 55. Burst read SDRAM access The FMC SDRAM controller features a Cacheable read FIFO (6 lines x 32 bits). It is used to store data read in advance during the CAS latency period and the RPIPE delay following the below formula.
Page 310: Figure 56. Logic Diagram Of Read Access With Rburst Bit Set (Cas=1, Rpipe=0)
Flexible memory controller (FMC) RM0390 Figure 56. Logic diagram of Read access with RBURST bit set (CAS=1, RPIPE=0) During a write access or a Precharge command, the read FIFO is flushed and ready to be filled with new data. After the first read request, if the current access was not performed to a row boundary, the SDRAM controller anticipates the next read access during the CAS latency period and the RPIPE delay (if configured).
Page 311 RM0390 Flexible memory controller (FMC) The address management depends on the next AHB request: • Next AHB request is sequential (AHB Burst) In this case, the SDRAM controller increments the address. • Next AHB request is not sequential – If the new read request targets the same row or another active row, the new address is passed to the memory and the master is stalled for the CAS latency period, waiting for the new data from memory.
Page 312: Figure 57. Read Access Crossing Row Boundary
Flexible memory controller (FMC) RM0390 Figure 57. Read access crossing row boundary Figure 58. Write access crossing row boundary 312/1328 RM0390 Rev 4...
Page 313: Low-Power Modes
RM0390 Flexible memory controller (FMC) If the next access is sequential and the current access crosses a bank boundary, the SDRAM controller activates the first row in the next bank and initiates a new read/write command. Two cases are possible: •...
Page 314: Figure 59. Self-Refresh Mode
Flexible memory controller (FMC) RM0390 Before entering Self-Refresh mode, the SDRAM controller automatically issues a PALL command. If the Write data FIFO is not empty, all data are sent to the memory before activating the Self-refresh mode and the BUSY status flag remains set. In Self-refresh mode, all SDRAM device inputs become don’t care except for SDCKE which remains low.
Page 315: Sdram Controller Registers
RM0390 Flexible memory controller (FMC) Power-down mode This mode is selected by setting the MODE bits to ‘110’ and by configuring the Target Bank bits (CTB1 and/or CTB2) in the FMC_SDCMR register. Figure 60. Power-down mode If the Write data FIFO is not empty, all data are sent to the memory before activating the Power-down mode.
Page 316 Flexible memory controller (FMC) RM0390 Reset value: 0x0000 02D0 This register contains the control parameters for each SDRAM memory bank Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RPIPE[1:0] RBURST SDCLK MWID Bits 31:15 Reserved, must be kept at reset value Bits 14:13 RPIPE[1:0]: Read pipe...
Page 317 RM0390 Flexible memory controller (FMC) Bits 5:4 MWID[1:0]: Memory data bus width. These bits define the memory device width. 00: 8 bits 01: 16 bits 10: reserved 11: reserved. Bits 3:2 NR[1:0]: Number of row address bits These bits define the number of bits of a row address. 00: 11 bit 01: 12 bits 10: 13 bits...
Page 318 Flexible memory controller (FMC) RM0390 Bits 23:20 TRP[3:0]: Row precharge delay These bits define the delay between a Precharge command and another command in number of memory clock cycles. The TRP timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRP must be programmed with the timing of the slowest device.
Page 319 RM0390 Flexible memory controller (FMC) Bits 3:0 TMRD[3:0]: Load Mode Register to Active These bits define the delay between a Load Mode Register command and an Active or Refresh command in number of memory clock cycles. 0000: 1 cycle 0001: 2 cycles ..
Page 320 Flexible memory controller (FMC) RM0390 Bit 3 CTB2: Command Target Bank 2 This bit indicates whether the command will be issued to SDRAM Bank 2 or not. 0: Command not issued to SDRAM Bank 2 1: Command issued to SDRAM Bank 2 Bits 2:0 MODE[2:0]: Command mode These bits define the command issued to the SDRAM device.
Page 321 RM0390 Flexible memory controller (FMC) As soon as the FMC_SDRTR register is programmed, the timer starts counting. If the value programmed in the register is ’0’, no refresh is carried out. This register must not be reprogrammed after the initialization procedure to avoid modifying the refresh rate. Each time a refresh pulse is generated, this 13-bit COUNT field is reloaded into the counter.
Page 322 Flexible memory controller (FMC) RM0390 Bit 5 BUSY: Busy status This bit defines the status of the SDRAM controller after a Command Mode request 0: SDRAM Controller is ready to accept a new request 1; SDRAM Controller is not ready to accept a new request Bits 4:3 MODES2[1:0]: Status Mode for Bank 2 This bit defines the Status Mode of SDRAM Bank 2.
Page 323: Fmc Register Map
RM0390 Flexible memory controller (FMC) 11.8 FMC register map Table 80. FMC register map Offset Register CPSIZE MWID MTYP FMC_BCR1 [2:0] [1:0] [1:0] 0x00 Reset value CPSIZE MWID MTYP FMC_BCR2 [2:0] [1:0] [1:0] 0x08 Reset value CPSIZE MWID MTYP FMC_BCR3 [2:0] [1:0] [1:0]...
Page 324 Flexible memory controller (FMC) RM0390 Table 80. FMC register map (continued) Offset Register FMC_BWTR3 BUSTURN[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0] 0x114 Reset value FMC_BWTR4 BUSTURN[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0] 0x11C Reset value ECCPS PWID FMC_PCR TAR[3:0] TCLR[3:0] [2:0] [1:0] 0x80 Reset value FMC_SR 0x84 Reset value FMC_PMEM...
Page 325: Quad-Spi Interface (Quadspi)
RM0390 Quad-SPI interface (QUADSPI) Quad-SPI interface (QUADSPI) 12.1 Introduction The QUADSPI is a specialized communication interface targeting single, dual or quad SPI Flash memories. It can operate in any of the three following modes: • indirect mode: all the operations are performed using the QUADSPI registers •...
Page 326: Quadspi Pins
Quad-SPI interface (QUADSPI) RM0390 Figure 62. QUADSPI block diagram when dual-flash mode is enabled 12.3.2 QUADSPI pins Table 81 lists the QUADSPI pins, six for interfacing with a single Flash memory, or 10 to 11 for interfacing with two Flash memories (FLASH 1 and FLASH 2) in dual-flash mode. Table 81.
Page 327: Quadspi Command Sequence
RM0390 Quad-SPI interface (QUADSPI) 12.3.3 QUADSPI command sequence The QUADSPI communicates with the Flash memory using commands. Each command can include 5 phases: instruction, address, alternate byte, dummy, data. Any of these phases can be configured to be skipped, but at least one of the instruction, address, alternate byte, or data phase must be present.
Page 328 Quad-SPI interface (QUADSPI) RM0390 Alternate-bytes phase In the alternate-bytes phase, 1-4 bytes are sent to the Flash memory, generally to control the mode of operation. The number of alternate bytes to be sent is configured in the ABSIZE[1:0] field of QUADSPI_CCR[17:16] register. The bytes to be sent are specified in the QUADSPI_ABR register.
Page 329: Quadspi Signal Interface Protocol Modes
RM0390 Quad-SPI interface (QUADSPI) mode). This can be configured using the ABMODE[1:0] field of QUADSPI_CCR[15:14] register. When DMODE = 00, the data phase is skipped, and the command sequence finishes immediately by raising nCS. This configuration must only be used in only indirect write mode.
Page 330: Figure 64. An Example Of A Ddr Command In Quad Mode
Quad-SPI interface (QUADSPI) RM0390 SDR mode By default, the DDRM bit (QUADSPI_CCR[31]) is 0 and the QUADSPI operates in single data rate (SDR) mode. In SDR mode, when the QUADSPI is driving the IO0/SO, IO1, IO2, IO3 signals, these signals transition only with the falling edge of CLK. When receiving data in SDR mode, the QUADSPI assumes that the Flash memories also send the data using CLK’s falling edge.
Page 331: Quadspi Indirect Mode
RM0390 Quad-SPI interface (QUADSPI) The Flash memory size, as specified in FSIZE[4:0] (QUADSPI_DCR[20:16]), should reflect the total Flash memory capacity, which is double the size of one individual component. If address X is even, then the byte which the QUADSPI gives for address X is the byte at the address X/2 of FLASH 1, and the byte which the QUADSPI gives for address X+1 is the byte at the address X/2 of FLASH 2.
Page 332 Quad-SPI interface (QUADSPI) RM0390 is set when the limit of the external SPI memory is reached according to the Flash memory size defined in the QUADSPI_CR. Triggering the start of a command Essentially, a command starts as soon as firmware gives the last information that is necessary for this command.
Page 333: Quadspi Status Flag Polling Mode
RM0390 Quad-SPI interface (QUADSPI) 12.3.6 QUADSPI status flag polling mode In automatic-polling mode, the QUADSPI periodically starts a command to read a defined number of status bytes (up to 4). The received bytes can be masked to isolate some status bits and an interrupt can be generated when the selected bits have a defined value.
Page 334: Quadspi Flash Memory Configuration
Quad-SPI interface (QUADSPI) RM0390 By default, the QUADSPI never stops its prefetch operation, keeping the previous read operation active with nCS maintained low, even if no access to the Flash memory occurs for a long time. Since Flash memories tend to consume more when nCS is held low, the application might want to activate the timeout counter (TCEN = 1, bit 3 of QUADSPI_CR) so that nCS is released after a period of TIMEOUT[15:0] (QUADSPI_LPTR) cycles have elapsed without any access since when the FIFO becomes full with prefetch data.
Page 335: Quadspi Usage
RM0390 Quad-SPI interface (QUADSPI) The QUADSPI IP is configured using the QUADSPI_CR. The user shall configure the clock prescaler division factor and the sample shifting settings for the incoming data. DDR mode can be set through the DDRM bit. Once enabled, the address and the alternate bytes are sent on both clock edges and the data are sent/received on both clock edges.
Page 336 Quad-SPI interface (QUADSPI) RM0390 When writing the control register (QUADSPI_CR) the user specifies the following settings: • The enable bit (EN) set to ‘1’ • The DMA enable bit (DMAEN) for transferring data to/from RAM • Timeout counter enable bit (TCEN) •...
Page 337: Sending The Instruction Only Once
RM0390 Quad-SPI interface (QUADSPI) In case of match, the status match flag is set and an interrupt is generated if enabled, and the QUADSPI can be automatically stopped if the AMPS bit is set. In any case, the latest retrieved value is available in the QUADSPI_DR. Memory-mapped mode In memory-mapped mode, the external Flash memory is seen as internal memory but with some latency during accesses.
Page 338: Quadspi Busy Bit And Abort Functionality
Quad-SPI interface (QUADSPI) RM0390 12.3.14 QUADSPI busy bit and abort functionality Once the QUADSPI starts an operation with the Flash memory, the BUSY bit is automatically set in the QUADSPI_SR. In indirect mode, the BUSY bit is reset once the QUADSPI has completed the requested command sequence and the FIFO is empty.
Page 339: Figure 67. Ncs When Ckmode = 1 In Ddr Mode (T = Clk Period)
RM0390 Quad-SPI interface (QUADSPI) When CKMODE = 1 (“mode3”) and DDRM = 1 (DDR mode), nCS falls one CLK cycle before an operation first rising CLK edge, and nCS rises one CLK cycle after the operation final active rising CLK edge, as shown in Figure 67.
Page 340: Quadspi Interrupts
Quad-SPI interface (QUADSPI) RM0390 12.4 QUADSPI interrupts An interrupt can be produced on the following events: • Timeout • Status match • FIFO threshold • Transfer complete • Transfer error Separate interrupt enable bits are available for flexibility. Table 82. QUADSPI interrupt requests Interrupt event Event flag Enable control bit...
Page 341: Quadspi Registers
RM0390 Quad-SPI interface (QUADSPI) 12.5 QUADSPI registers 12.5.1 QUADSPI control register (QUADSPI_CR) Address offset: 0x0000 Reset value: 0x0000 0000 PRESCALER[7:0] APMS Res. TOIE SMIE FTIE TCIE TEIE Res. Res. Res. FTHRES[4:0] FSEL Res. SSHIFT TCEN DMAEN ABORT Bits 31:24 PRESCALER[7:0]: Clock prescaler This field defines the scaler factor for generating CLK based on the AHB clock (value+1).
Page 342 Quad-SPI interface (QUADSPI) RM0390 Bit 18 FTIE: FIFO threshold interrupt enable This bit enables the FIFO threshold interrupt. 0: Interrupt disabled 1: Interrupt enabled Bit 17 TCIE: Transfer complete interrupt enable This bit enables the transfer complete interrupt. 0: Interrupt disabled 1: Interrupt enabled Bit 16 TEIE: Transfer error interrupt enable This bit enables the transfer error interrupt.
Page 343 RM0390 Quad-SPI interface (QUADSPI) Bit 4 SSHIFT: Sample shift By default, the QUADSPI samples data 1/2 of a CLK cycle after the data is driven by the Flash memory. This bit allows the data is to be sampled later in order to account for external signal delays.
Page 344: Quadspi Device Configuration Register (Quadspi_Dcr)
Quad-SPI interface (QUADSPI) RM0390 12.5.2 QUADSPI device configuration register (QUADSPI_DCR) Address offset: 0x0004 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FSIZE[4:0] Res. Res. Res. Res. Res. CSHT[2:0] Res. Res. Res. Res. Res. Res.
Page 345: Quadspi Status Register (Quadspi_Sr)
RM0390 Quad-SPI interface (QUADSPI) 12.5.3 QUADSPI status register (QUADSPI_SR) Address offset: 0x0008 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FLEVEL[5:0] Res. Res. BUSY Bits 31:14 Reserved, must be kept at reset value. Bits 13:8 FLEVEL[5:0]: FIFO level This field gives the number of valid bytes which are being held in the FIFO.
Page 346: Quadspi Flag Clear Register (Quadspi_Fcr)
Quad-SPI interface (QUADSPI) RM0390 12.5.4 QUADSPI flag clear register (QUADSPI_FCR) Address offset: 0x000C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 347: Quadspi Communication Configuration Register (Quadspi_Ccr)
RM0390 Quad-SPI interface (QUADSPI) Bits 31:0 DL[31:0]: Data length Number of data to be retrieved (value+1) in indirect and status-polling modes. A value no greater than 3 (indicating 4 bytes) should be used for status-polling mode. All 1s in indirect mode means undefined length, where QUADSPI will continue until the end of memory, as defined by FSIZE.
Page 348 Quad-SPI interface (QUADSPI) RM0390 Bit 28 SIOO: Send instruction only once mode Section 12.3.12: Sending the instruction only once on page 337. This bit has no effect when IMODE = 00. 0: Send instruction on every transaction 1: Send instruction only for the first command This field can be written only when BUSY = 0.
Page 349: Quadspi Address Register (Quadspi_Ar)
RM0390 Quad-SPI interface (QUADSPI) Bits 13:12 ADSIZE[1:0]: Address size This bit defines address size: 00: 8-bit address 01: 16-bit address 10: 24-bit address 11: 32-bit address This field can be written only when BUSY = 0. Bits 11:10 ADMODE[1:0]: Address mode This field defines the address phase mode of operation: 00: No address 01: Address on a single line...
Page 350: Quadspi Alternate Bytes Registers (Quadspi_Abr)
Quad-SPI interface (QUADSPI) RM0390 12.5.8 QUADSPI alternate bytes registers (QUADSPI_ABR) Address offset: 0x001C Reset value: 0x0000 0000 ALTERNATE[31:16] ALTERNATE[15:0] Bits 31:0 ALTERNATE[31:0]: Alternate Bytes Optional data to be send to the external SPI device right after the address. This field can be written only when BUSY = 0. 12.5.9 QUADSPI data register (QUADSPI_DR) Address offset: 0x0020...
Page 351: Quadspi Polling Status Mask Register (Quadspi
RM0390 Quad-SPI interface (QUADSPI) 12.5.10 QUADSPI polling status mask register (QUADSPI _PSMKR) Address offset: 0x0024 Reset value: 0x0000 0000 MASK[31:16] MASK[15:0] Bits 31:0 MASK[31:0]: Status mask Mask to be applied to the status bytes received in polling mode. For bit n: 0: Bit n of the data received in automatic polling mode is masked and its value is not considered in the matching logic 1: Bit n of the data received in automatic polling mode is unmasked and its value is...
Page 352: Quadspi Polling Interval Register (Quadspi
Quad-SPI interface (QUADSPI) RM0390 12.5.12 QUADSPI polling interval register (QUADSPI _PIR) Address offset: 0x002C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. INTERVAL[15:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 INTERVAL[15:0]: Polling interval Number of CLK cycles between to read during automatic polling phases.
Page 353: Quadspi Register Map
RM0390 Quad-SPI interface (QUADSPI) 12.5.14 QUADSPI register map Table 83. QUADSPI register map and reset values Register Offset name FTHRES QUADSPI_CR PRESCALER[7:0] [4:0] 0x0000 Reset value QUADSPI_DCR FSIZE[4:0] CSHT 0x0004 Reset value QUADSPI_SR FLEVEL[6:0] 0x0008 Reset value QUADSPI_FCR 0x000C Reset value QUADSPI_DLR DL[31:0] 0x0010...
Page 354: Analog-To-Digital Converter (Adc)
Analog-to-digital converter (ADC) RM0390 Analog-to-digital converter (ADC) 13.1 ADC introduction The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 19 multiplexed channels allowing it to measure signals from 16 external sources, two internal sources, and the V channel.
Page 355: Figure 69. Single Adc Block Diagram
RM0390 Analog-to-digital converter (ADC) Figure 69. Single ADC block diagram RM0390 Rev 4 355/1328...
Page 356: Adc On-Off Control
Analog-to-digital converter (ADC) RM0390 Table 84. ADC pins Name Signal type Remarks Input, analog reference The higher/positive reference voltage for the ADC, REF+ positive 1.8 V ≤ V ≤ V REF+ Analog power supply equal to V Input, analog supply 2.4 V ≤V ≤V (3.6 V) for full speed...
Page 357: Adc1/2 And Adc3 Connectivity
RM0390 Analog-to-digital converter (ADC) 13.3.2 ADC1/2 and ADC3 connectivity ADC1, ADC2 and ADC3 are tightly coupled and share some external channels as described Figure Figure 71 Figure Figure 70. ADC1 connectivity RM0390 Rev 4 357/1328...
Page 358: Figure 71. Adc2 Connectivity
Analog-to-digital converter (ADC) RM0390 Figure 71. ADC2 connectivity 358/1328 RM0390 Rev 4...
Page 359: Figure 72. Adc3 Connectivity
RM0390 Analog-to-digital converter (ADC) Figure 72. ADC3 connectivity RM0390 Rev 4 359/1328...
Page 360: Adc Clock
Analog-to-digital converter (ADC) RM0390 13.3.3 ADC clock The ADC features two clock schemes: • Clock for the analog circuitry: ADCCLK, common to all ADCs This clock is generated from the APB2 clock divided by a programmable prescaler that allows the ADC to work at f /2, /4, /6 or /8.
Page 361: Single Conversion Mode
RM0390 Analog-to-digital converter (ADC) 13.3.5 Single conversion mode In Single conversion mode the ADC does one conversion. This mode is started with the CONT bit at 0 by either: • setting the SWSTART bit in the ADC_CR2 register (for a regular channel only) •...
Page 362: Analog Watchdog
Analog-to-digital converter (ADC) RM0390 Figure 73. Timing diagram 13.3.8 Analog watchdog The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is below a lower threshold or above a higher threshold. These thresholds are programmed in the 12 least significant bits of the ADC_HTR and ADC_LTR 16-bit registers.
Page 363: Scan Mode
RM0390 Analog-to-digital converter (ADC) Table 85. Analog watchdog channel selection (continued) ADC_CR1 register control bits (x = don’t care) Channels guarded by the analog watchdog AWDSGL bit AWDEN bit JAWDEN bit All regular channels All regular and injected channels Single injected channel Single regular channel...
Page 364: Discontinuous Mode
Analog-to-digital converter (ADC) RM0390 Note: When using triggered injection, one must ensure that the interval between trigger events is longer than the injection sequence. For instance, if the sequence length is 30 ADC clock cycles (that is two conversions with a sampling time of 3 clock periods), the minimum interval between triggers must be 31 ADC clock cycles.
Page 365: Data Alignment
RM0390 Analog-to-digital converter (ADC) Example: • n = 3, channels to be converted = 0, 1, 2, 3, 6, 7, 9, 10 • 1st trigger: sequence converted 0, 1, 2. An EOC event is generated at each conversion. • 2nd trigger: sequence converted 3, 6, 7. An EOC event is generated at each conversion •...
Page 366: Channel-Wise Programmable Sampling Time
Analog-to-digital converter (ADC) RM0390 Figure 76. Right alignment of 12-bit data Figure 77. Left alignment of 12-bit data Special case: when left-aligned, the data are aligned on a half-word basis except when the resolution is set to 6-bit. in that case, the data are aligned on a byte basis as shown in Figure Figure 78.
Page 367: Conversion On External Trigger And Trigger Polarity
RM0390 Analog-to-digital converter (ADC) 13.6 Conversion on external trigger and trigger polarity Conversion can be triggered by an external event (e.g. timer capture, EXTI line). If the EXTEN[1:0] control bits (for a regular conversion) or JEXTEN[1:0] bits (for an injected conversion) are different from “0b00”, then external events are able to trigger a conversion with the selected polarity.
Page 368: Fast Conversion Mode
Analog-to-digital converter (ADC) RM0390 Table 88 gives the possible external trigger for injected conversion. Table 88. External trigger for injected channels Source Connection type JEXTSEL[3:0] TIM1_CH4 event 0000 TIM1_TRGO event 0001 TIM2_CH1 event 0010 TIM2_TRGO event 0011 TIM3_CH2 event 0100 TIM3_CH4 event 0101 TIM4_CH1 event...
Page 369: Data Management
RM0390 Analog-to-digital converter (ADC) 13.8 Data management 13.8.1 Using the DMA Since converted regular channel values are stored into a unique data register, it is useful to use DMA for conversion of more than one regular channel. This avoids the loss of the data already stored in the ADC_DR register.
Page 370: Conversions Without Dma And Without Overrun Detection
Analog-to-digital converter (ADC) RM0390 13.8.3 Conversions without DMA and without overrun detection It may be useful to let the ADC convert one or more channels without reading the data each time (if there is an analog watchdog for instance). For that, the DMA must be disabled (DMA = 0) and the EOC bit must be set at the end of a sequence only (EOCS = 0).
Page 371: Figure 79. Multi Adc Block Diagram (1)
RM0390 Analog-to-digital converter (ADC) Figure 79. Multi ADC block diagram 1. Although external triggers are present on ADC2 and ADC3 they are not shown in this diagram. 2. In the Dual ADC mode, the ADC3 slave part is not present. 3.
Page 372 Analog-to-digital converter (ADC) RM0390 • DMA requests in Multi ADC mode: In Multi ADC mode the DMA may be configured to transfer converted data in three different modes. In all cases, the DMA streams to use are those connected to the ADC: –...
Page 373: Injected Simultaneous Mode
RM0390 Analog-to-digital converter (ADC) – DMA mode 3: This mode is similar to the DMA mode 2. The only differences are that the on each DMA request (two data items are available) two bytes representing two ADC converted data items are transferred as a half-word. The data transfer order is similar to that of the DMA mode 2.
Page 374: Regular Simultaneous Mode
Analog-to-digital converter (ADC) RM0390 Dual ADC mode At the end of conversion event on ADC1 or ADC2: • The converted data are stored into the ADC_JDRx registers of each ADC interface. • A JEOC interrupt is generated (if enabled on one of the two ADC interfaces) when the ADC1/ADC2’s injected channels have all been converted.
Page 375: Interleaved Mode
RM0390 Analog-to-digital converter (ADC) Dual ADC mode At the end of conversion event on ADC1 or ADC2: • A 32-bit DMA transfer request is generated (if DMA[1:0] bits in the ADC_CCR register are equal to 0b10). This request transfers the ADC2 converted data stored in the upper half-word of the ADC_CDR 32-bit register to the SRAM and then the ADC1 converted data stored in the lower half-word of ADC_CCR to the SRAM.
Page 376: Figure 84. Interleaved Mode On 1 Channel In Continuous Conversion Mode: Dual Adc Mode
Analog-to-digital converter (ADC) RM0390 The minimum delay which separates 2 conversions in interleaved mode is configured in the DELAY bits in the ADC_CCR register. However, an ADC cannot start a conversion if the complementary ADC is still sampling its input (only one ADC can sample the input signal at a given time).
Page 377: Alternate Trigger Mode
RM0390 Analog-to-digital converter (ADC) first converted data stored in the lower half-word of the ADC_CDR 32-bit register to SRAM, then it transfers the second converted data stored in ADC_CDR’s upper half-word to SRAM. The sequence is the following: • 1st request: ADC_CDR[31:0] = ADC2_DR[15:0] | ADC1_DR[15:0] •...
Page 378: Figure 86. Alternate Trigger: Injected Group Of Each Adc
Analog-to-digital converter (ADC) RM0390 A JEOC interrupt, if enabled, is generated after all injected ADC2 channels in the group have been converted. If another external trigger occurs after all injected channels in the group have been converted then the alternate trigger process restarts by converting the injected ADC1 channels in the group.
Page 379: Combined Regular/Injected Simultaneous Mode
RM0390 Analog-to-digital converter (ADC) A JEOC interrupt, if enabled, is generated after all injected ADC1 channels in the group have been converted. A JEOC interrupt, if enabled, is generated after all injected ADC2 channels in the group have been converted. A JEOC interrupt, if enabled, is generated after all injected ADC3 channels in the group have been converted.
Page 380: Temperature Sensor
Analog-to-digital converter (ADC) RM0390 Otherwise, the ADC with the shortest sequence may restart while the ADC with the longest sequence is completing the previous conversions. If the conversion sequence is interrupted (for instance when DMA end of transfer occurs), the multi-ADC sequencer must be reset by configuring it in independent mode first (bits DUAL[4:0] = 00000) before reprogramming the interleaved mode.
Page 381: Figure 91. Temperature Sensor And Vrefint Channel Block Diagram
RM0390 Analog-to-digital converter (ADC) When not in use, the sensor can be put in power down mode. Note: The TSVREFE bit must be set to enable the conversion of both internal channels: the ADC1_IN18 (temperature sensor) and the ADC1_IN17 (VREFINT). Main features •...
Page 382: Battery Charge Monitoring
Analog-to-digital converter (ADC) RM0390 Note: The sensor has a startup time after waking from power down mode before it can output at the correct level. The ADC also has a startup time after power-on, so to minimize SENSE the delay, the ADON and TSVREFE bits should be set at the same time. The temperature sensor output voltage changes linearly with temperature.
Page 383: Adc Registers
RM0390 Analog-to-digital converter (ADC) 13.13 ADC registers Refer to for a list of abbreviations used in register descriptions. Section 1.1 on page 51 The peripheral registers must be written at word level (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). 13.13.1 ADC status register (ADC_SR) Address offset: 0x00...
Page 384: Adc Control Register 1 (Adc_Cr1)
Analog-to-digital converter (ADC) RM0390 13.13.2 ADC control register 1 (ADC_CR1) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. OVRIE AWDEN JAWDEN Res. Res. Res. Res. Res. Res. DISCNUM[2:0] JDISCEN DISCEN JAUTO AWDSGL SCAN JEOCIE AWDIE EOCIE AWDCH[4:0] Bits 31:27 Reserved, must be kept at reset value.
Page 385 RM0390 Analog-to-digital converter (ADC) Bit 11 DISCEN: Discontinuous mode on regular channels This bit is set and cleared by software to enable/disable Discontinuous mode on regular channels. 0: Discontinuous mode on regular channels disabled 1: Discontinuous mode on regular channels enabled Bit 10 JAUTO: Automatic injected group conversion This bit is set and cleared by software to enable/disable automatic injected group conversion after regular group conversion.
Page 386: Adc Control Register 2 (Adc_Cr2)
Analog-to-digital converter (ADC) RM0390 13.13.3 ADC control register 2 (ADC_CR2) Address offset: 0x08 Reset value: 0x0000 0000 Res. SWSTART EXTEN EXTSEL[3:0] Res. JSWSTART JEXTEN JEXTSEL[3:0] Res. Res. Res. Res. ALIGN EOCS Res. Res. Res. Res. Res. Res. CONT ADON Bit 31 Reserved, must be kept at reset value. Bit 30 SWSTART: Start conversion of regular channels This bit is set by software to start conversion and cleared by hardware as soon as the conversion starts.
Page 387 RM0390 Analog-to-digital converter (ADC) Bits 21:20 JEXTEN: External trigger enable for injected channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group. 00: Trigger detection disabled 01: Trigger detection on the rising edge 10: Trigger detection on the falling edge 11: Trigger detection on both the rising and falling edges Bits 19:16 JEXTSEL[3:0]: External event select for injected group...
Page 388: Adc Sample Time Register 1 (Adc_Smpr1)
Analog-to-digital converter (ADC) RM0390 Bits 7:2 Reserved, must be kept at reset value. Bit 1 CONT: Continuous conversion This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared. 0: Single conversion mode 1: Continuous conversion mode Bit 0 ADON: A/D Converter ON / OFF This bit is set and cleared by software.
Page 389: Adc Injected Channel Data Offset Register X (Adc_Jofrx) (X=1
RM0390 Analog-to-digital converter (ADC) Bits 31:30 Reserved, must be kept at reset value. Bits 29:0 SMPx[2:0]: Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: 000: 3 cycles 001: 15 cycles 010: 28 cycles...
Page 390: Adc Watchdog Lower Threshold Register (Adc_Ltr)
Analog-to-digital converter (ADC) RM0390 Note: The software can write to these registers when an ADC conversion is ongoing. The programmed value will be effective when the next conversion is complete. Writing to this register is performed with a write delay that can create uncertainty on the effective time at which the new value is programmed.
Page 391: Adc Regular Sequence Register 2 (Adc_Sqr2)
RM0390 Analog-to-digital converter (ADC) Bits 31:24 Reserved, must be kept at reset value. Bits 23:20 L[3:0]: Regular channel sequence length These bits are written by software to define the total number of conversions in the regular channel conversion sequence. 0000: 1 conversion 0001: 2 conversions 1111: 16 conversions Bits 19:15 SQ16[4:0]: 16th conversion in regular sequence...
Page 392: Adc Regular Sequence Register 3 (Adc_Sqr3)
Analog-to-digital converter (ADC) RM0390 13.13.11 ADC regular sequence register 3 (ADC_SQR3) Address offset: 0x34 Reset value: 0x0000 0000 Res. Res. SQ6[4:0] SQ5[4:0] SQ4[4:1] SQ4_0 SQ3[4:0] SQ2[4:0] SQ1[4:0] Bits 31:30 Reserved, must be kept at reset value. Bits 29:25 SQ6[4:0]: 6th conversion in regular sequence These bits are written by software with the channel number (0..18) assigned as the 6th in the sequence to be converted.
Page 393: Adc Injected Sequence Register (Adc_Jsqr)
RM0390 Analog-to-digital converter (ADC) 13.13.12 ADC injected sequence register (ADC_JSQR) Address offset: 0x38 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. JL[1:0] JSQ4[4:1] JSQ4[0] JSQ3[4:0] JSQ2[4:0] JSQ1[4:0] Bits 31:22 Reserved, must be kept at reset value. Bits 21:20 JL[1:0]: Injected sequence length These bits are written by software to define the total number of conversions in the injected channel conversion sequence.
Page 394: Adc Regular Data Register (Adc_Dr)
Analog-to-digital converter (ADC) RM0390 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 JDATA[15:0]: Injected data These bits are read-only. They contain the conversion result from injected channel x. The data are left -or right-aligned as shown in Figure 76 Figure 13.13.14 ADC regular data register (ADC_DR)
Page 395: Adc Common Control Register (Adc_Ccr)
RM0390 Analog-to-digital converter (ADC) Bit 19 JSTRT3: Injected channel Start flag of ADC3 This bit is a copy of the JSTRT bit in the ADC3_SR register. Bit 18 JEOC3: Injected channel end of conversion of ADC3 This bit is a copy of the JEOC bit in the ADC3_SR register. Bit 17 EOC3: End of conversion of ADC3 This bit is a copy of the EOC bit in the ADC3_SR register.
Page 396 Analog-to-digital converter (ADC) RM0390 Res. Res. Res. Res. Res. Res. Res. Res. TSVREFE VBATE Res. Res. Res. Res. ADCPRE DMA[1:0] Res. DELAY[3:0] Res. Res. Res. MULTI[4:0] Bits 31:24 Reserved, must be kept at reset value. Bit 23 TSVREFE: Temperature sensor and V enable REFINT This bit is set and cleared by software to enable/disable the temperature sensor and the...
Page 397 RM0390 Analog-to-digital converter (ADC) Bits 11:8 DELAY: Delay between 2 sampling phases Set and cleared by software. These bits are used in dual or triple interleaved modes. 0000: 5 * T ADCCLK 0001: 6 * T ADCCLK 0010: 7 * T ADCCLK 1111: 20 * T ADCCLK...
Page 398: 13.13.17 Adc Common Regular Data Register For Dual And Triple Modes
Analog-to-digital converter (ADC) RM0390 13.13.17 ADC common regular data register for dual and triple modes (ADC_CDR) Address offset: 0x08 (this offset address is relative to ADC1 base address + 0x300) Reset value: 0x0000 0000 DATA2[15:0] DATA1[15:0] Bits 31:16 DATA2[15:0]: 2nd data item of a pair of regular conversions –...
Page 399 RM0390 Analog-to-digital converter (ADC) Table 91. ADC register map and reset values for each ADC (continued) Offset Register JEXTSEL ADC_CR2 EXTSEL [3:0] [3:0] 0x08 Reset value ADC_SMPR1 Sample time bits SMPx_x 0x0C Reset value ADC_SMPR2 Sample time bits SMPx_x 0x10 Reset value ADC_JOFR1 JOFFSET1[11:0]...
Page 400: Table 92. Adc Register Map And Reset Values (Common Adc Registers)
Analog-to-digital converter (ADC) RM0390 Table 92. ADC register map and reset values (common ADC registers) Offset Register ADC_CSR 0x00 Reset value ADC3 ADC2 ADC1 ADC_CCR DELAY [3:0] MULTI [4:0] 0x04 Reset value ADC_CDR Regular DATA2[15:0] Regular DATA1[15:0] 0x08 Reset value Refer to Section 2.2.2 on page 56 for the register boundary addresses.
Page 401: Digital-To-Analog Converter (Dac)
RM0390 Digital-to-analog converter (DAC) Digital-to-analog converter (DAC) 14.1 DAC introduction The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In 12-bit mode, the data could be left- or right-aligned.
Page 402: Dac Functional Description
Digital-to-analog converter (DAC) RM0390 Figure 92. DAC channel block diagram Table 93. DAC pins Name Signal type Remarks Input, analog reference The higher/positive reference voltage for the DAC, REF+ positive 1.8 V ≤ V ≤ V REF+ Input, analog supply Analog power supply Input, analog supply ground Ground for analog power supply...
Page 403: Dac Output Buffer Enable
RM0390 Digital-to-analog converter (DAC) Note: The ENx bit enables the analog DAC Channelx macrocell only. The DAC Channelx digital interface is enabled even if the ENx bit is reset. 14.3.2 DAC output buffer enable The DAC integrates two output buffers that can be used to reduce the output impedance, and to drive external loads directly without having to add an external operational amplifier.
Page 404: Dac Conversion
Digital-to-analog converter (DAC) RM0390 Figure 94. Data registers in single DAC channel mode • Dual DAC channels, there are three possibilities: – 8-bit right alignment: data for DAC channel1 to be loaded into the DAC_DHR8RD [7:0] bits (stored into the DHR1[11:4] bits) and data for DAC channel2 to be loaded into the DAC_DHR8RD [15:8] bits (stored into the DHR2[11:4] bits) –...
Page 405: Dac Output Voltage
RM0390 Digital-to-analog converter (DAC) When DAC_DORx is loaded with the DAC_DHRx contents, the analog output voltage becomes available after a time t that depends on the power supply voltage and the SETTLING analog output load. Figure 96. Timing diagram for conversion with trigger disabled TEN = 0 14.3.5 DAC output voltage Digital inputs are converted to output voltages on a linear conversion between 0 and V...
Page 406: Dma Request
Digital-to-analog converter (DAC) RM0390 If the software trigger is selected, the conversion starts once the SWTRIG bit is set. SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the DAC_DHRx register contents. Note: TSELx[2:0] bit cannot be changed when the ENx bit is set. When software trigger is selected, the transfer from the DAC_DHRx register to the DAC_DORx register takes only one APB1 clock cycle.
Page 407: Triangle-Wave Generation
RM0390 Digital-to-analog converter (DAC) Figure 97. DAC LFSR register calculation algorithm The LFSR value, that may be masked partially or totally by means of the MAMPx[3:0] bits in the DAC_CR register, is added up to the DAC_DHRx contents without overflow and this value is then stored into the DAC_DORx register.
Page 408: Dual Dac Channel Conversion
Digital-to-analog converter (DAC) RM0390 It is possible to reset triangle wave generation by resetting the WAVEx[1:0] bits. Figure 99. DAC triangle wave generation Figure 100. DAC conversion (SW trigger enabled) with triangle wave generation Note: The DAC trigger must be enabled for noise generation by setting the TENx bit in the DAC_CR register.
Page 409: Independent Trigger Without Wave Generation
RM0390 Digital-to-analog converter (DAC) 14.4.1 Independent trigger without wave generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits •...
Page 410: Independent Trigger With Single Triangle Generation
Digital-to-analog converter (DAC) RM0390 14.4.4 Independent trigger with single triangle generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits •...
Page 411: Simultaneous Trigger Without Wave Generation
RM0390 Digital-to-analog converter (DAC) 14.4.7 Simultaneous trigger without wave generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits •...
Page 412: Simultaneous Trigger With Single Triangle Generation
Digital-to-analog converter (DAC) RM0390 14.4.10 Simultaneous trigger with single triangle generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits •...
Page 413: Dac Registers
RM0390 Digital-to-analog converter (DAC) 14.5 DAC registers Refer to Section 1 on page 51 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32 bits). 14.5.1 DAC control register (DAC_CR) Address offset: 0x00 Reset value: 0x0000 0000 DMAU Res.
Page 414 Digital-to-analog converter (DAC) RM0390 Bits 21:19 TSEL2[2:0]: DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 000: Timer 6 TRGO event 001: Timer 8 TRGO event 010: Timer 7 TRGO event 011: Timer 5 TRGO event 100: Timer 2 TRGO event 101: Timer 4 TRGO event 110: External line9...
Page 415 RM0390 Digital-to-analog converter (DAC) Bits 11:8 MAMP1[3:0]: DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. 0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1 0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15...
Page 416: Dac Software Trigger Register (Dac_Swtrigr)
Digital-to-analog converter (DAC) RM0390 14.5.2 DAC software trigger register (DAC_SWTRIGR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 417: Dac Channel1 12-Bit Left Aligned Data Holding Register
RM0390 Digital-to-analog converter (DAC) 14.5.4 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) Address offset: 0x0C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DACC1DHR[11:0] Res. Res. Res.
Page 418: Dac Channel2 12-Bit Right Aligned Data Holding Register (Dac_Dhr12R2)
Digital-to-analog converter (DAC) RM0390 14.5.6 DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) Address offset: 0x14 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 419: Dual Dac 12-Bit Right-Aligned Data Holding Register (Dac_Dhr12Rd)
RM0390 Digital-to-analog converter (DAC) Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2. 14.5.9 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) Address offset: 0x20 Reset value: 0x0000 0000...
Page 420: Dual Dac 8-Bit Right Aligned Data Holding Register
Digital-to-analog converter (DAC) RM0390 14.5.11 DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) Address offset: 0x28 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DACC2DHR[7:0] DACC1DHR[7:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:8 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2.
Page 421: Dac Status Register (Dac_Sr)
RM0390 Digital-to-analog converter (DAC) Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 DACC2DOR[11:0]: DAC channel2 data output These bits are read-only, they contain data output for DAC channel2. 14.5.14 DAC status register (DAC_SR) Address offset: 0x34 Reset value: 0x0000 0000 Res.
Page 422: Dac Register Map
Digital-to-analog converter (DAC) RM0390 14.5.15 DAC register map Table 95 summarizes the DAC registers. Table 95. DAC register map Register Offset name DAC_CR MAMP2[3:0] MAMP1[3:0] 0x00 Reset value DAC_ SWTRIGR 0x04 Reset value DAC_ DACC1DHR[11:0] DHR12R1 0x08 Reset value DAC_ DACC1DHR[11:0] DHR12L1 0x0C...
Page 423: Digital Camera Interface (Dcmi)
RM0390 Digital camera interface (DCMI) Digital camera interface (DCMI) 15.1 DCMI introduction The digital camera is a synchronous parallel interface able to receive a high-speed data flow from an external 8-, 10-, 12- or 14-bit CMOS camera module. It supports different data formats: YCbCr4:2:2/RGB565 progressive video and compressed data (JPEG).
Page 424: Dcmi Functional Overview
Digital camera interface (DCMI) RM0390 15.4 DCMI functional overview The digital camera interface is a synchronous parallel interface that can receive high-speed (up to 54 Mbytes/s) data flows. It consists of up to 14 data lines (D13-D0) and a pixel clock line (DCMI_PIXCLK).
Page 425: Dma Interface
RM0390 Digital camera interface (DCMI) Figure 102. Top-level block diagram 15.4.2 DMA interface The DMA interface is active when the CAPTURE bit in the DCMI_CR register is set. A DMA request is generated each time the camera interface receives a complete 32-bit data block in its register.
Page 426: Table 97. Positioning Of Captured Data Bytes In 32-Bit Words (8-Bit Width)
Digital camera interface (DCMI) RM0390 Figure 103. DCMI signal waveforms 1. The capture edge of DCMI_PIXCLK is the falling edge, the active state of DCMI_HSYNC and DCMI_VSYNC is 1. 2. DCMI_HSYNC and DCMI_VSYNC can change states at the same time. 8-bit data When EDM[1:0] in DCMI_CR are programmed to “00”...
Page 427: Synchronization
RM0390 Digital camera interface (DCMI) 12-bit data When EDM[1:0] in DCMI_CR are programmed to “10”, the camera interface captures the 12-bit data at its input DCMI_D[0..11] and stores them as the 12 least significant bits of a 16- bit word. The remaining most significant bits are cleared to zero. So, in this case a 32-bit data word is made up every two pixel clock cycles.
Page 428: Figure 104. Timing Diagram
Digital camera interface (DCMI) RM0390 Figure 104. Timing diagram Hardware synchronization mode In hardware synchronization mode, the two synchronization signals (DCMI_HSYNC/DCMI_VSYNC) are used. Depending on the camera module/mode, data may be transmitted during horizontal/vertical synchronization periods. The DCMI_HSYNC/DCMI_VSYNC signals act like blanking signals since all the data received during DCMI_HSYNC/DCMI_VSYNC active periods are ignored.
Page 429 RM0390 Digital camera interface (DCMI) Note: Camera modules can have 8 such codes (in interleaved mode). For this reason, the interleaved mode is not supported by the camera interface (otherwise, every other half-frame would be discarded). • Mode 2 Four embedded codes signal the following events –...
Page 430: Capture Modes
Digital camera interface (DCMI) RM0390 15.4.5 Capture modes This interface supports two types of capture: snapshot (single frame) and continuous grab. Snapshot mode (single frame) In this mode, a single frame is captured (CM = ‘1’ in the DCMI_CR register). After the CAPTURE bit is set in DCMI_CR, the interface waits for the detection of a start of frame before sampling the data.
Page 431: Crop Feature
RM0390 Digital camera interface (DCMI) Figure 106. Frame capture waveforms in continuous grab mode 1. Here, the active state of DCMI_HSYNC and DCMI_VSYNC is 1. 2. DCMI_HSYNC and DCMI_VSYNC can change states at the same time. In continuous grab mode, you can configure the FCRC bits in DCMI_CR to grab all pictures, every second picture or one out of four pictures to decrease the frame capture rate.
Page 432: Jpeg Format
Digital camera interface (DCMI) RM0390 If the DCMI_VSYNC signal goes active before the number of lines is specified in the DCMI_CWSIZE register, then the capture stops and an IT_FRAME interrupt is generated when enabled. Figure 108. Data capture waveforms 1. Here, the active state of DCMI_HSYNC and DCMI_VSYNC is 1. 2.
Page 433: Data Format Description
RM0390 Digital camera interface (DCMI) 15.5 Data format description 15.5.1 Data formats Three types of data are supported: • 8-bit progressive video: either monochrome or raw Bayer format • YCbCr 4:2:2 progressive video • RGB565 progressive video. A pixel coded in 16 bits (5 bits for blue, 5 bits for red, 6 bits for green) takes two clock cycles to be transferred.
Page 434: Rgb Format
Digital camera interface (DCMI) RM0390 15.5.3 RGB format Characteristics: • Raster format • • Interleaved: one buffer: R, G & B interleaved: BRGBRGBRG, etc. • Optimized for display output The RGB planar format is compatible with standard OS frame buffer display formats. Only 16 BPP (bits per pixel): RGB565 (2 pixels per 32-bit word) is supported.
Page 435: Half Resolution Image Extraction
RM0390 Digital camera interface (DCMI) pixel , encoded in 8 bits, is stored as shown in Table 104. The result is a monochrome image having the same resolution as the original YCbCr data. Table 104. Data storage in YCbCr progressive video format - Y extraction mode Byte address 31:24 23:16...
Page 436 Digital camera interface (DCMI) RM0390 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OELS OEBS BSM[1:0] Res. ENABLE Res. Res. EDM[1:0] FCRC[1:0] VSPOL HSPOL PCKPOL JPEG CROP CAPTURE Bits 31:21 Reserved, must be kept at reset value. Bit 20 OELS: Odd/Even Line Select (Line Select Start) This bit works in conjunction with LSM field (LSM = 1) 0: Interface captures first line after the frame start, second one being dropped...
Page 437 RM0390 Digital camera interface (DCMI) Bit 7 VSPOL: Vertical synchronization polarity This bit indicates the level on the DCMI_VSYNC pin when the data are not valid on the parallel interface. 0: DCMI_VSYNC active low 1: DCMI_VSYNC active high Bit 6 HSPOL: Horizontal synchronization polarity This bit indicates the level on the DCMI_HSYNC pin when the data are not valid on the parallel interface.
Page 438 Digital camera interface (DCMI) RM0390 Bit 0 CAPTURE: Capture enable 0: Capture disabled. 1: Capture enabled. The camera interface waits for the first start of frame, then a DMA request is generated to transfer the received data into the destination memory. In snapshot mode, the CAPTURE bit is automatically cleared at the end of the 1st frame received.
Page 439: Dcmi Status Register (Dcmi_Sr)
RM0390 Digital camera interface (DCMI) 15.7.2 DCMI status register (DCMI_SR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 440: Dcmi Raw Interrupt Status Register (Dcmi_Ris)
Digital camera interface (DCMI) RM0390 15.7.3 DCMI raw interrupt status register (DCMI_RIS) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LINE VSYNC FRAME Res. Res. Res.
Page 441: Dcmi Interrupt Enable Register (Dcmi_Ier)
RM0390 Digital camera interface (DCMI) 15.7.4 DCMI interrupt enable register (DCMI_IER) Address offset: 0x0C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LINE VSYNC FRAME Res. Res. Res. Res.
Page 442: Dcmi Masked Interrupt Status Register (Dcmi_Mis)
Digital camera interface (DCMI) RM0390 15.7.5 DCMI masked interrupt status register (DCMI_MIS) This DCMI_MIS register is a read-only register. When read, it returns the current masked status value (depending on the value in DCMI_IER) of the corresponding interrupt. A bit in this register is set if the corresponding enable bit in DCMI_IER is set and the corresponding bit in DCMI_RIS is set.
Page 443: Dcmi Interrupt Clear Register (Dcmi_Icr)
RM0390 Digital camera interface (DCMI) 15.7.6 DCMI interrupt clear register (DCMI_ICR) Address offset: 0x14 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LINE VSYNC FRAME Res. Res. Res. Res.
Page 444: Dcmi Embedded Synchronization Code Register (Dcmi_Escr)
Digital camera interface (DCMI) RM0390 15.7.7 DCMI embedded synchronization code register (DCMI_ESCR) Address offset: 0x18 Reset value: 0x0000 0000 Bits 31:24 FEC: Frame end delimiter code This byte specifies the code of the frame end delimiter. The code consists of 4 bytes in the form of 0xFF, 0x00, 0x00, FEC.
Page 445: Dcmi Embedded Synchronization Unmask Register (Dcmi_Esur)
RM0390 Digital camera interface (DCMI) 15.7.8 DCMI embedded synchronization unmask register (DCMI_ESUR) Address offset: 0x1C Reset value: 0x0000 0000 Bits 31:24 FEU: Frame end delimiter unmask This byte specifies the mask to be applied to the code of the frame end delimiter. 0: The corresponding bit in the FEC byte in DCMI_ESCR is masked while comparing the frame end delimiter with the received data.
Page 446: Dcmi Crop Window Start (Dcmi_Cwstrt)
Digital camera interface (DCMI) RM0390 15.7.9 DCMI crop window start (DCMI_CWSTRT) Address offset: 0x20 Reset value: 0x0000 0000 Res. Res. Res. VST[12:0] Res. Res. HOFFCNT[13:0] Bits 31:29 Reserved, must be kept at reset value. Bits 28:16 VST[12:0]: Vertical start line count The image capture starts with this line number.
Page 447: Dcmi Data Register (Dcmi_Dr)
RM0390 Digital camera interface (DCMI) Bits 15:14 Reserved, must be kept at reset value. Bits 13:0 CAPCNT[13:0]: Capture count This value gives the number of pixel clocks to be captured from the starting point on the same line. It value should corresponds to word-aligned data for different widths of parallel interfaces.
Page 448: Dcmi Register Map
Digital camera interface (DCMI) RM0390 15.7.12 DCMI register map Table 106 summarizes the DCMI registers. Table 106. DCMI register map and reset values Register Offset name DCMI_CR EDM FCRC 0x00 Reset value DCMI_SR 0x04 Reset value DCMI_RIS 0x08 Reset value DCMI_IER 0x0C Reset value...
Page 449: Advanced-Control Timers (Tim1&Tim8)
RM0390 Advanced-control timers (TIM1&TIM8) Advanced-control timers (TIM1&TIM8) 16.1 TIM1&TIM8 introduction The advanced-control timers (TIM1&TIM8) consist of a 16-bit auto-reload counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse length of input signals (input capture) or generating output waveforms (output compare, PWM, complementary PWM with dead-time insertion).
Page 450: Figure 110. Advanced-Control Timer Block Diagram
Advanced-control timers (TIM1&TIM8) RM0390 Figure 110. Advanced-control timer block diagram 450/1328 RM0390 Rev 4...
Page 451: Tim1&Tim8 Functional Description
RM0390 Advanced-control timers (TIM1&TIM8) 16.3 TIM1&TIM8 functional description 16.3.1 Time-base unit The main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler.
Page 452: Figure 111. Counter Timing Diagram With Prescaler Division Change From 1 To 2
Advanced-control timers (TIM1&TIM8) RM0390 Figure 111. Counter timing diagram with prescaler division change from 1 to 2 Figure 112. Counter timing diagram with prescaler division change from 1 to 4 452/1328 RM0390 Rev 4...
Page 453: Counter Modes
RM0390 Advanced-control timers (TIM1&TIM8) 16.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. If the repetition counter is used, the update event (UEV) is generated after upcounting is repeated for the number of times programmed in the repetition counter register plus one (TIMx_RCR+1).
Page 454: Figure 114. Counter Timing Diagram, Internal Clock Divided By 2
Advanced-control timers (TIM1&TIM8) RM0390 Figure 114. Counter timing diagram, internal clock divided by 2 Figure 115. Counter timing diagram, internal clock divided by 4 Figure 116. Counter timing diagram, internal clock divided by N 454/1328 RM0390 Rev 4...
Page 455: Figure 117. Counter Timing Diagram, Update Event When Arpe=0
RM0390 Advanced-control timers (TIM1&TIM8) Figure 117. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) Figure 118. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) RM0390 Rev 4 455/1328...
Page 456 Advanced-control timers (TIM1&TIM8) RM0390 Downcounting mode In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event. If the repetition counter is used, the update event (UEV) is generated after downcounting is repeated for the number of times programmed in the repetition counter register plus one (TIMx_RCR+1).
Page 457: Figure 119. Counter Timing Diagram, Internal Clock Divided By 1
RM0390 Advanced-control timers (TIM1&TIM8) Figure 119. Counter timing diagram, internal clock divided by 1 Figure 120. Counter timing diagram, internal clock divided by 2 RM0390 Rev 4 457/1328...
Page 458: Figure 121. Counter Timing Diagram, Internal Clock Divided By 4
Advanced-control timers (TIM1&TIM8) RM0390 Figure 121. Counter timing diagram, internal clock divided by 4 Figure 122. Counter timing diagram, internal clock divided by N 458/1328 RM0390 Rev 4...
Page 459: Figure 123. Counter Timing Diagram, Update Event When Repetition Counter Is Not Used
RM0390 Advanced-control timers (TIM1&TIM8) Figure 123. Counter timing diagram, update event when repetition counter is not used Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register) – 1, generates a counter overflow event, then counts from the auto- reload value down to 1 and generates a counter underflow event.
Page 460: Figure 124. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr = 0X6
Advanced-control timers (TIM1&TIM8) RM0390 DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): •...
Page 461: Figure 126. Counter Timing Diagram, Internal Clock Divided By 4, Timx_Arr=0X36
RM0390 Advanced-control timers (TIM1&TIM8) Figure 126. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 Center-aligned mode 2 or 3 is used with an UIF on overflow. Figure 127. Counter timing diagram, internal clock divided by N RM0390 Rev 4 461/1328...
Page 462: Repetition Counter
Advanced-control timers (TIM1&TIM8) RM0390 Figure 128. Counter timing diagram, update event with ARPE=1 (counter underflow) Figure 129. Counter timing diagram, update event with ARPE=1 (counter overflow) 16.3.3 Repetition counter Section 16.3.1: Time-base unit describes how the update event (UEV) is generated with respect to the counter overflows/underflows.
Page 463 RM0390 Advanced-control timers (TIM1&TIM8) The repetition counter is decremented: • At each counter overflow in upcounting mode, • At each counter underflow in downcounting mode, • At each counter overflow and at each counter underflow in center-aligned mode. Although this limits the maximum number of repetition to 128 PWM cycles, it makes it possible to update the duty cycle twice per PWM period.
Page 464: Figure 130. Update Rate Examples Depending On Mode And Timx_Rcr Register Settings
Advanced-control timers (TIM1&TIM8) RM0390 Figure 130. Update rate examples depending on mode and TIMx_RCR register settings 464/1328 RM0390 Rev 4...
Page 465: Clock Selection
RM0390 Advanced-control timers (TIM1&TIM8) 16.3.4 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin • External clock mode2: external trigger input ETR • Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for example, you can configure Timer 1 to act as a prescaler for Timer 2.
Page 466: Figure 132. Ti2 External Clock Connection Example
Advanced-control timers (TIM1&TIM8) RM0390 Figure 132. TI2 external clock connection example For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register.
Page 467: Figure 133. Control Circuit In External Clock Mode 1
RM0390 Advanced-control timers (TIM1&TIM8) Figure 133. Control circuit in external clock mode 1 External clock source mode 2 This mode is selected by writing ECE=1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR. Figure 134 gives an overview of the external trigger input block.
Page 468: Capture/Compare Channels
Advanced-control timers (TIM1&TIM8) RM0390 As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
Page 469: Figure 136. Capture/Compare Channel (Example: Channel 1 Input Stage)
RM0390 Advanced-control timers (TIM1&TIM8) Figure 136. Capture/compare channel (example: channel 1 input stage) The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain. Figure 137. Capture/compare channel 1 main circuit RM0390 Rev 4 469/1328...
Page 470: Figure 138. Output Stage Of Capture/Compare Channel (Channels 1 To 3)
Advanced-control timers (TIM1&TIM8) RM0390 Figure 138. Output stage of capture/compare channel (channels 1 to 3) Figure 139. Output stage of capture/compare channel (channel 4) The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register.
Page 471: Input Capture Mode
RM0390 Advanced-control timers (TIM1&TIM8) 16.3.6 Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled.
Page 472: Pwm Input Mode
Advanced-control timers (TIM1&TIM8) RM0390 16.3.7 PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. • These 2 ICx signals are active on edges with opposite polarity. •...
Page 473: Output Compare Mode
RM0390 Advanced-control timers (TIM1&TIM8) To force an output compare signal (OCXREF/OCx) to its active level, you just need to write 101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit. For example: CCxP=0 (OCx active high) =>...
Page 474: Pwm Mode
Advanced-control timers (TIM1&TIM8) RM0390 Figure 141. Output compare mode, toggle on OC1. 16.3.10 PWM mode Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
Page 475: Figure 142. Edge-Aligned Pwm Waveforms (Arr=8)
RM0390 Advanced-control timers (TIM1&TIM8) PWM edge-aligned mode • Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to Upcounting mode. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT <...
Page 476: Figure 143. Center-Aligned Pwm Waveforms (Arr=8)
Advanced-control timers (TIM1&TIM8) RM0390 Figure 143 shows some center-aligned PWM waveforms in an example where: • TIMx_ARR=8, • PWM mode is the PWM mode 1, • The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for CMS=01 in TIMx_CR1 register. Figure 143.
Page 477: Complementary Outputs And Dead-Time Insertion
RM0390 Advanced-control timers (TIM1&TIM8) Hints on using center-aligned mode: • When starting in center-aligned mode, the current up-down configuration is used. It means that the counter counts up or down depending on the value written in the DIR bit in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software.
Page 478: Figure 144. Complementary Output With Dead-Time Insertion
Advanced-control timers (TIM1&TIM8) RM0390 Figure 144. Complementary output with dead-time insertion. Figure 145. Dead-time waveforms with delay greater than the negative pulse. Figure 146. Dead-time waveforms with delay greater than the positive pulse. The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the TIMx_BDTR register.
Page 479: Using The Break Function
RM0390 Advanced-control timers (TIM1&TIM8) are to have both outputs at inactive level or both outputs active and complementary with dead-time. Note: When only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented and becomes active as soon as OCxREF is high. For example, if CCxNP=0 then OCxN=OCxRef. On the other hand, when both OCx and OCxN are enabled (CCxE=CCxNE=1) OCx becomes active when OCxREF is high whereas OCxN is complemented and becomes active when OCxREF is low.
Page 480 Advanced-control timers (TIM1&TIM8) RM0390 active level together. Note that because of the resynchronization on MOE, the dead-time duration is a bit longer than usual (around 2 ck_tim clock cycles). – If OSSI=0 then the timer releases the enable outputs else the enable outputs remain or become high as soon as one of the CCxE or CCxNE bits is high.
Page 481: Figure 147. Output Behavior In Response To A Break
RM0390 Advanced-control timers (TIM1&TIM8) Figure 147. Output behavior in response to a break. RM0390 Rev 4 481/1328...
Page 482: Clearing The Ocxref Signal On An External Event
Advanced-control timers (TIM1&TIM8) RM0390 16.3.13 Clearing the OCxREF signal on an external event The OCxREF signal for a given channel can be driven Low by applying a High level to the ETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to ‘1’). The OCxREF signal remains Low until the next update event, UEV, occurs.
Page 483: 6-Step Pwm Generation
RM0390 Advanced-control timers (TIM1&TIM8) 16.3.14 6-step PWM generation When complementary outputs are used on a channel, preload bits are available on the OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the COM commutation event. Thus you can program in advance the configuration for the next step and change the configuration of all the channels at the same time.
Page 484: One-Pulse Mode
Advanced-control timers (TIM1&TIM8) RM0390 16.3.15 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller.
Page 485: Encoder Interface Mode
RM0390 Advanced-control timers (TIM1&TIM8) The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The t is defined by the value written in the TIMx_CCR1 register. DELAY • The t is defined by the difference between the auto-reload value and the compare PULSE value (TIMx_ARR - TIMx_CCR1).
Page 486: Table 107. Counting Direction Versus Encoder Signals
Advanced-control timers (TIM1&TIM8) RM0390 configure TIMx_ARR before starting. in the same way, the capture, compare, prescaler, repetition counter, trigger output features continue to work as normal. Encoder mode and External clock mode 2 are not compatible and must not be selected together. In this mode, the counter is modified automatically following the speed and the direction of the incremental encoder and its content, therefore, always represents the encoder’s position.
Page 487: Figure 151. Example Of Counter Operation In Encoder Interface Mode
RM0390 Advanced-control timers (TIM1&TIM8) Figure 151. Example of counter operation in encoder interface mode. Figure 152 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=’1’). Figure 152. Example of encoder interface mode with TI1FP1 polarity inverted. The timer, when configured in Encoder Interface mode provides information on the sensor’s current position.
Page 488: Timer Input Xor Function
Advanced-control timers (TIM1&TIM8) RM0390 16.3.17 Timer input XOR function The TI1S bit in the TIMx_CR2 register allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the three input pins TIMx_CH1, TIMx_CH2 and TIMx_CH3.
Page 489: Figure 153. Example Of Hall Sensor Interface
RM0390 Advanced-control timers (TIM1&TIM8) Figure 153 describes this example. Figure 153. Example of Hall sensor interface RM0390 Rev 4 489/1328...
Page 490: Timx And External Trigger Synchronization
Advanced-control timers (TIM1&TIM8) RM0390 16.3.19 TIMx and external trigger synchronization The TIMx timer can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated.
Page 491: Figure 155. Control Circuit In Gated Mode
RM0390 Advanced-control timers (TIM1&TIM8) Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: • Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000).
Page 492: Figure 156. Control Circuit In Trigger Mode
Advanced-control timers (TIM1&TIM8) RM0390 Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: • Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC2F=0000).
Page 493: Timer Synchronization
RM0390 Advanced-control timers (TIM1&TIM8) Configure the channel 1 as follows, to detect rising edges on TI: – IC1F=0000: no filter. – The capture prescaler is not used for triggering and does not need to be configured. – CC1S=01 in TIMx_CCMR1 register to select only the input capture source –...
Page 494: Tim1&Tim8 Registers
Advanced-control timers (TIM1&TIM8) RM0390 16.4 TIM1&TIM8 registers Refer to Section 1.1: List of abbreviations for registers for a list of abbreviations used in register descriptions. The peripheral registers must be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-word (16 bits) or words (32 bits).
Page 495: Tim1&Tim8 Control Register 2 (Timx_Cr2)
RM0390 Advanced-control timers (TIM1&TIM8) Bit 3 OPM: One pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled.
Page 496 Advanced-control timers (TIM1&TIM8) RM0390 Bit 11 OIS2N: Output Idle state 2 (OC2N output) refer to OIS1N bit Bit 10 OIS2: Output Idle state 2 (OC2 output) refer to OIS1 bit Bit 9 OIS1N: Output Idle state 1 (OC1N output) 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
Page 497: Tim1&Tim8 Slave Mode Control Register (Timx_Smcr)
RM0390 Advanced-control timers (TIM1&TIM8) Bit 1 Reserved, must be kept at reset value. Bit 0 CCPC: Capture/compare preloaded control 0: CCxE, CCxNE and OCxM bits are not preloaded 1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit).
Page 498 Advanced-control timers (TIM1&TIM8) RM0390 Bits 11:8 ETF[3:0]: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
Page 499: Tim1&Tim8 Dma/Interrupt Enable Register (Timx_Dier)
RM0390 Advanced-control timers (TIM1&TIM8) Bits 2:0 SMS: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description.
Page 500 Advanced-control timers (TIM1&TIM8) RM0390 Bit 11 CC3DE: Capture/Compare 3 DMA request enable 0: CC3 DMA request disabled 1: CC3 DMA request enabled Bit 10 CC2DE: Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled 1: CC2 DMA request enabled Bit 9 CC1DE: Capture/Compare 1 DMA request enable 0: CC1 DMA request disabled 1: CC1 DMA request enabled...
Page 501: Tim1&Tim8 Status Register (Timx_Sr)
RM0390 Advanced-control timers (TIM1&TIM8) 16.4.5 TIM1&TIM8 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 Res. Res. Res. CC4OF CC3OF CC2OF CC1OF Res. COMIF CC4IF CC3IF CC2IF CC1IF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:13 Reserved, must be kept at reset value.
Page 502: Tim1&Tim8 Event Generation Register (Timx_Egr)
Advanced-control timers (TIM1&TIM8) RM0390 Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/Compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description).
Page 503 RM0390 Advanced-control timers (TIM1&TIM8) Bit 5 COMG: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware 0: No action 1: When CCPC bit is set, it allows to update CCxE, CCxNE and OCxM bits Note: This bit acts only on channels having a complementary output.
Page 504: Tim1&Tim8 Capture/Compare Mode Register 1 (Timx_Ccmr1)
Advanced-control timers (TIM1&TIM8) RM0390 16.4.7 TIM1&TIM8 capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode.
Page 505 RM0390 Advanced-control timers (TIM1&TIM8) Bits 6:4 OC1M: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 506 Advanced-control timers (TIM1&TIM8) RM0390 Bits 1:0 CC1S: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC.
Page 507: Tim1&Tim8 Capture/Compare Mode Register 2 (Timx_Ccmr2)
RM0390 Advanced-control timers (TIM1&TIM8) Bits 3:2 IC1PSC: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register). 00: no prescaler, capture is done each time an edge is detected on the capture input 01: capture is done once every 2 events 10: capture is done once every 4 events 11: capture is done once every 8 events...
Page 508: Tim1&Tim8 Capture/Compare Enable Register (Timx_Ccer)
Advanced-control timers (TIM1&TIM8) RM0390 Bit 3 OC3PE: Output compare 3 preload enable Bit 2 OC3FE: Output compare 3 fast enable Bits 1:0 CC3S: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4...
Page 509 RM0390 Advanced-control timers (TIM1&TIM8) Bit 12 CC4E: Capture/Compare 4 output enable refer to CC1E description Bit 11 CC3NP: Capture/Compare 3 complementary output polarity refer to CC1NP description Bit 10 CC3NE: Capture/Compare 3 complementary output enable refer to CC1NE description Bit 9 CC3P: Capture/Compare 3 output polarity refer to CC1P description Bit 8 CC3E: Capture/Compare 3 output enable refer to CC1E description...
Page 510 Advanced-control timers (TIM1&TIM8) RM0390 Bit 1 CC1P: Capture/Compare 1 output polarity CC1 channel configured as output: 0: OC1 active high 1: OC1 active low CC1 channel configured as input: CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations.
Page 511: Table 109. Output Control Bits For Complementary Ocx And Ocxn Channels
RM0390 Advanced-control timers (TIM1&TIM8) Table 109. Output control bits for complementary OCx and OCxN channels with break feature Control bits Output states OSSI OSSR CCxE CCxNE OCx output state OCxN output state Output Disabled (not driven by Output Disabled (not driven by the timer) the timer) OCxN=0, OCxN_EN=0 OCx=0, OCx_EN=0...
Page 512: Tim1&Tim8 Counter (Timx_Cnt)
Advanced-control timers (TIM1&TIM8) RM0390 Note: The state of the external I/O pins connected to the complementary OCx and OCxN channels depends on the OCx and OCxN channel state and the GPIO registers. 16.4.10 TIM1&TIM8 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[15:0] Bits 15:0 CNT[15:0]: Counter value 16.4.11...
Page 513: Tim1&Tim8 Repetition Counter Register (Timx_Rcr)
RM0390 Advanced-control timers (TIM1&TIM8) 16.4.13 TIM1&TIM8 repetition counter register (TIMx_RCR) Address offset: 0x30 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. REP[7:0] Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e.
Page 514: Tim1&Tim8 Capture/Compare Register 2 (Timx_Ccr2)
Advanced-control timers (TIM1&TIM8) RM0390 16.4.15 TIM1&TIM8 capture/compare register 2 (TIMx_CCR2) Address offset: 0x38 Reset value: 0x0000 CCR2[15:0] Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC2PE).
Page 515: Tim1&Tim8 Capture/Compare Register 4 (Timx_Ccr4)
RM0390 Advanced-control timers (TIM1&TIM8) 16.4.17 TIM1&TIM8 capture/compare register 4 (TIMx_CCR4) Address offset: 0x40 Reset value: 0x0000 CCR4[15:0] Bits 15:0 CCR4[15:0]: Capture/Compare value If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit OC4PE).
Page 516 Advanced-control timers (TIM1&TIM8) RM0390 Bit 13 BKP: Break polarity 0: Break input BRK is active low 1: Break input BRK is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 517: Tim1&Tim8 Dma Control Register (Timx_Dcr)
RM0390 Advanced-control timers (TIM1&TIM8) Bits 7:0 DTG[7:0]: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x t with t DTG[7:5]=10x => DT=(64+DTG[5:0])xt with T =2xt DTG[7:5]=110 =>...
Page 518: Tim1&Tim8 Dma Address For Full Transfer (Timx_Dmar)
Advanced-control timers (TIM1&TIM8) RM0390 16.4.20 TIM1&TIM8 DMA address for full transfer (TIMx_DMAR) Address offset: 0x4C Reset value: 0x0000 DMAB[15:0] Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the...
Page 519: Tim1&Tim8 Register Map
RM0390 Advanced-control timers (TIM1&TIM8) 16.4.21 TIM1&TIM8 register map TIM1&TIM8 registers are mapped as 16-bit addressable registers as described in the table below: Table 110. TIM1&TIM8 register map and reset values Offset Register TIMx_CR1 [1:0] [1:0] 0x00 Reset value TIMx_CR2 MMS[2:0] 0x04 Reset value ETPS...
Page 520 Advanced-control timers (TIM1&TIM8) RM0390 Table 110. TIM1&TIM8 register map and reset values (continued) Offset Register TIMx_CCR1 CCR1[15:0] 0x34 Reset value TIMx_CCR2 CCR2[15:0] 0x38 Reset value TIMx_CCR3 CCR3[15:0] 0x3C Reset value TIMx_CCR4 CCR4[15:0] 0x40 Reset value LOCK TIMx_BDTR DT[7:0] [1:0] 0x44 Reset value TIMx_DCR DBL[4:0]...
Page 521: General-Purpose Timers (Tim2 To Tim5)
RM0390 General-purpose timers (TIM2 to TIM5) General-purpose timers (TIM2 to TIM5) 17.1 TIM2 to TIM5 introduction The general-purpose timers consist of a 16-bit or 32-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare and PWM).
Page 522: Tim2 To Tim5 Functional Description
General-purpose timers (TIM2 to TIM5) RM0390 Figure 158. General-purpose timer block diagram 17.3 TIM2 to TIM5 functional description 17.3.1 Time-base unit The main block of the programmable timer is a 16-bit/32-bit counter with its related auto- reload register. The counter can count up. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software.
Page 523: Figure 159. Counter Timing Diagram With Prescaler Division Change From 1 To 2
RM0390 General-purpose timers (TIM2 to TIM5) The time-base unit includes: • Counter Register (TIMx_CNT) • Prescaler Register (TIMx_PSC): • Auto-Reload Register (TIMx_ARR) The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register.
Page 524: Counter Modes
General-purpose timers (TIM2 to TIM5) RM0390 Figure 160. Counter timing diagram with prescaler division change from 1 to 4 17.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An Update event can be generated at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).
Page 525: Figure 161. Counter Timing Diagram, Internal Clock Divided By 1
RM0390 General-purpose timers (TIM2 to TIM5) Figure 161. Counter timing diagram, internal clock divided by 1 Figure 162. Counter timing diagram, internal clock divided by 2 Figure 163. Counter timing diagram, internal clock divided by 4 RM0390 Rev 4 525/1328...
Page 526: Figure 164. Counter Timing Diagram, Internal Clock Divided By N
General-purpose timers (TIM2 to TIM5) RM0390 Figure 164. Counter timing diagram, internal clock divided by N Figure 165. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded) 526/1328 RM0390 Rev 4...
Page 527: Figure 166. Counter Timing Diagram, Update Event When Arpe=1 (Timx_Arr Preloaded)
RM0390 General-purpose timers (TIM2 to TIM5) Figure 166. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded) Downcounting mode In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event.
Page 528: Figure 167. Counter Timing Diagram, Internal Clock Divided By 1
General-purpose timers (TIM2 to TIM5) RM0390 Figure 167. Counter timing diagram, internal clock divided by 1 Figure 168. Counter timing diagram, internal clock divided by 2 Figure 169. Counter timing diagram, internal clock divided by 4 528/1328 RM0390 Rev 4...
Page 529: Figure 170. Counter Timing Diagram, Internal Clock Divided By N
RM0390 General-purpose timers (TIM2 to TIM5) Figure 170. Counter timing diagram, internal clock divided by N Figure 171. Counter timing diagram, Update event Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register) –...
Page 530: Figure 172. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr=0X6
General-purpose timers (TIM2 to TIM5) RM0390 In this mode, the direction bit (DIR from TIMx_CR1 register) cannot be written. It is updated by hardware and gives the current direction of the counter. The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event.
Page 531: Figure 173. Counter Timing Diagram, Internal Clock Divided By 2
RM0390 General-purpose timers (TIM2 to TIM5) Figure 173. Counter timing diagram, internal clock divided by 2 Figure 174. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 1. Center-aligned mode 2 or 3 is used with an UIF on overflow. Figure 175.
Page 532: Figure 176. Counter Timing Diagram, Update Event With Arpe=1 (Counter Underflow)
General-purpose timers (TIM2 to TIM5) RM0390 Figure 176. Counter timing diagram, Update event with ARPE=1 (counter underflow) Figure 177. Counter timing diagram, Update event with ARPE=1 (counter overflow) 532/1328 RM0390 Rev 4...
Page 533: Clock Selection
RM0390 General-purpose timers (TIM2 to TIM5) 17.3.3 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin (TIx) • External clock mode2: external trigger input (ETR) available on TIM2, TIM3 and TIM4 only.
Page 534: Figure 179. Ti2 External Clock Connection Example
General-purpose timers (TIM2 to TIM5) RM0390 Figure 179. TI2 external clock connection example For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: Configure channel 2 to detect rising edges on the TI2 input by writing CC2S= ‘01 in the TIMx_CCMR1 register.
Page 535: Figure 180. Control Circuit In External Clock Mode 1
RM0390 General-purpose timers (TIM2 to TIM5) Figure 180. Control circuit in external clock mode 1 External clock source mode 2 This mode is selected by writing ECE=1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR. Figure 181 gives an overview of the external trigger input block.
Page 536: Capture/Compare Channels
General-purpose timers (TIM2 to TIM5) RM0390 The delay between the rising edge on ETR and the actual clock of the counter is due to the resynchronization circuit on the ETRP signal. Figure 182. Control circuit in external clock mode 2 17.3.4 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a...
Page 537: Figure 183. Capture/Compare Channel (Example: Channel 1 Input Stage)
RM0390 General-purpose timers (TIM2 to TIM5) Figure 183. Capture/compare channel (example: channel 1 input stage) The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain. Figure 184.
Page 538: Input Capture Mode
General-purpose timers (TIM2 to TIM5) RM0390 Figure 185. Output stage of capture/compare channel (channel 1) The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register.
Page 539: Pwm Input Mode
RM0390 General-purpose timers (TIM2 to TIM5) new level have been detected (sampled at f frequency). Then write IC1F bits to 0011 in the TIMx_CCMR1 register. • Select the edge of the active transition on the TI1 channel by writing the CC1P and CC1NP bits to 00 in the TIMx_CCER register (rising edge in this case).
Page 540: Forced Output Mode
General-purpose timers (TIM2 to TIM5) RM0390 For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value): •...
Page 541: Output Compare Mode
RM0390 General-purpose timers (TIM2 to TIM5) Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the Output Compare Mode section. 17.3.8 Output compare mode This function is used to control an output waveform or indicating when a period of time has...
Page 542: Pwm Mode
General-purpose timers (TIM2 to TIM5) RM0390 Figure 187. Output compare mode, toggle on OC1 17.3.9 PWM mode Pulse width modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
Page 543: Figure 188. Edge-Aligned Pwm Waveforms (Arr=8)
RM0390 General-purpose timers (TIM2 to TIM5) PWM edge-aligned mode Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to Upcounting mode on page 524. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT <TIMx_CCRx else it becomes low.
Page 544: Figure 189. Center-Aligned Pwm Waveforms (Arr=8)
General-purpose timers (TIM2 to TIM5) RM0390 TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to Center-aligned mode (up/down counting) on page 529. Figure 189 shows some center-aligned PWM waveforms in an example where: • TIMx_ARR=8, •...
Page 545: One-Pulse Mode
RM0390 General-purpose timers (TIM2 to TIM5) in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software. • Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results.
Page 546: Clearing The Ocxref Signal On An External Event
General-purpose timers (TIM2 to TIM5) RM0390 Let’s use TI2FP2 as trigger 1: • Map TI2FP2 on TI2 by writing CC2S=01 in the TIMx_CCMR1 register. • TI2FP2 must detect a rising edge, write CC2P=0 and CC2NP=’0’ in the TIMx_CCER register. • Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=110 in the TIMx_SMCR register.
Page 547: Encoder Interface Mode
RM0390 General-purpose timers (TIM2 to TIM5) The external trigger prescaler should be kept off: bits ETPS[1:0] in the TIMx_SMCR register are cleared to 00. The external clock mode 2 must be disabled: bit ECE in the TIM1_SMCR register is cleared to 0. The external trigger polarity (ETP) and the external trigger filter (ETF) can be configured according to the application’s needs.
Page 548: Table 111. Counting Direction Versus Encoder Signals
General-purpose timers (TIM2 to TIM5) RM0390 In this mode, the counter is modified automatically following the speed and the direction of the incremental encoder and its content, therefore, always represents the encoder’s position. The count direction correspond to the rotation direction of the connected sensor. The table summarizes the possible combinations, assuming TI1 and TI2 don’t switch at the same time.
Page 549: Figure 192. Example Of Counter Operation In Encoder Interface Mode
RM0390 General-purpose timers (TIM2 to TIM5) Figure 192. Example of counter operation in encoder interface mode Figure 193 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=1). Figure 193. Example of encoder interface mode with TI1FP1 polarity inverted The timer, when configured in Encoder Interface mode provides information on the sensor’s current position.
Page 550: Timer Input Xor Function
General-purpose timers (TIM2 to TIM5) RM0390 17.3.13 Timer input XOR function The TI1S bit in the TIM_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the three input pins TIMx_CH1 to TIMx_CH3. The XOR output can be used with all the timer input functions such as trigger or input capture.
Page 551: Figure 195. Control Circuit In Gated Mode
RM0390 General-purpose timers (TIM2 to TIM5) Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: • Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000).
Page 552: Figure 196. Control Circuit In Trigger Mode
General-purpose timers (TIM2 to TIM5) RM0390 The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input. Figure 196. Control circuit in trigger mode Slave mode: External Clock mode 2 + trigger mode The external clock mode 2 can be used in addition to another slave mode (except external clock mode 1 and encoder mode).
Page 553: Timer Synchronization
RM0390 General-purpose timers (TIM2 to TIM5) Figure 197. Control circuit in external clock mode 2 + trigger mode 17.3.15 Timer synchronization The TIMx timers are linked together internally for timer synchronization or chaining. When one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of another Timer configured in Slave Mode.
Page 554: Figure 199. Gating Timer 2 With Oc1Ref Of Timer 1
General-purpose timers (TIM2 to TIM5) RM0390 For example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to Figure 198. To do this: • Configure Timer 1 in master mode so that it outputs a periodic trigger signal on each update event UEV.
Page 555: Figure 200. Gating Timer 2 With Enable Of Timer 1
RM0390 General-purpose timers (TIM2 to TIM5) you want in the timer counters. The timers can easily be reset by software using the UG bit in the TIMx_EGR registers. In the next example, we synchronize Timer 1 and Timer 2. Timer 1 is the master and starts from 0.
Page 556: Figure 201. Triggering Timer 2 With Update Of Timer 1
General-purpose timers (TIM2 to TIM5) RM0390 counts until we write ‘0 to the CEN bit in the TIM2_CR1 register. Both counter clock frequencies are divided by 3 by the prescaler compared to CK_INT (f /3). CK_CNT CK_INT • Configure Timer 1 master mode to send its Update Event (UEV) as trigger output (MMS=010 in the TIM1_CR2 register).
Page 557: Figure 202. Triggering Timer 2 With Enable Of Timer 1
RM0390 General-purpose timers (TIM2 to TIM5) Figure 202. Triggering timer 2 with Enable of timer 1 Using one timer as prescaler for another timer For example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to Figure 198 for connections.
Page 558: Debug Mode
General-purpose timers (TIM2 to TIM5) RM0390 counters are aligned, Timer 1 must be configured in Master/Slave mode (slave with respect to TI1, master with respect to Timer 2): • Configure Timer 1 master mode to send its Enable as trigger output (MMS=001 in the TIM1_CR2 register).
Page 559: Tim2 To Tim5 Registers
RM0390 General-purpose timers (TIM2 to TIM5) 17.4 TIM2 to TIM5 registers Refer to Section 1.1 on page 51 for a list of abbreviations used in register descriptions. The 32-bit peripheral registers have to be written by words (32 bits). All other peripheral registers have to be written by half-words (16 bits) or words (32 bits).
Page 560 General-purpose timers (TIM2 to TIM5) RM0390 Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: –...
Page 561: Timx Control Register 2 (Timx_Cr2)
RM0390 General-purpose timers (TIM2 to TIM5) 17.4.2 TIMx control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. TI1S MMS[2:0] CCDS Res. Res. Res. Bits 15:8 Reserved, must be kept at reset value. Bit 7 TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input 1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
Page 562: Timx Slave Mode Control Register (Timx_Smcr)
General-purpose timers (TIM2 to TIM5) RM0390 17.4.3 TIMx slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 ETPS[1:0] ETF[3:0] TS[2:0] Res. SMS[2:0] Bit 15 ETP: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is noninverted, active at high level or rising edge 1: ETR is inverted, active at low level or falling edge Bit 14 ECE: External clock enable...
Page 563: Table 112. Timx Internal Trigger Connections
RM0390 General-purpose timers (TIM2 to TIM5) Bit 7 MSM: Master/Slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Page 564: Timx Dma/Interrupt Enable Register (Timx_Dier)
General-purpose timers (TIM2 to TIM5) RM0390 17.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 Res. Res. CC4DE CC3DE CC2DE CC1DE Res. Res. CC4IE CC3IE CC2IE CC1IE Bit 15 Reserved, must be kept at reset value. Bit 14 TDE: Trigger DMA request enable 0: Trigger DMA request disabled.
Page 565: Timx Status Register (Timx_Sr)
RM0390 General-purpose timers (TIM2 to TIM5) Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled 1: CC2 interrupt enabled Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled 17.4.5...
Page 566 General-purpose timers (TIM2 to TIM5) RM0390 Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description).
Page 567: Timx Event Generation Register (Timx_Egr)
RM0390 General-purpose timers (TIM2 to TIM5) 17.4.6 TIMx event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC4G CC3G CC2G CC1G Bits 15:7 Reserved, must be kept at reset value. Bit 6 TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
Page 568: Timx Capture/Compare Mode Register 1 (Timx_Ccmr1)
General-purpose timers (TIM2 to TIM5) RM0390 17.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode.
Page 569 RM0390 General-purpose timers (TIM2 to TIM5) Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 570 General-purpose timers (TIM2 to TIM5) RM0390 Input capture mode Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output.
Page 571: Timx Capture/Compare Mode Register 2 (Timx_Ccmr2)
RM0390 General-purpose timers (TIM2 to TIM5) 17.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2) Address offset: 0x1C Reset value: 0x0000 Refer to the above CCMR1 register description. OC4CE OC4M[2:0] OC4PE OC4FE OC3CE OC3M[2:0] OC3PE OC3FE CC4S[1:0] CC3S[1:0] IC4F[3:0] IC4PSC[1:0] IC3F[3:0] IC3PSC[1:0] Output compare mode Bit 15 OC4CE: Output compare 4 clear enable Bits 14:12 OC4M: Output compare 4 mode...
Page 572: Timx Capture/Compare Enable Register (Timx_Ccer)
General-purpose timers (TIM2 to TIM5) RM0390 Input capture mode Bits 15:12 IC4F: Input capture 4 filter Bits 11:10 IC4PSC: Input capture 4 prescaler Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3...
Page 573: Table 113. Output Control Bit For Standard Ocx Channels
RM0390 General-purpose timers (TIM2 to TIM5) Bit 7 CC2NP: Capture/Compare 2 output Polarity. refer to CC1NP description Bit 6 Reserved, must be kept at reset value. Bit 5 CC2P: Capture/Compare 2 output Polarity. refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable. refer to CC1E description Bit 3 CC1NP: Capture/Compare 1 output Polarity.
Page 574: Timx Counter (Timx_Cnt)
General-purpose timers (TIM2 to TIM5) RM0390 17.4.10 TIMx counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[15:0] Bits 15:0 CNT[15:0]: Counter value 17.4.11 TIMx prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to f / (PSC[15:0] + 1).
Page 575: Timx Capture/Compare Register 1 (Timx_Ccr1)
RM0390 General-purpose timers (TIM2 to TIM5) 17.4.13 TIMx capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 0000 CCR1[31:16] (depending on timers) CCR1[15:0] Bits 31:16 CCR1[31:16]: High Capture/Compare 1 value (on TIM2 and TIM5). Bits 15:0 CCR1[15:0]: Low Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
Page 576: Timx Capture/Compare Register 3 (Timx_Ccr3)
General-purpose timers (TIM2 to TIM5) RM0390 17.4.15 TIMx capture/compare register 3 (TIMx_CCR3) Address offset: 0x3C Reset value: 0x0000 0000 CCR3[31:16] (depending on timers) CCR3[15:0] Bits 31:16 CCR3[31:16]: High Capture/Compare 3 value (on TIM2 and TIM5). Bits 15:0 CCR3[15:0]: Low Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).
Page 577: Timx Dma Control Register (Timx_Dcr)
RM0390 General-purpose timers (TIM2 to TIM5) 17.4.17 TIMx DMA control register (TIMx_DCR) Address offset: 0x48 Reset value: 0x0000 Res. Res. Res. DBL[4:0] Res. Res. Res. DBA[4:0] Bits 15:13 Reserved, must be kept at reset value. Bits 12:8 DBL[4:0]: DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address).
Page 578: Tim2 Option Register (Tim2_Or)
General-purpose timers (TIM2 to TIM5) RM0390 Configure the corresponding DMA channel as follows: – DMA channel peripheral address is the DMAR register address – DMA channel memory address is the address of the buffer in the RAM containing the data to be transferred by DMA into CCRx registers. –...
Page 579: Tim5 Option Register (Tim5_Or)
RM0390 General-purpose timers (TIM2 to TIM5) 17.4.20 TIM5 option register (TIM5_OR) Address offset: 0x50 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. TI4_RMP Res. Res. Res. Res. Res. Res. Bits 15:8 Reserved, must be kept at reset value. Bits 7:6 TI4_RMP: Timer Input 4 remap Set and cleared by software.
Page 580: Timx Register Map
General-purpose timers (TIM2 to TIM5) RM0390 17.4.21 TIMx register map TIMx registers are mapped as described in the table below: Table 114. TIM2 to TIM5 register map and reset values Offset Register TIMx_CR1 [1:0] [1:0] 0x00 Reset value TIMx_CR2 MMS[2:0] 0x04 Reset value ETPS...
Page 581 RM0390 General-purpose timers (TIM2 to TIM5) Table 114. TIM2 to TIM5 register map and reset values (continued) Offset Register TIMx_PSC PSC[15:0] 0x28 Reset value ARR[31:16] TIMx_ARR ARR[15:0] (TIM2 and TIM5 only, reserved on the other timers) 0x2C Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x30 Reserved CCR1[31:16]...
Page 582: General-Purpose Timers (Tim9 To Tim14)
General-purpose timers (TIM9 to TIM14) RM0390 General-purpose timers (TIM9 to TIM14) 18.1 TIM9 to TIM14 introduction The TIM9 to TIM14 general-purpose timers consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM).
Page 583: Tim10/Tim11 And Tim13/Tim14 Main Features
RM0390 General-purpose timers (TIM9 to TIM14) Figure 204. General-purpose timer block diagram (TIM9 and TIM12) Internal clock (CK_INT) ITR0 Trigger controller ITR1 ITR2 TRGI Slave ITR3 Reset, Enable, Count mode TI1F_ED controller TI1FP1 TI2FP2 Auto-reload register Stop, Clear CK_PSC CK_CNT Prescaler COUNTER CC1I...
Page 584: Figure 205. General-Purpose Timer Block Diagram (Tim10/11/13/14)
General-purpose timers (TIM9 to TIM14) RM0390 Figure 205. General-purpose timer block diagram (TIM10/11/13/14) 584/1328 RM0390 Rev 4...
Page 585: Tim9 To Tim14 Functional Description
RM0390 General-purpose timers (TIM9 to TIM14) 18.3 TIM9 to TIM14 functional description 18.3.1 Time-base unit The main block of the timer is a 16-bit counter with its related auto-reload register. The counters counts up. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software.
Page 586: Figure 206. Counter Timing Diagram With Prescaler Division Change From 1 To 2
General-purpose timers (TIM9 to TIM14) RM0390 Figure 206. Counter timing diagram with prescaler division change from 1 to 2 Figure 207. Counter timing diagram with prescaler division change from 1 to 4 586/1328 RM0390 Rev 4...
Page 587: Counter Modes
RM0390 General-purpose timers (TIM9 to TIM14) 18.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller on TIM9 and TIM12) also generates an update event.
Page 588: Figure 209. Counter Timing Diagram, Internal Clock Divided By 2
General-purpose timers (TIM9 to TIM14) RM0390 Figure 209. Counter timing diagram, internal clock divided by 2 Figure 210. Counter timing diagram, internal clock divided by 4 Figure 211. Counter timing diagram, internal clock divided by N 588/1328 RM0390 Rev 4...
Page 589: Figure 212. Counter Timing Diagram, Update Event When Arpe=0
RM0390 General-purpose timers (TIM9 to TIM14) Figure 212. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) Figure 213. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) RM0390 Rev 4 589/1328...
Page 590: Clock Selection
General-purpose timers (TIM9 to TIM14) RM0390 18.3.3 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1 (for TIM9 and TIM12): external input pin (TIx) • Internal trigger inputs (ITRx) (for TIM9 and TIM12): connecting the trigger output from another timer.
Page 591: Figure 215. Ti2 External Clock Connection Example
RM0390 General-purpose timers (TIM9 to TIM14) Figure 215. TI2 external clock connection example For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register.
Page 592: Capture/Compare Channels
General-purpose timers (TIM9 to TIM14) RM0390 18.3.4 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control). Figure 217 Figure 219 give an overview of one capture/compare channel.
Page 593: Input Capture Mode
RM0390 General-purpose timers (TIM9 to TIM14) Figure 218. Capture/compare channel 1 main circuit Figure 219. Output stage of capture/compare channel (channel 1) The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register.
Page 594: Pwm Input Mode (Only For Tim9/12)
General-purpose timers (TIM9 to TIM14) RM0390 cleared by software by writing it to ‘0’ or by reading the captured data stored in the TIMx_CCRx register. CCxOF is cleared when you write it to ‘0’. The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises.
Page 595: Forced Output Mode
RM0390 General-purpose timers (TIM9 to TIM14) Select the active input for TIMx_CCR1: write the CC1S bits to ‘01’ in the TIMx_CCMR1 register (TI1 selected). Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): program the CC1P and CC1NP bits to ‘00’ (active on rising edge). Select the active input for TIMx_CCR2: write the CC2S bits to ‘10’...
Page 596: Output Compare Mode
General-purpose timers (TIM9 to TIM14) RM0390 18.3.8 Output compare mode This function is used to control an output waveform or indicating when a period of time has elapsed. When a match is found between the capture/compare register and the counter, the output compare function: Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP...
Page 597: Pwm Mode
RM0390 General-purpose timers (TIM9 to TIM14) Figure 221. Output compare mode, toggle on OC1. 18.3.9 PWM mode Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
Page 598: One-Pulse Mode
General-purpose timers (TIM9 to TIM14) RM0390 Figure 222. Edge-aligned PWM waveforms (ARR=8) 18.3.10 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay.
Page 599: Figure 223. Example Of One Pulse Mode
RM0390 General-purpose timers (TIM9 to TIM14) Figure 223. Example of one pulse mode. For example you may want to generate a positive pulse on OC1 with a length of t PULSE after a delay of t as soon as a positive edge is detected on the TI2 input pin. DELAY Use TI2FP2 as trigger 1: Map TI2FP2 to TI2 by writing CC2S=’01’...
Page 600: Tim9/12 External Trigger Synchronization
General-purpose timers (TIM9 to TIM14) RM0390 Particular case: OCx fast enable In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle.
Page 601: Figure 224. Control Circuit In Reset Mode
RM0390 General-purpose timers (TIM9 to TIM14) Figure 224. Control circuit in reset mode Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: Configure the channel 1 to detect low levels on TI1.
Page 602: Figure 225. Control Circuit In Gated Mode
General-purpose timers (TIM9 to TIM14) RM0390 Figure 225. Control circuit in gated mode Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: Configure the channel 2 to detect rising edges on TI2.
Page 603: Timer Synchronization (Tim9/12)
RM0390 General-purpose timers (TIM9 to TIM14) 18.3.12 Timer synchronization (TIM9/12) The TIM timers are linked together internally for timer synchronization or chaining. Refer to Section 17.3.15: Timer synchronization for details. 18.3.13 Debug mode ® When the microcontroller enters debug mode (Cortex -M4 with FPU core halted), the TIMx counter either continues to work normally or stops, depending on DBG_TIMx_STOP configuration bit in DBG module.
Page 604 General-purpose timers (TIM9 to TIM14) RM0390 Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generates an update interrupt if enabled: – Counter overflow –...
Page 605: Tim9/12 Slave Mode Control Register (Timx_Smcr)
RM0390 General-purpose timers (TIM9 to TIM14) 18.4.2 TIM9/12 slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. TS[2:0] Res. SMS[2:0] Bits 15:8 Reserved, must be kept at reset value. Bit 7 MSM: Master/Slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO).
Page 606: Tim9/12 Interrupt Enable Register (Timx_Dier)
General-purpose timers (TIM9 to TIM14) RM0390 Table 115. TIMx internal trigger connections Slave TIM ITR0 (TS = ‘000’) ITR1 (TS = ‘001’) ITR2 (TS = ‘010’) ITR3 (TS = ‘011’) TIM9 TIM2 TIM3 TIM10_OC TIM11_OC TIM12 TIM4 TIM5 TIM13_OC TIM14_OC 18.4.3 TIM9/12 Interrupt enable register (TIMx_DIER) Address offset: 0x0C...
Page 607: Tim9/12 Status Register (Timx_Sr)
RM0390 General-purpose timers (TIM9 to TIM14) 18.4.4 TIM9/12 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 Res. Res. Res. Res. Res. CC2OF CC1OF Res. Res. Res. Res. Res. CC2IF CC1IF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:11 Reserved, must be kept at reset value. Bit 10 CC2OF: Capture/compare 2 overcapture flag refer to CC1OF description Bit 9 CC1OF: Capture/Compare 1 overcapture flag...
Page 608: Tim9/12 Event Generation Register (Timx_Egr)
General-purpose timers (TIM9 to TIM14) RM0390 Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value. It is cleared by software. 0: No match. 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
Page 609: Tim9/12 Capture/Compare Mode Register 1 (Timx_Ccmr1)
RM0390 General-purpose timers (TIM9 to TIM14) Bit 1 CC1G: Capture/compare 1 generation This bit is set by software to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: the CC1IF flag is set, the corresponding interrupt is sent if enabled.
Page 610 General-purpose timers (TIM9 to TIM14) RM0390 Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas the active levels of OC1 and OC1N depend on the CC1P and CC1NP bits, respectively.
Page 611 RM0390 General-purpose timers (TIM9 to TIM14) Input capture mode Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/compare 2 selection This bitfield defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1...
Page 612: Tim9/12 Capture/Compare Enable Register (Timx_Ccer)
General-purpose timers (TIM9 to TIM14) RM0390 18.4.7 TIM9/12 capture/compare enable register (TIMx_CCER) Address offset: 0x20 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. CC2NP Res. CC2P CC2E CC1NP Res. CC1P CC1E Bits 15:8 Reserved, must be kept at reset value. Bit 7 CC2NP: Capture/Compare 2 output Polarity refer to CC1NP description Bit 6 Reserved, must be kept at reset value.
Page 613: Tim9/12 Counter (Timx_Cnt)
RM0390 General-purpose timers (TIM9 to TIM14) Table 116. Output control bit for standard OCx channels CCxE bit OCx output state Output disabled (OCx=’0’, OCx_EN=’0’) OCx=OCxREF + Polarity, OCx_EN=’1’ Note: The states of the external I/O pins connected to the standard OCx channels depend on the state of the OCx channel and on the GPIO registers.
Page 614: Tim9/12 Capture/Compare Register 1 (Timx_Ccr1)
General-purpose timers (TIM9 to TIM14) RM0390 18.4.11 TIM9/12 capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 CCR1[15:0] Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded into the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (OC1PE bit).
Page 615: Tim9/12 Register Map
RM0390 General-purpose timers (TIM9 to TIM14) 18.4.13 TIM9/12 register map TIM9/12 registers are mapped as 16-bit addressable registers as described below: Table 117. TIM9/12 register map and reset values Offset Register TIMx_CR1 [1:0] 0x00 Reset value TIMx_SMCR TS[2:0] SMS[2:0] 0x08 Reset value TIMx_DIER 0x0C...
Page 616 General-purpose timers (TIM9 to TIM14) RM0390 Table 117. TIM9/12 register map and reset values (continued) Offset Register TIMx_CCR1 CCR1[15:0] 0x34 Reset value TIMx_CCR2 CCR2[15:0] 0x38 Reset value 0x3C to Reserved 0x4C Refer to Section 2.2.2 on page 56 for the register boundary addresses. 616/1328 RM0390 Rev 4...
Page 617: Tim10/11/13/14 Registers
RM0390 General-purpose timers (TIM9 to TIM14) 18.5 TIM10/11/13/14 registers The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). 18.5.1 TIM10/11/13/14 control register 1 (TIMx_CR1) Address offset: 0x00...
Page 618: Tim10/11/13/14 Interrupt Enable Register (Timx_Dier)
General-purpose timers (TIM9 to TIM14) RM0390 18.5.2 TIM10/11/13/14 Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC1IE Bits 15:2 Reserved, must be kept at reset value. Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled...
Page 619: Tim10/11/13/14 Event Generation Register (Timx_Egr)
RM0390 General-purpose timers (TIM9 to TIM14) Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value. It is cleared by software. 0: No match. 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
Page 620: Tim10/11/13/14 Capture/Compare Mode Register 1
General-purpose timers (TIM9 to TIM14) RM0390 18.5.5 TIM10/11/13/14 capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode.
Page 621 RM0390 General-purpose timers (TIM9 to TIM14) Output compare mode Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 is derived.
Page 622 General-purpose timers (TIM9 to TIM14) RM0390 Input capture mode Bits 15:8 Reserved, must be kept at reset value. Bits 7:4 IC1F: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1.
Page 623: Tim10/11/13/14 Capture/Compare Enable Register
RM0390 General-purpose timers (TIM9 to TIM14) 18.5.6 TIM10/11/13/14 capture/compare enable register (TIMx_CCER) Address offset: 0x20 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC1NP Res. CC1P CC1E Bits 15:4 Reserved, must be kept at reset value. Bit 3 CC1NP: Capture/Compare 1 complementary output Polarity.
Page 624: Tim10/11/13/14 Counter (Timx_Cnt)
General-purpose timers (TIM9 to TIM14) RM0390 18.5.7 TIM10/11/13/14 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[15:0] Bits 15:0 CNT[15:0]: Counter value 18.5.8 TIM10/11/13/14 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to f / (PSC[15:0] + 1).
Page 625: Tim10/11/13/14 Capture/Compare Register 1 (Timx_Ccr1)
RM0390 General-purpose timers (TIM9 to TIM14) 18.5.10 TIM10/11/13/14 capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 CCR1[15:0] Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE).
Page 626: Tim10/11/13/14 Register Map
General-purpose timers (TIM9 to TIM14) RM0390 18.5.12 TIM10/11/13/14 register map TIMx registers are mapped as 16-bit addressable registers as described in the table below: Table 119. TIM10/11/13/14 register map and reset values Offset Register TIMx_CR1 [1:0] 0x00 Reset value TIMx_SMCR 0x08 Reset value TIMx_DIER...
Page 627 RM0390 General-purpose timers (TIM9 to TIM14) Table 119. TIM10/11/13/14 register map and reset values (continued) Offset Register TIMx_CCR1 CCR1[15:0] 0x34 Reset value 0x38 to Reserved 0x4C TIMx_OR 0x50 Reset value Refer to Section 2.2.2 on page 56 for the register boundary addresses. RM0390 Rev 4 627/1328...
Page 628: Basic Timers (Tim6&Tim7)
Basic timers (TIM6&TIM7) RM0390 Basic timers (TIM6&TIM7) 19.1 TIM6&TIM7 introduction The basic timers TIM6 and TIM7 consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used as generic timers for time-base generation but they are also specifically used to drive the digital-to-analog converter (DAC).
Page 629: Tim6&Tim7 Functional Description
RM0390 Basic timers (TIM6&TIM7) 19.3 TIM6&TIM7 functional description 19.3.1 Time-base unit The main block of the programmable timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software.
Page 630: Figure 228. Counter Timing Diagram With Prescaler Division Change From 1 To 2
Basic timers (TIM6&TIM7) RM0390 Figure 228. Counter timing diagram with prescaler division change from 1 to 2 Figure 229. Counter timing diagram with prescaler division change from 1 to 4 630/1328 RM0390 Rev 4...
Page 631: Counting Mode
RM0390 Basic timers (TIM6&TIM7) 19.3.2 Counting mode The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An update event can be generate at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).
Page 632: Figure 231. Counter Timing Diagram, Internal Clock Divided By 2
Basic timers (TIM6&TIM7) RM0390 Figure 231. Counter timing diagram, internal clock divided by 2 Figure 232. Counter timing diagram, internal clock divided by 4 Figure 233. Counter timing diagram, internal clock divided by N 632/1328 RM0390 Rev 4...
Page 633: Clock Source
RM0390 Basic timers (TIM6&TIM7) Figure 234. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded) Figure 235. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) 19.3.3 Clock source The counter clock is provided by the Internal clock (CK_INT) source. The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except for UG that remains cleared automatically).
Page 634: Debug Mode
Basic timers (TIM6&TIM7) RM0390 Figure 236. Control circuit in normal mode, internal clock divided by 1 19.3.4 Debug mode ® When the microcontroller enters the debug mode (Cortex -M4 with FPU core - halted), the TIMx counter either continues to work normally or stops, depending on the DBG_TIMx_STOP configuration bit in the DBG module.
Page 635 RM0390 Basic timers (TIM6&TIM7) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generates an update interrupt or DMA request if enabled. These events can be: –...
Page 636: Tim6&Tim7 Control Register 2 (Timx_Cr2)
Basic timers (TIM6&TIM7) RM0390 19.4.2 TIM6&TIM7 control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. MMS[2:0] Res. Res. Res. Res. Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 MMS[2:0]: Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO).
Page 637: Tim6&Tim7 Status Register (Timx_Sr)
RM0390 Basic timers (TIM6&TIM7) 19.4.4 TIM6&TIM7 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rc_w0 Bits 15:1 Reserved, must be kept at reset value. Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event.
Page 638: Tim6&Tim7 Prescaler (Timx_Psc)
Basic timers (TIM6&TIM7) RM0390 19.4.7 TIM6&TIM7 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to f / (PSC[15:0] + 1). CK_PSC PSC contains the value to be loaded into the active prescaler register at each update event. 19.4.8 TIM6&TIM7 auto-reload register (TIMx_ARR) Address offset: 0x2C...
Page 639: Tim6&Tim7 Register Map
RM0390 Basic timers (TIM6&TIM7) 19.4.9 TIM6&TIM7 register map TIMx registers are mapped as 16-bit addressable registers as described in the table below: Table 120. TIM6&TIM7 register map and reset values Offset Register TIMx_CR1 0x00 Reset value TIMx_CR2 MMS[2:0] 0x04 Reset value 0x08 Reserved TIMx_DIER...
Page 640: Independent Watchdog (Iwdg)
Independent watchdog (IWDG) RM0390 Independent watchdog (IWDG) 20.1 IWDG introduction The devices feature two embedded watchdog peripherals that offer a combination of high safety level, timing accuracy and flexibility of use. Both watchdog peripherals (Independent and Window) serve to detect and resolve malfunctions due to software failure, and to trigger system reset or an interrupt (window watchdog only) when the counter reaches a given timeout value.
Page 641: Debug Mode
RM0390 Independent watchdog (IWDG) A status register is available to indicate that an update of the prescaler or the down-counter reload value is on going. 20.3.3 Debug mode ® When the microcontroller enters debug mode (Cortex -M4 with FPU core halted), the IWDG counter either continues to work normally or stops, depending on DBG_IWDG_STOP configuration bit in DBG module.
Page 642: Iwdg Registers
Independent watchdog (IWDG) RM0390 20.4 IWDG registers Refer to Section 1.1 on page 51 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits). 20.4.1 Key register (IWDG_KR) Address offset: 0x00 Reset value: 0x0000 0000 (reset by Standby mode) Res.
Page 643: Prescaler Register (Iwdg_Pr)
RM0390 Independent watchdog (IWDG) 20.4.2 Prescaler register (IWDG_PR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 644: Reload Register (Iwdg_Rlr)
Independent watchdog (IWDG) RM0390 20.4.3 Reload register (IWDG_RLR) Address offset: 0x08 Reset value: 0x0000 0FFF (reset by Standby mode) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RL[11:0] Bits 31:12 Reserved, must be kept at reset value.
Page 645: Iwdg Register Map
RM0390 Independent watchdog (IWDG) Note: If several reload values or prescaler values are used by application, it is mandatory to wait until RVU bit is reset before changing the reload value and to wait until PVU bit is reset before changing the prescaler value. However, after updating the prescaler and/or the reload value it is not necessary to wait until RVU or PVU is reset before continuing code execution (even in case of low-power mode entry, the write operation is taken into account and will complete)
Page 646: Window Watchdog (Wwdg)
Window watchdog (WWDG) RM0390 Window watchdog (WWDG) 21.1 WWDG introduction The window watchdog is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the contents of the downcounter before the T6 bit becomes cleared.
Page 647: Figure 238. Watchdog Block Diagram
RM0390 Window watchdog (WWDG) Figure 238. Watchdog block diagram The application program must write in the WWDG_CR register at regular intervals during normal operation to prevent an MCU reset. This operation must occur only when the counter value is lower than the window register value. The value to be stored in the WWDG_CR register must be between 0xFF and 0xC0.
Page 648: How To Program The Watchdog Timeout
Window watchdog (WWDG) RM0390 In some applications, the EWI interrupt can be used to manage a software system check and/or system recovery/graceful degradation, without generating a WWDG reset. In this case, the corresponding interrupt service routine (ISR) should reload the WWDG counter to avoid the WWDG reset, then trigger the required actions.
Page 649: Debug Mode
RM0390 Window watchdog (WWDG) As an example, let us assume APB1 frequency is equal to 24 MHz, WDGTB[1:0] is set to 3 and T[5:0] is set to 63: ⁄ × × × t WWDG 24000 4096 21.85 ms Refer to the datasheets for the minimum and maximum values of the t WWDG.
Page 650: Wwdg Registers
Window watchdog (WWDG) RM0390 21.6 WWDG registers Refer to for a list of abbreviations used in register descriptions. Section 1.1 on page 51 The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits). 21.6.1 Control register (WWDG_CR) Address offset: 0x00 Reset value: 0x0000 007F Res.
Page 651: Configuration Register (Wwdg_Cfr)
RM0390 Window watchdog (WWDG) 21.6.2 Configuration register (WWDG_CFR) Address offset: 0x04 Reset value: 0x0000 007F Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WDGTB[1:0] W[6:0] Bits 31:10 Reserved, must be kept at reset value. Bit 9 EWI: Early wakeup interrupt When set, an interrupt occurs whenever the counter reaches the value 0x40.
Page 652: Wwdg Register Map
Window watchdog (WWDG) RM0390 21.6.4 WWDG register map The following table gives the WWDG register map and reset values. Table 123. WWDG register map and reset values Offset Register WWDG_CR T[6:0] 0x00 Reset value WWDG_CFR W[6:0] 0x04 Reset value WWDG_SR 0x08 Reset value Refer to...
Page 653: Real-Time Clock (Rtc)
RM0390 Real-time clock (RTC) Real-time clock (RTC) 22.1 Introduction The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time-of-day clock/calendar, two programmable alarm interrupts, and a periodic programmable wakeup flag with interrupt capability. The RTC also includes an automatic wakeup unit to manage low power modes.
Page 654 Real-time clock (RTC) RM0390 – 0.95 ppm accuracy, obtained in a calibration window of several seconds • Timestamp function for event saving (1 event) • Tamper detection: – 2 tamper events with configurable filter and internal pull-up. • 20 backup registers (80 bytes). The backup registers are reset when a tamper detection event occurs.
Page 655: Rtc Functional Description
RM0390 Real-time clock (RTC) 22.3 RTC functional description 22.3.1 Clock and prescalers The RTC clock source (RTCCLK) is selected through the clock controller among the LSE clock, the LSI oscillator clock, and the HSE clock. For more information on the RTC clock source configuration, refer to Section 6: Reset and clock control (RCC).
Page 656: Programmable Alarms
Real-time clock (RTC) RM0390 Every two RTCCLK periods, the current calendar value is copied into the shadow registers, and the RSF bit of RTC_ISR register is set (see Section 22.6.4). The copy is not performed in Stop and Standby mode. When exiting these modes, the shadow registers are updated after up to two RTCCLK periods.
Page 657: Rtc Initialization And Configuration
RM0390 Real-time clock (RTC) complete (see Programming the wakeup timer), the timer starts counting down.When the wakeup function is enabled, the down-counting remains active in low power modes. In addition, when it reaches 0, the WUTF flag is set in the RTC_ISR register, and the wakeup counter is automatically reloaded with its reload value (RTC_WUTR register value).
Page 658 Real-time clock (RTC) RM0390 factor. Even if only one of the two fields needs to be changed, 2 separate write accesses must be performed to the RTC_PRER register. Load the initial time and date values in the shadow registers (RTC_TR and RTC_DR), and configure the time format (12 or 24 hours) through the FMT bit in the RTC_CR register.
Page 659: Reading The Calendar
RM0390 Real-time clock (RTC) 22.3.6 Reading the calendar BYPSHAD control bit is cleared in the RTC_CR register When To read the RTC calendar registers (RTC_SSR, RTC_TR and RTC_DR) properly, the APB1 clock frequency (f ) must be equal to or greater than seven times the f PCLK1 RTCCLK clock frequency.
Page 660: Resetting The Rtc
Real-time clock (RTC) RM0390 22.3.7 Resetting the RTC The calendar shadow registers (RTC_SSR, RTC_TR and RTC_DR) and some bits of the RTC status register (RTC_ISR) are reset to their default values by all available system reset sources. On the contrary, the following registers are resetted to their default values by a backup domain reset and are not affected by a system reset: the RTC current calendar registers, the RTC control register (RTC_CR), the prescaler register (RTC_PRER), the RTC calibration registers (RTC_CALIBR or RTC_CALR), the RTC shift register (RTC_SHIFTR),...
Page 661: Rtc Reference Clock Detection
RM0390 Real-time clock (RTC) 22.3.9 RTC reference clock detection The RTC calendar update can be synchronized to a reference clock RTC_REFIN, usually the mains (50 or 60 Hz). The RTC_REFIN reference clock should have a higher precision than the 32.768 kHz LSE clock. When the RTC_REFIN detection is enabled (REFCKON bit of RTC_CR set to 1), the calendar is still clocked by the LSE, and RTC_REFIN is used to compensate for the imprecision of the calendar update frequency (1 Hz).
Page 662: Rtc Smooth Digital Calibration
Real-time clock (RTC) RM0390 When positive calibration is enabled (DCS = ‘0’), 2 ck_apre cycles are added every minute (around 15360 ck_apre cycles) for 2xDC minutes. This causes the calendar to be updated sooner, thereby adjusting the effective RTC frequency to be a bit higher. When negative calibration is enabled (DCS = ‘1’), 1 ck_apre cycle is removed every minute (around 15360 ck_apre cycles) for 2xDC minutes.
Page 663 RM0390 Real-time clock (RTC) The smooth calibration register (RTC_CALR) specifies the number of RTCCLK clock cycles to be masked during the 32-second cycle: • Setting the bit CALM[0] to 1 causes exactly one pulse to be masked during the 32- second cycle.
Page 664: Timestamp Function
Real-time clock (RTC) RM0390 Verifying the RTC calibration RTC precision is performed by measuring the precise frequency of RTCCLK and calculating the correct CALM value and CALP values. An optional 1 Hz output is provided to allow applications to measure and verify the RTC precision. Measuring the precise frequency of the RTC over a limited interval can result in a measurement error of up to 2 RTCCLK clock cycles over the measurement period, depending on how the digital calibration cycle is aligned with the measurement period.
Page 665: Tamper Detection
RM0390 Real-time clock (RTC) If a new timestamp event is detected while the timestamp flag (TSF) is already set, the timestamp overflow flag (TSOVF) flag is set and the timestamp registers (RTC_TSTR and RTC_TSDR) maintain the results of the previous event. Note: TSF is set 2 ck_apre cycles after the timestamp event occurs due to synchronization process.
Page 666 Real-time clock (RTC) RM0390 Timestamp on tamper event With TAMPTS set to ‘1 , any tamper event causes a timestamp to occur. In this case, either the TSF bit or the TSOVF bit are set in RTC_ISR, in the same manner as if a normal timestamp event occurs.
Page 667: Calibration Clock Output
RM0390 Real-time clock (RTC) (see Section 22.6.17). TAMPE bit must be cleared when TAMP1INSEL is modified to avoid unwanted setting of TAMPF. The TAMPER 2 alternate function corresponds to RTC_TAMP2 pin. 22.3.14 Calibration clock output When the COE bit is set to 1 in the RTC_CR register, a reference clock is provided on the RTC_CALIB device output.
Page 668: Rtc And Low Power Modes
Real-time clock (RTC) RM0390 22.4 RTC and low power modes Table 124. Effect of low power modes on RTC Mode Description No effect Sleep RTC interrupts cause the device to exit the Sleep mode. The RTC remains active when the RTC clock source is LSE or LSI. RTC alarm, RTC Stop tamper event, RTC time stamp event, and RTC Wakeup cause the device to exit the Stop mode.
Page 669: Table 125. Interrupt Control Bits
RM0390 Real-time clock (RTC) Table 125. Interrupt control bits Enable Exit the Exit the Exit the Interrupt event Event flag control Sleep Stop Standby mode mode mode Alarm A ALRAF ALRAIE Alarm B ALRBF ALRBIE Wakeup WUTF WUTIE TimeStamp TSIE Tamper1 detection TAMP1F TAMPIE...
Page 670: Rtc Registers
Bits 14:12 MNT[2:0]: Minute tens in BCD format Bits 11:8 MNU[3:0]: Minute units in BCD format Bit 7 Reserved, must be kept at reset value. Bits 6:4 ST[2:0]: Second tens in BCD format Bits 3:0 SU[3:0]: Second units in BCD format Note: This register is write protected.
Page 671: Rtc Date Register (Rtc_Dr)
RM0390 Real-time clock (RTC) 22.6.2 RTC date register (RTC_DR) The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration Reading the calendar. Address offset: 0x04 Backup domain reset value: 0x0000_2101 System reset: 0x0000 2101 when BYPSHAD = 0.
Page 672: Rtc Control Register (Rtc_Cr)
Real-time clock (RTC) RM0390 22.6.3 RTC control register (RTC_CR) Address offset: 0x08 Backup domain reset value: 0x0000 0000 System reset: not affected Res. Res. Res. Res. Res. Res. Res. Res. OSEL[1:0] COSEL BKP SUB1H ADD1H TSIE WUTIE ALRBIE ALRAIE WUTE ALRBE ALRAE DCE FMT BYPSHAD REFCKON TSEDGE WUCKSEL[2:0] Bits 31:24 Reserved, must be kept at reset value.
Page 673 RM0390 Real-time clock (RTC) Bit 16 ADD1H: Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0. 0: No effect 1: Adds 1 hour to the current time. This can be used for summer time change Bit 15 TSIE: Timestamp interrupt enable 0: Timestamp Interrupt disable 1: Timestamp Interrupt enable...
Page 674: Rtc Initialization And Status Register (Rtc_Isr)
Real-time clock (RTC) RM0390 Bit 4 REFCKON: Reference clock detection enable (50 or 60 Hz) 0: Reference clock detection disabled 1: Reference clock detection enabled Note: PREDIV_S must be 0x00FF. Bit 3 TSEDGE: Timestamp event active edge 0: TIMESTAMP rising edge generates a timestamp event 1: TIMESTAMP falling edge generates a timestamp event TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting Bits 2:0 WUCKSEL[2:0]: Wakeup clock selection...
Page 675 RM0390 Real-time clock (RTC) Bit 14 TAMP2F: TAMPER2 detection flag This flag is set by hardware when a tamper detection event is detected on tamper input 2. It is cleared by software writing 0. Bit 13 TAMP1F: Tamper detection flag This flag is set by hardware when a tamper detection event is detected.
Page 676: Rtc Prescaler Register (Rtc_Prer)
Real-time clock (RTC) RM0390 Bit 4 INITS: Initialization status flag This bit is set by hardware when the calendar year field is different from 0 (backup domain reset value state). 0: Calendar has not been initialized 1: Calendar has been initialized Bit 3 SHPF: Shift operation pending 0: No shift operation is pending 1: A shift operation is pending...
Page 677: Rtc Wakeup Timer Register (Rtc_Wutr)
RM0390 Real-time clock (RTC) Bits 31:23 Reserved, must be kept at reset value Bits 22:16 PREDIV_A[6:0]: Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1) Bit 15 Reserved, must be kept at reset value. Bits 14:0 PREDIV_S[14:0]: Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1) Note:...
Page 678 Real-time clock (RTC) RM0390 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DC[4:0] Bits 31:8 Reserved, must be kept at reset value Bit 7 DCS: Digital calibration sign 0: Positive calibration: calendar update frequency is increased 1: Negative calibration: calendar update frequency is decreased...
Page 679: Rtc Alarm A Register (Rtc_Alrmar)
Bit 7 MSK1: Alarm A seconds mask 0: Alarm A set if the seconds match 1: Seconds don’t care in Alarm A comparison Bits 6:4 ST[2:0]: Second tens in BCD format. Bits 3:0 SU[3:0]: Second units in BCD format. Note: This register can be written only when ALRAWF is set to 1 in RTC_ISR, or in initialization mode.
Page 680: Rtc Alarm B Register (Rtc_Alrmbr)
Bit 7 MSK1: Alarm B seconds mask 0: Alarm B set if the seconds match 1: Seconds don’t care in Alarm B comparison Bits 6:4 ST[2:0]: Second tens in BCD format Bits 3:0 SU[3:0]: Second units in BCD format Note: This register can be written only when ALRBWF is set to 1 in RTC_ISR, or in initialization mode.
Page 681: Rtc Write Protection Register (Rtc_Wpr)
RM0390 Real-time clock (RTC) 22.6.10 RTC write protection register (RTC_WPR) Address offset: 0x24 Backup domain reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 682: Rtc Shift Control Register (Rtc_Shiftr)
Real-time clock (RTC) RM0390 22.6.12 RTC shift control register (RTC_SHIFTR) Address offset: 0x2C Backup domain reset value: 0x0000 0000 System reset: not affected ADD1S Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SUBFS[14:0] Bit 31 ADD1S: Add one second 0: No effect...
Page 683: Rtc Time Stamp Time Register (Rtc_Tstr)
Bits 14:12 MNT[2:0]: Minute tens in BCD format. Bits 11:8 MNU[3:0]: Minute units in BCD format. Bit 7 Reserved, must be kept at reset value. Bits 6:4 ST[2:0]: Second tens in BCD format. Bits 3:0 SU[3:0]: Second units in BCD format. Note: The content of this register is valid only when TSF is set to 1 in RTC_ISR.
Page 684: Rtc Timestamp Sub Second Register (Rtc_Tsssr)
Real-time clock (RTC) RM0390 Bits 31:16 Reserved, must be kept at reset value. Bits 15:13 WDU[1:0]: Week day units Bit 12 MT: Month tens in BCD format Bits 11:8 MU[3:0]: Month units in BCD format Bits 7:6 Reserved, must be kept at reset value. Bits 5:4 DT[1:0]: Date tens in BCD format Bits 3:0 DU[3:0]: Date units in BCD format Note:...
Page 685: Rtc Tamper And Alternate Function Configuration Register
RM0390 Real-time clock (RTC) Bits 31:16 Reserved, must be kept at reset value Bit 15 CALP: Increase frequency of RTC by 488.5 ppm 0: No RTCCLK pulses are added. 1: One RTCCLK pulse is effectively inserted every 2 pulses (frequency increased by 488.5 ppm).
Page 686 Real-time clock (RTC) RM0390 Bits 31:19 Reserved, must be kept at reset value. Always read as 0. Bit 18 ALARMOUTTYPE: RTC_ALARM output type 0: RTC_ALARM is an open-drain output 1: RTC_ALARM is a push-pull output Bit 17 TSINSEL: TIMESTAMP mapping 0: RTC_AF1 used as TIMESTAMP 1: RTC_AF2 used as TIMESTAMP Bit 16 TAMP1INSEL: TAMPER1 mapping...
Page 687: Rtc Alarm A Sub Second Register (Rtc_Alrmassr)
RM0390 Real-time clock (RTC) Bits 6:5 Reserved. Always read as 0. Bit 4 TAMP2TRG: Active level for tamper 2 if TAMPFLT != 00 0: TAMPER2 staying low triggers a tamper detection event. 1: TAMPER2 staying high triggers a tamper detection event. if TAMPFLT = 00: 0: TAMPER2 rising edge triggers a tamper detection event.
Page 688: Rtc Alarm B Sub Second Register (Rtc_Alrmbssr)
Real-time clock (RTC) RM0390 Bits 31:28 Reserved, must be kept at reset value Bits 27:24 MASKSS[3:0]: Mask the most-significant bits starting at this bit 0: No comparison on sub seconds for Alarm A. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match).
Page 689: Rtc Backup Registers (Rtc_Bkpxr)
RM0390 Real-time clock (RTC) Bits 31:28 Reserved, must be kept at reset value Bits 27:24 MASKSS[3:0]: Mask the most-significant bits starting at this bit 0x0: No comparison on sub seconds for Alarm B. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match).
Page 690: Rtc Register Map
Real-time clock (RTC) RM0390 22.6.21 RTC register map Table 126. RTC register map and reset values Offset Register RTC_TR HU[3:0] MNT[2:0] MNU[3:0] ST[2:0] SU[3:0] [1:0] 0x00 Reset value RTC_DR YT[3:0] YU[3:0] WDU[2:0] MU[3:0] DU[3:0] [1:0] 0x04 Reset value WCKSEL OSEL...
Page 691 RM0390 Real-time clock (RTC) Table 126. RTC register map and reset values (continued) Offset Register RTC_TSTR HU[3:0] MNU[3:0] ST[2:0] SU[3:0] 0x30 Reset value RTC_TSSSR SS[15:0] 0x38 Reset value RTC_ CALR CALM[8:0] 0x3C Reset value RTC_TAFCR 0x40 Reset value RTC_ MASKSS[3:0]...
Page 692: Fast-Mode Plus Inter-Integrated Circuit (Fmpi2C) Interface
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 23.1 Introduction The I C (inter-integrated circuit) bus interface handles communications between the microcontroller and the serial I C bus. It provides multimaster capability, and controls all I bus-specific sequencing, protocol, arbitration and timing.
Page 693: Fmpi2C Implementation
RM0390 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface The following additional features are also available depending on the product implementation (see Section 23.3: FMPI2C implementation): • SMBus specification rev 3.0 compatibility: – Hardware PEC (Packet Error Checking) generation and verification with ACK control –...
Page 694: Fmpi2C Block Diagram
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390 23.4.1 FMPI2C block diagram The block diagram of the FMPI2C interface is shown in Figure 241. Figure 241. FMPI2C block diagram The FMPI2C is clocked by an independent clock source which allows to the FMPI2C to operate independently from the PCLK frequency.
Page 695: Fmpi2C Clock Requirements
RM0390 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface For I2C I/Os supporting 20 mA output current drive for Fast-mode Plus operation, the driving capability is enabled through control bits in the system configuration controller (SYSCFG). Refer to Section 23.3: FMPI2C implementation. 23.4.2 FMPI2C clock requirements The FMPI2C kernel is clocked by FMPI2CCLK.
Page 696: Fmpi2C Initialization
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390 Figure 242. I C bus protocol Acknowledge can be enabled or disabled by software. The FMPI2C interface addresses can be selected by software. 23.4.4 FMPI2C initialization Enabling and disabling the peripheral The FMPI2C peripheral clock must be configured and enabled in the clock controller (refer Section 6: Reset and clock control (RCC)).
Page 697: Figure 243. Setup And Hold Timings
RM0390 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface FMPI2C timings The timings must be configured in order to guarantee a correct data hold and setup time, used in master and slave modes. This is done by programming the PRESC[3:0], SCLDEL[3:0] and SDADEL[3:0] bits in the FMPI2C_TIMINGR register. The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C configuration window Figure 243.
Page 698: Table 128. I2C-Smbus Specification Data Setup And Hold Times
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390 • When the SCL falling edge is internally detected, a delay is inserted before sending SDA output. This delay is where = SDADEL x t = (PRESC+1) SDADEL PRESC I2CCLK PRESC I2CCLK impacts the hold time SDADEL HD;DAT.
Page 699 RM0390 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface The SDA and SCL transition time values to be used are the ones in the application. Using the maximum values from the standard increases the constraints for the SDADEL and SCLDEL calculation, but ensures the feature whatever the application. Note: At every clock pulse, after SCL falling edge detection, the I2C master or slave stretches SCL low during at least [(SDADEL+SCLDEL+1) x (PRESC+1) + 1] x t...
Page 700: Software Reset
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390 Figure 244. FMPI2C initialization flowchart 23.4.5 Software reset A software reset can be performed by clearing the PE bit in the FMPI2C_CR1 register. In that case FMPI2C lines SCL and SDA are released. Internal states machines are reset and communication control bits, as well as status bits come back to their reset value.
Page 701: Data Transfer
RM0390 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 23.4.6 Data transfer The data transfer is managed through transmit and receive data registers and a shift register. Reception The SDA input fills the shift register. After the 8th SCL pulse (when the complete data byte is received), the shift register is copied into FMPI2C_RXDR register if it is empty (RXNE=0).
Page 702: Figure 246. Data Transmission
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390 Transmission If the FMPI2C_TXDR register is not empty (TXE=0), its content is copied into the shift register after the 9th SCL pulse (the Acknowledge pulse). Then the shift register content is shifted out on SDA line. If TXE=1, meaning that no data is written yet in FMPI2C_TXDR, SCL line is stretched low until FMPI2C_TXDR is written.
Page 703: Fmpi2C Slave Mode
RM0390 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface When RELOAD=0 in master mode, the counter can be used in 2 modes: • Automatic end mode (AUTOEND = ‘1’ in the FMPI2C_CR2 register). In this mode, the master automatically sends a STOP condition once the number of bytes programmed in the NBYTES[7:0] bit field has been transferred.
Page 704 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390 By default, the slave uses its clock stretching capability, which means that it stretches the SCL signal at low level when needed, in order to perform software actions. If the master does not support clock stretching, the FMPI2C must be configured with NOSTRETCH=1 in the FMPI2C_CR1 register.
Page 705: Figure 247. Slave Initialization Flowchart
RM0390 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Slave Byte Control mode In order to allow byte ACK control in slave reception mode, Slave Byte Control mode must be enabled by setting the SBC bit in the FMPI2C_CR1 register. This is required to be compliant with SMBus standards.
Page 706 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390 Slave transmitter A transmit interrupt status (TXIS) is generated when the FMPI2C_TXDR register becomes empty. An interrupt is generated if the TXIE bit is set in the FMPI2C_CR1 register. The TXIS bit is cleared when the FMPI2C_TXDR register is written with the next data byte to be transmitted.
Page 707: Figure 248. Transfer Sequence Flowchart For Fmpi2C Slave Transmitter, Nostretch=0
RM0390 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 248. Transfer sequence flowchart for FMPI2C slave transmitter, NOSTRETCH=0 RM0390 Rev 4 707/1328...
Page 708: Figure 249. Transfer Sequence Flowchart For Fmpi2C Slave Transmitter, Nostretch=1
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390 Figure 249. Transfer sequence flowchart for FMPI2C slave transmitter, NOSTRETCH=1 708/1328 RM0390 Rev 4...
Page 709: Figure 250. Transfer Bus Diagrams For Fmpi2C Slave Transmitter
RM0390 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 250. Transfer bus diagrams for FMPI2C slave transmitter RM0390 Rev 4 709/1328...
Page 710: Figure 251. Transfer Sequence Flowchart For Slave Receiver With Nostretch=0
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390 Slave receiver RXNE is set in FMPI2C_ISR when the FMPI2C_RXDR is full, and generates an interrupt if RXIE is set in FMPI2C_CR1. RXNE is cleared when FMPI2C_RXDR is read. When a STOP is received and STOPIE is set in FMPI2C_CR1, STOPF is set in FMPI2C_ISR and an interrupt is generated.
Page 711: Figure 252. Transfer Sequence Flowchart For Slave Receiver With Nostretch=1
RM0390 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 252. Transfer sequence flowchart for slave receiver with NOSTRETCH=1 Figure 253. Transfer bus diagrams for FMPI2C slave receiver RM0390 Rev 4 711/1328...
Page 712: Fmpi2C Master Mode
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390 23.4.8 FMPI2C master mode FMPI2C master initialization Before enabling the peripheral, the FMPI2C master clock must be configured by setting the SCLH and SCLL bits in the FMPI2C_TIMINGR register. The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C Configuration window.
Page 713: Figure 254. Master Clock Generation
RM0390 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 254. Master clock generation Caution: In order to be I C or SMBus compliant, the master clock must respect the timings given below: RM0390 Rev 4 713/1328...
Page 714: Table 130. I2C-Smbus Specification Clock Timings
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390 Table 130. I C-SMBUS specification clock timings Standard- Fast-mode Fast-mode SMBUS mode (Sm) (Fm) Plus (Fm+) Symbol Parameter Unit SCL clock frequency 1000 Hold time (repeated) START condition 0.26 µs HD:STA Set-up time for a repeated START 0.26 µs SU:STA...
Page 715: Figure 255. Master Initialization Flowchart
RM0390 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface master will re-launch automatically the slave address transmission until ACK is received. In this case ADDRCF must be set if a NACK is received from the slave, in order to stop sending the slave address. If the FMPI2C is addressed as a slave (ADDR=1) while the START bit is set, the FMPI2C switches to slave mode and the START bit is cleared when the ADDRCF bit is set.
Page 716: Figure 257. 10-Bit Address Read Access With Head10R=1
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390 • If the master addresses a 10-bit address slave, transmits data to this slave and then reads data from the same slave, a master transmission flow must be done first. Then a repeated start is set with the 10 bit slave address configured with HEAD10R=1. In this case the master sends this sequence: ReStart + Slave address 10-bit header Read.
Page 717: Figure 258. Transfer Sequence Flowchart For Fmpi2C Master Transmitter For N≤255 Bytes
RM0390 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 258. Transfer sequence flowchart for FMPI2C master transmitter for N≤255 bytes RM0390 Rev 4 717/1328...
Page 718: Figure 259. Transfer Sequence Flowchart For Fmpi2C Master Transmitter For N>255 Bytes
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390 Figure 259. Transfer sequence flowchart for FMPI2C master transmitter for N>255 bytes 718/1328 RM0390 Rev 4...
Page 719: Figure 260. Transfer Bus Diagrams For Fmpi2C Master Transmitter
RM0390 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 260. Transfer bus diagrams for FMPI2C master transmitter RM0390 Rev 4 719/1328...
Page 720 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390 Master receiver In the case of a read transfer, the RXNE flag is set after each byte reception, after the 8th SCL pulse. An RXNE event generates an interrupt if the RXIE bit is set in the FMPI2C_CR1 register.
Page 721: Figure 261. Transfer Sequence Flowchart For Fmpi2C Master Receiver For N≤255 Bytes
RM0390 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 261. Transfer sequence flowchart for FMPI2C master receiver for N≤255 bytes RM0390 Rev 4 721/1328...
Page 722: Figure 262. Transfer Sequence Flowchart For Fmpi2C Master Receiver For N >255 Bytes
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390 Figure 262. Transfer sequence flowchart for FMPI2C master receiver for N >255 bytes 722/1328 RM0390 Rev 4...
Page 723: Figure 263. Transfer Bus Diagrams For Fmpi2C Master Receiver
RM0390 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 263. Transfer bus diagrams for FMPI2C master receiver RM0390 Rev 4 723/1328...
Page 724: Fmpi2C_Timingr Register Configuration Examples
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390 23.4.9 FMPI2C_TIMINGR register configuration examples The tables below provide examples of how to program the FMPI2C_TIMINGR to obtain timings compliant with the I C specification. In order to get more accurate configuration values, the STM32CubeMX tool (I2C Configuration window) should be used. Table 131.
Page 725: Smbus Specific Features
RM0390 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 2. t minimum value is 4 x t = 250 ns. Example with t = 1000 ns SYNC1 + SYNC2 I2CCLK SYNC1 + SYNC2 minimum value is 4 x t = 250 ns. Example with t = 750 ns SYNC1 + SYNC2...
Page 726 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390 Received Command and Data acknowledge control A SMBus receiver must be able to NACK each received command or data. In order to allow the ACK control in slave mode, the Slave Byte Control mode must be enabled by setting SBC bit in FMPI2C_CR1 register.
Page 727: Table 133. Smbus Timeout Specifications
RM0390 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Timeouts This peripheral embeds hardware timers in order to be compliant with the 3 timeouts defined in SMBus specification. Table 133. SMBus timeout specifications Limits Symbol Parameter Unit Detect clock low timeout TIMEOUT Cumulative clock low extend time (slave device) LOW:SEXT Cumulative clock low extend time (master device)
Page 728: Smbus Initialization
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390 Bus idle detection A master can assume that the bus is free if it detects that the clock and data signals have been high for t greater than t . (refer to Table 128: I2C-SMBUS specification data IDLE HIGH setup and hold...
Page 729: Table 134. Smbus With Pec Configuration
RM0390 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Table 134. SMBUS with PEC configuration Mode SBC bit RELOAD bit AUTOEND bit PECBYTE bit Master Tx/Rx NBYTES + PEC+ STOP Master Tx/Rx NBYTES + PEC + ReSTART Slave Tx/Rx with PEC Timeout detection The timeout detection is enabled by setting the TIMOUTEN and TEXTEN bits in the FMPI2C_TIMEOUTR register.
Page 730: Smbus: Fmpi2C_Timeoutr Register Configuration Examples
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390 Refer to Table 137: Examples of TIMEOUTA settings for various FMPI2CCLK frequencies (max tIDLE = 50 µs) Caution: Changing the TIMEOUTA and TIDLE configuration is not allowed when the TIMEOUTEN is set. SMBus: 23.4.12 FMPI2C_TIMEOUTR register configuration examples This section is relevant only when SMBus feature is supported.
Page 731: Figure 265. Transfer Sequence Flowchart For Smbus Slave Transmitter N Bytes + Pec
RM0390 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface FMPI2C_PECR register is automatically transmitted if the master requests an extra byte after the NBYTES-1 data transfer. Caution: The PECBYTE bit has no effect when the RELOAD bit is set. Figure 265. Transfer sequence flowchart for SMBus slave transmitter N bytes + PEC RM0390 Rev 4 731/1328...
Page 732: Figure 266. Transfer Bus Diagrams For Smbus Slave Transmitter (Sbc=1)
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390 Figure 266. Transfer bus diagrams for SMBus slave transmitter (SBC=1) SMBus Slave receiver When the FMPI2C is used in SMBus mode, SBC must be programmed to ‘1’ in order to allow the PEC checking at the end of the programmed number of data bytes. In order to allow the ACK control of each byte, the reload mode must be selected (RELOAD=1).
Page 733: Figure 267. Transfer Sequence Flowchart For Smbus Slave Receiver N Bytes + Pec
RM0390 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 267. Transfer sequence flowchart for SMBus slave receiver N Bytes + PEC RM0390 Rev 4 733/1328...
Page 734: Figure 268. Bus Transfer Diagrams For Smbus Slave Receiver (Sbc=1)
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390 Figure 268. Bus transfer diagrams for SMBus slave receiver (SBC=1) This section is relevant only when SMBus feature is supported. Refer to Section 23.3: FMPI2C implementation. In addition to FMPI2C master transfer management (refer to Section 23.4.8: FMPI2C master mode) some additional software flowcharts are provided to support SMBus.
Page 735: Figure 269. Bus Transfer Diagrams For Smbus Master Transmitter
RM0390 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface When the SMBus master wants to send a RESTART condition after the PEC, software mode must be selected (AUTOEND=0). In this case, once NBYTES-1 have been transmitted, the FMPI2C_PECR register content is transmitted and the TC flag is set after the PEC transmission, stretching the SCL line low.
Page 736 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390 SMBus Master receiver When the SMBus master wants to receive the PEC followed by a STOP at the end of the transfer, automatic end mode can be selected (AUTOEND=1). The PECBYTE bit must be set and the slave address must be programmed, before setting the START bit.
Page 737: Error Conditions
RM0390 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 270. Bus transfer diagrams for SMBus master receiver 23.4.14 Error conditions The following are the error conditions which may cause communication to fail. Bus error (BERR) A bus error is detected when a START or a STOP condition is detected and is not located after a multiple of 9 SCL clock pulses.
Page 738 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390 In case of a misplaced START or RESTART detection in slave mode, the FMPI2C enters address recognition state like for a correct START condition. When a bus error is detected, the BERR flag is set in the FMPI2C_ISR register, and an interrupt is generated if the ERRIE bit is set in the FMPI2C_CR1 register.
Page 739: Dma Requests
RM0390 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Timeout Error (TIMEOUT) This section is relevant only when the SMBus feature is supported. Refer to Section 23.3: FMPI2C implementation. A timeout error occurs for any of these conditions: • TIDLE=0 and SCL remained low for the time defined in the TIMEOUTA[11:0] bits: this is used to detect a SMBus timeout.
Page 740: Debug Mode
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390 initialized before setting the START bit. The end of transfer is managed with the NBYTES counter. Refer to Master transmitter on page 716. • In slave mode: – With NOSTRETCH=0, when all data are transferred using DMA, the DMA must be initialized before the address match event, or in ADDR interrupt subroutine, before clearing ADDR.
Page 741: Fmpi2C Interrupts
RM0390 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 23.6 FMPI2C interrupts The table below gives the list of FMPI2C interrupt requests. Table 139. FMPI2C Interrupt requests Event flag/Interrupt Interrupt enable Interrupt event Event flag clearing method control bit Receive buffer not empty RXNE Read FMPI2C_RXDR register RXIE...
Page 742: Fmpi2C Registers
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390 23.7 FMPI2C registers Refer to Section 1.1 on page 51 for a list of abbreviations used in register descriptions. The peripheral registers are accessed by words (32-bit). 23.7.1 Control register 1 (FMPI2C_CR1) Address offset: 0x00 Reset value: 0x0000 0000 Access: No wait states, except if a write access occurs while a write access to this register is ongoing.
Page 743 RM0390 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Bit 20 SMBHEN: SMBus Host address enable 0: Host address disabled. Address 0b0001000x is NACKed. 1: Host address enabled. Address 0b0001000x is ACKed. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to Section 23.3: FMPI2C implementation.
Page 744 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390 Bit 7 ERRIE: Error interrupts enable 0: Error detection interrupts disabled 1: Error detection interrupts enabled Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT)
Page 745: Control Register 2 (Fmpi2C_Cr2)
RM0390 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 23.7.2 Control register 2 (FMPI2C_CR2) Address offset: 0x04 Reset value: 0x0000 0000 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed.
Page 746 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390 Bit 15 NACK: NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. 0: an ACK is sent after current received byte.
Page 747 RM0390 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Bits 9:8 SADD[9:8]: Slave address bit 9:8 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits are don’t care In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 9:8 of the slave address to be sent Note: Changing these bits when the START bit is set is not allowed.
Page 748: Own Address 1 Register (Fmpi2C_Oar1)
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390 23.7.3 Own address 1 register (FMPI2C_OAR1) Address offset: 0x08 Reset value: 0x0000 0000 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed.
Page 749: Own Address 2 Register (Fmpi2C_Oar2)
RM0390 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 23.7.4 Own address 2 register (FMPI2C_OAR2) Address offset: 0x0C Reset value: 0x0000 0000 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed.
Page 750: Timing Register (Fmpi2C_Timingr)
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390 23.7.5 Timing register (FMPI2C_TIMINGR) Address offset: 0x10 Reset value: 0x0000 0000 Access: No wait states PRESC[3:0] Res. Res. Res. Res. SCLDEL[3:0] SDADEL[3:0] SCLH[7:0] SCLL[7:0] Bits 31:28 PRESC[3:0]: Timing prescaler This field is used to prescale FMPI2CCLK in order to generate the clock period t used for PRESC data setup and hold counters (refer to...
Page 751: Timeout Register (Fmpi2C_Timeoutr)
RM0390 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 23.7.6 Timeout register (FMPI2C_TIMEOUTR) Address offset: 0x14 Reset value: 0x0000 0000 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed.
Page 752: Interrupt And Status Register (Fmpi2C_Isr)
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390 23.7.7 Interrupt and status register (FMPI2C_ISR) Address offset: 0x18 Reset value: 0x0000 0001 Access: No wait states Res. Res. Res. Res. Res. Res. Res. Res. ADDCODE[6:0] TIME BUSY Res. ALERT ARLO BERR STOPF NACKF ADDR RXNE TXIS Bits 31:24 Reserved, must be kept at reset value.
Page 753 RM0390 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Bit 11 PECERR: PEC Error in reception This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit.
Page 754: Interrupt Clear Register (Fmpi2C_Icr)
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390 Bit 2 RXNE: Receive data register not empty (receivers) This bit is set by hardware when the received data is copied into the FMPI2C_RXDR register, and is ready to be read. It is cleared when FMPI2C_RXDR is read. Note: This bit is cleared by hardware when PE=0.
Page 755: Pec Register (Fmpi2C_Pecr)
RM0390 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Bit 10 OVRCF: Overrun/Underrun flag clear Writing 1 to this bit clears the OVR flag in the FMPI2C_ISR register. Bit 9 ARLOCF: Arbitration Lost flag clear Writing 1 to this bit clears the ARLO flag in the FMPI2C_ISR register. Bit 8 BERRCF: Bus error flag clear Writing 1 to this bit clears the BERRF flag in the FMPI2C_ISR register.
Page 756: Receive Data Register (Fmpi2C_Rxdr)
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390 23.7.10 Receive data register (FMPI2C_RXDR) Address offset: 0x24 Reset value: 0x0000 0000 Access: No wait states Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 757: Fmpi2C Register Map
RM0390 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 23.7.12 FMPI2C register map The table below provides the FMPI2C register map and reset values. Table 140. FMPI2C register map and reset values Register Offset name FMPI2C_CR1 DNF[3:0] Reset value FMPI2C_CR2 NBYTES[7:0] SADD[9:0] Reset value FMPI2C_OAR1 OA1[9:0]...
Page 758 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390 Table 140. FMPI2C register map and reset values (continued) Register Offset name FMPI2C_TXDR TXDATA[7:0] 0x28 Reset value Refer to Section 2.2.2 on page 56 for the register boundary addresses. 758/1328 RM0390 Rev 4...
Page 759: Inter-Integrated Circuit (I 2 C) Interface
RM0390 Inter-integrated circuit (I C) interface Inter-integrated circuit (I C) interface 24.1 C introduction C (inter-integrated circuit) bus Interface serves as an interface between the microcontroller and the serial I C bus. It provides multimaster capability, and controls all I C bus-specific sequencing, protocol, arbitration and timing.
Page 760: I 2 C Main Features
Inter-integrated circuit (I C) interface RM0390 24.2 C main features • Parallel-bus/I C protocol converter • Multimaster capability: the same interface can act as Master or Slave • C Master features: – Clock generation – Start and Stop generation • C Slave features: –...
Page 761: C Functional Description
RM0390 Inter-integrated circuit (I C) interface Note: Some of the above features may not be available in certain products. The user should refer to the product data sheet, to identify the specific features supported by the I C interface implementation. 24.3 C functional description In addition to receiving and transmitting data, this interface converts it from serial to parallel...
Page 762: I2C Slave Mode
Inter-integrated circuit (I C) interface RM0390 The block diagram of the I C interface is shown in Figure 273. Figure 273. I C block diagram 1. SMBA is an optional signal in SMBus mode. This signal is not applicable if SMBus is disabled. 24.3.2 C slave mode By default the I...
Page 763 RM0390 Inter-integrated circuit (I C) interface Note: In 10-bit addressing mode, the comparison includes the header sequence (11110xx0), where xx denotes the two most significant bits of the address. Header or address not matched: the interface ignores it and waits for another Start condition.
Page 764: Figure 274. Transfer Sequence Diagram For Slave Transmitter
Inter-integrated circuit (I C) interface RM0390 Figure 274. Transfer sequence diagram for slave transmitter 1. The EV1 and EV3_1 events stretch SCL low until the end of the corresponding software sequence. 2. The EV3 event stretches SCL low if the software sequence is not completed before the end of the next byte transmission Slave receiver Following the address reception and after clearing ADDR, the slave receives bytes from the...
Page 765: I2C Master Mode
RM0390 Inter-integrated circuit (I C) interface Figure 275. Transfer sequence diagram for slave receiver 1. The EV1 event stretches SCL low until the end of the corresponding software sequence. 2. The EV2 event stretches SCL low if the software sequence is not completed before the end of the next byte reception.
Page 766 Inter-integrated circuit (I C) interface RM0390 SCL master clock generation The CCR bits are used to generate the high and low level of the SCL clock, starting from the generation of the rising and falling edge (respectively). As a slave may stretch the SCL line, the peripheral checks the SCL input from the bus at the end of the time programmed in TRISE bits after rising edge generation.
Page 767 RM0390 Inter-integrated circuit (I C) interface The master can decide to enter Transmitter or Receiver mode depending on the LSB of the slave address sent. • In 7-bit addressing mode, – To enter Transmitter mode, a master sends the slave address with LSB reset. –...
Page 768: Figure 276. Transfer Sequence Diagram For Master Transmitter
Inter-integrated circuit (I C) interface RM0390 Figure 276. Transfer sequence diagram for master transmitter 1. The EV5, EV6, EV9, EV8_1 and EV8_2 events stretch SCL low until the end of the corresponding software sequence. 2. The EV8 event stretches SCL low if the software sequence is not complete before the end of the next byte transmission. 768/1328 RM0390 Rev 4...
Page 769 RM0390 Inter-integrated circuit (I C) interface Master receiver Following the address transmission and after clearing ADDR, the I C interface enters Master Receiver mode. In this mode the interface receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence: An acknowledge pulse if the ACK bit is set The RxNE bit is set and an interrupt is generated if the ITEVFEN and ITBUFEN bits are...
Page 770: Figure 277. Transfer Sequence Diagram For Master Receiver
Inter-integrated circuit (I C) interface RM0390 Figure 277. Transfer sequence diagram for master receiver 1. If a single byte is received, it is NA. 2. The EV5, EV6 and EV9 events stretch SCL low until the end of the corresponding software sequence. 3.
Page 771: Error Conditions
RM0390 Inter-integrated circuit (I C) interface For N >2 -byte reception, from N-2 data reception • Wait until BTF = 1 (data N-2 in DR, data N-1 in shift register, SCL stretched low until data N-2 is read) • Set ACK low •...
Page 772: Programmable Noise Filter
Inter-integrated circuit (I C) interface RM0390 Overrun/underrun error (OVR) An overrun error can occur in slave mode when clock stretching is disabled and the I interface is receiving data. The interface has received a byte (RxNE=1) and the data in DR has not been read, before the next byte is received by the interface.
Page 773: Sda/Scl Line Control
RM0390 Inter-integrated circuit (I C) interface Note: For each frequency range, the constraint is given based on the worst case which is the minimum frequency of the range. Greater DNF values can be used if the system can support maximum hold time violation. 24.3.6 SDA/SCL line control •...
Page 774: Table 142. Smbus Vs. I2C
Inter-integrated circuit (I C) interface RM0390 Table 142. SMBus vs. I SMBus Max. speed 100 kHz Max. speed 400 kHz Min. clock speed 10 kHz No minimum clock speed 35 ms clock low timeout No timeout Logic levels are fixed Logic levels are V dependent Different address types (reserved, dynamic etc.)
Page 775 RM0390 Inter-integrated circuit (I C) interface SMBus alert mode SMBus Alert is an optional signal with an interrupt line for devices that want to trade their ability to master for a pin. SMBA is a wired-AND signal just as the SCL and SDA signals are. SMBA is used in conjunction with the SMBus General Call Address.
Page 776: Dma Requests
Inter-integrated circuit (I C) interface RM0390 24.3.8 DMA requests DMA requests (when enabled) are generated only for data transfer. DMA requests are generated by Data Register becoming empty in transmission and Data Register becoming full in reception. The DMA must be initialized and enabled before the I2C data transfer. The DMAEN bit must be set in the I2C_CR2 register before the ADDR event.
Page 777: Packet Error Checking
RM0390 Inter-integrated circuit (I C) interface Reception using DMA DMA mode can be enabled for reception by setting the DMAEN bit in the I2C_CR2 register. Data will be loaded from the I2C_DR register to a Memory area configured using the DMA peripheral (refer to the DMA specification) whenever a data byte is received.
Page 778: I 2 C Interrupts
Inter-integrated circuit (I C) interface RM0390 be set before the ACK of the CRC reception in slave mode. It must be set when the ACK is set low in master mode. • A PECERR error flag/interrupt is also available in the I2C_SR1 register. •...
Page 779: Figure 278. I2C Interrupt Mapping Diagram
RM0390 Inter-integrated circuit (I C) interface Figure 278. I C interrupt mapping diagram ITEVFEN ADDR ADD10 STOPF it_event ITBUFEN RxNE ITERREN BERR ARLO it_error PECERR TIMEOUT SMBALERT RM0390 Rev 4 779/1328...
Page 780: I 2 C Debug Mode
Inter-integrated circuit (I C) interface RM0390 24.5 C debug mode ® When the microcontroller enters the debug mode (Cortex -M4 with FPU core halted), the SMBUS timeout either continues to work normally or stops, depending on the DBG_I2Cx_SMBUS_TIMEOUT configuration bits in the DBG module. For more details, refer to Section 33.16.2: Debug support for timers, watchdog, bxCAN and I2C.
Page 781 RM0390 Inter-integrated circuit (I C) interface Bit 11 POS: Acknowledge/PEC Position (for data reception) This bit is set and cleared by software and cleared by hardware when PE=0. 0: ACK bit controls the (N)ACK of the current byte being received in the shift register. The PEC bit indicates that current byte in shift register is a PEC.
Page 782: I 2 C Control Register 2 (I2C_Cr2)
Inter-integrated circuit (I C) interface RM0390 Bit 2 Reserved, must be kept at reset value Bit 1 SMBUS: SMBus mode 0: I C mode 1: SMBus mode Bit 0 PE: Peripheral enable 0: Peripheral disable 1: Peripheral enable Note: If this bit is reset while a communication is on going, the peripheral is disabled at the end of the current communication, when back to IDLE state.
Page 783 RM0390 Inter-integrated circuit (I C) interface ITERREN: Error interrupt enable 0: Error interrupt disabled 1: Error interrupt enabled This interrupt is generated when: – BERR = 1 – ARLO = 1 – AF = 1 – OVR = 1 – PECERR = 1 –...
Page 784: I 2 C Own Address Register 1 (I2C_Oar1)
Inter-integrated circuit (I C) interface RM0390 24.6.3 C Own address register 1 (I2C_OAR1) Address offset: 0x08 Reset value: 0x0000 Res. Res. Res. Res. Res. ADD[9:8] ADD[7:1] ADD0 MODE Bit 15 ADDMODE Addressing mode (slave mode) 0: 7-bit slave address (10-bit address not acknowledged) 1: 10-bit slave address (7-bit address not acknowledged) Bit 14 Should always be kept at 1 by software.
Page 785: C Data Register (I2C_Dr)
RM0390 Inter-integrated circuit (I C) interface 24.6.5 C Data register (I2C_DR) Address offset: 0x10 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. DR[7:0] Bits 15:8 Reserved, must be kept at reset value Bits 7:0 DR[7:0] 8-bit data register Byte received or to be transmitted to the bus.
Page 786 Inter-integrated circuit (I C) interface RM0390 Bit 15 SMBALERT: SMBus alert In SMBus host mode: 0: no SMBALERT 1: SMBALERT event occurred on pin In SMBus slave mode: 0: no SMBALERT response address header 1: SMBALERT response address header to SMBALERT LOW received –...
Page 787 RM0390 Inter-integrated circuit (I C) interface Bit 9 ARLO: Arbitration lost (master mode) 0: No Arbitration Lost detected 1: Arbitration Lost detected Set by hardware when the interface loses the arbitration of the bus to another master – Cleared by software writing 0, or by hardware when PE=0. After an ARLO event the interface switches back automatically to Slave mode (MSL=0).
Page 788 Inter-integrated circuit (I C) interface RM0390 Bit 3 ADD10: 10-bit header sent (Master mode) 0: No ADD10 event occurred. 1: Master has sent first address byte (header). – Set by hardware when the master has sent the first byte in 10-bit address mode. –...
Page 789: I 2 C Status Register 2 (I2C_Sr2)
RM0390 Inter-integrated circuit (I C) interface 24.6.7 C Status register 2 (I2C_SR2) Address offset: 0x18 Reset value: 0x0000 Note: Reading I2C_SR2 after reading I2C_SR1 clears the ADDR flag, even if the ADDR flag was set after reading I2C_SR1. Consequently, I2C_SR2 must be read only when ADDR is found set in I2C_SR1 or when the STOPF bit is cleared.
Page 790: I 2 C Clock Control Register (I2C_Ccr)
Inter-integrated circuit (I C) interface RM0390 Bit 2 TRA: Transmitter/receiver 0: Data bytes received 1: Data bytes transmitted This bit is set depending on the R/W bit of the address byte, at the end of total address phase. It is also cleared by hardware after detection of Stop condition (STOPF=1), repeated Start condition, loss of bus arbitration (ARLO=1), or when PE=0.
Page 791: C Trise Register (I2C_Trise)
RM0390 Inter-integrated circuit (I C) interface Bit 14 DUTY: Fm mode duty cycle 0: Fm mode t high 1: Fm mode t = 16/9 (see CCR) high Bits 13:12 Reserved, must be kept at reset value Bits 11:0 CCR[11:0]: Clock control register in Fm/Sm mode (Master mode) Controls the SCL clock in master mode.
Page 792: I 2 C Fltr Register (I2C_Fltr)
Inter-integrated circuit (I C) interface RM0390 24.6.10 C FLTR register (I2C_FLTR) Address offset: 0x24 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ANOFF DNF[3:0] Bits 15:5 Reserved, must be kept at reset value Bit 4 ANOFF: Analog noise filter OFF 0: Analog noise filter enable 1: Analog noise filter disable Note: ANOFF must be configured only when the I2C is disabled (PE = 0).
Page 793: I2C Register Map
RM0390 Inter-integrated circuit (I C) interface 24.6.11 C register map The table below provides the I C register map and reset values. Table 144. I C register map and reset values Offset Register I2C_CR1 0x00 Reset value I2C_CR2 FREQ[5:0] 0x04 Reset value ADD[ I2C_OAR1...
Page 794: Universal Synchronous Asynchronous Receiver
Universal synchronous asynchronous receiver transmitter (USART) RM0390 Universal synchronous asynchronous receiver transmitter (USART) 25.1 USART introduction The universal synchronous asynchronous receiver transmitter (USART) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The USART offers a very wide range of baud rates using a fractional baud rate generator.
Page 795: Usart Main Features
RM0390 Universal synchronous asynchronous receiver transmitter (USART) 25.2 USART main features • Full duplex, asynchronous communications • NRZ standard format (Mark/Space) • Configurable oversampling method by 16 or by 8 to give flexibility between speed and clock tolerance • Fractional baud rate generator systems –...
Page 796: Usart Implementation
Universal synchronous asynchronous receiver transmitter (USART) RM0390 – Receive data register full – Idle line received – Overrun error – Framing error – Noise error – Parity error • Multiprocessor communication - enter into mute mode if address match does not occur •...
Page 797 RM0390 Universal synchronous asynchronous receiver transmitter (USART) Through these pins, serial data is transmitted and received in normal USART mode as frames comprising: • An Idle Line prior to transmission or reception • A start bit • A data word (8 or 9 bits) least significant bit first •...
Page 798: Figure 279. Usart Block Diagram
Universal synchronous asynchronous receiver transmitter (USART) RM0390 Figure 279. USART block diagram PWDATA PRDATA Write Read (Data register) DR (CPU or DMA) (CPU or DMA) Receive data register (RDR) Transmit data register (TDR) IrDA SW_RX Receive Shift Register Transmit Shift Register ENDEC block IRDA_OUT...
Page 799: Usart Character Description
RM0390 Universal synchronous asynchronous receiver transmitter (USART) 25.4.1 USART character description Word length may be selected as being either 8 or 9 bits by programming the M bit in the USART_CR1 register (see Figure 280). The TX pin is in low state during the start bit. It is in high state during the stop bit. An Idle character is interpreted as an entire frame of “1”s followed by the start bit of the next frame that contains data (The number of “1”...
Page 800: Transmitter
Universal synchronous asynchronous receiver transmitter (USART) RM0390 25.4.2 Transmitter The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the transmit enable bit (TE) is set, the data in the transmit shift register is output on the TX pin and the corresponding clock pulses are output on the SCLK pin.
Page 801: Figure 281. Configurable Stop Bits
RM0390 Universal synchronous asynchronous receiver transmitter (USART) Figure 281. Configurable stop bits 8-bit Word length (M bit is reset) Possible Next data frame parity Data frame Next Start start Stop Bit2 Bit0 Bit1 Bit3 Bit4 Bit5 Bit6 Bit7 CLOCK **** ** LBCL bit controls last data clock pulse a) 1 Stop Bit Possible...
Page 802: Figure 282. Tc/Txe Behavior When Transmitting
Universal synchronous asynchronous receiver transmitter (USART) RM0390 When a transmission is taking place, a write instruction to the USART_DR register stores the data in the TDR register and which is copied in the shift register at the end of the current transmission.
Page 803: Receiver
RM0390 Universal synchronous asynchronous receiver transmitter (USART) 25.4.3 Receiver The USART can receive data words of either 8 or 9 bits depending on the M bit in the USART_CR1 register. Start bit detection The start bit detection sequence is the same when oversampling by 16 or by 8. In the USART, the start bit is detected when a specific sequence of samples is recognized.
Page 804 Universal synchronous asynchronous receiver transmitter (USART) RM0390 Procedure: Enable the USART by writing the UE bit in USART_CR1 register to 1. Program the M bit in USART_CR1 to define the word length. Program the number of stop bits in USART_CR2. Select DMA enable (DMAR) in USART_CR3 if multibuffer communication is to take place.
Page 805 RM0390 Universal synchronous asynchronous receiver transmitter (USART) The RXNE flag is set after every byte received. An overrun error occurs if RXNE flag is set when the next data is received or the previous DMA request has not been serviced. When an overrun error occurs: •...
Page 806: Figure 284. Data Sampling When Oversampling By 16
Universal synchronous asynchronous receiver transmitter (USART) RM0390 Programming the ONEBIT bit in the USART_CR3 register selects the method used to evaluate the logic level. There are two options: • the majority vote of the three samples in the center of the received bit. In this case, when the 3 samples used for the majority vote are not equal, the NF bit is set •...
Page 807: Table 146. Noise Detection From Sampled Data
RM0390 Universal synchronous asynchronous receiver transmitter (USART) Figure 285. Data sampling when oversampling by 8 Table 146. Noise detection from sampled data Sampled value NE status Received bit value Framing error A framing error is detected when: The stop bit is not recognized on reception at the expected time, following either a de- synchronization or excessive noise.
Page 808: Fractional Baud Rate Generation
Universal synchronous asynchronous receiver transmitter (USART) RM0390 0.5 stop bit (reception in Smartcard mode): No sampling is done for 0.5 stop bit. As a consequence, no framing error and no break frame can be detected when 0.5 stop bit is selected. 1 stop bit: Sampling for 1 stop Bit is done on the 8 and 10 samples.
Page 809 RM0390 Universal synchronous asynchronous receiver transmitter (USART) Fraction (USARTDIV) = 12/16 = 0d0.75 Therefore USARTDIV = 0d27.75 Example 2: To program USARTDIV = 0d25.62 This leads to: DIV_Fraction = 16*0d0.62 = 0d9.92 The nearest real number is 0d10 = 0xA DIV_Mantissa = mantissa (0d25.620) = 0d25 = 0x19 Then, USART_BRR = 0x19A hence USARTDIV = 0d25.625 Example 3:...
Page 810: Table 147. Error Calculation For Programmed Baud Rates At F
Universal synchronous asynchronous receiver transmitter (USART) RM0390 The nearest real number is 0d8 = 0x8 => overflow of the DIV_frac[2:0] => carry must be added up to the mantissa DIV_Mantissa = mantissa (0d50.990 + carry) = 0d51 = 0x33 Then, USART_BRR = 0x0330 => USARTDIV = 0d51.000 Table 147.
Page 811 RM0390 Universal synchronous asynchronous receiver transmitter (USART) Table 148. Error calculation for programmed baud rates at f = 8 MHz or f = 12 MHz, PCLK PCLK oversampling by 8 (continued) Oversampling by 8 (OVER8 = 1) Baud rate = 8 MHz = 12 MHz PCLK PCLK...
Page 812 Universal synchronous asynchronous receiver transmitter (USART) RM0390 Table 150. Error calculation for programmed baud rates at f = 16 MHz or f = 24 MHz, PCLK PCLK oversampling by 8 Oversampling by 8 (OVER8=1) Baud rate = 16 MHz = 24 MHz PCLK PCLK Value...
Page 813 RM0390 Universal synchronous asynchronous receiver transmitter (USART) Table 151. Error calculation for programmed baud rates at f = 8 MHz or f = 16 MHz, PCLK PCLK oversampling by 16 (continued) Oversampling by 16 (OVER8=0) Baud rate = 8 MHz = 16 MHz PCLK PCLK...
Page 814 Universal synchronous asynchronous receiver transmitter (USART) RM0390 Table 153. Error calculation for programmed baud rates at f = 30 MHz or f = 60 MHz, PCLK PCLK (1)(2) oversampling by 16 Oversampling by 16 (OVER8=0) Baud rate = 30 MHz = 60 MHz PCLK PCLK...
Page 815 RM0390 Universal synchronous asynchronous receiver transmitter (USART) Table 154. Error calculation for programmed baud rates at f = 30 MHz or f = 60 MHz, PCLK PCLK (1) (2) oversampling by 8 (continued) Oversampling by 8 (OVER8=1) Baud rate = 30 MHz =60 MHz PCLK PCLK...
Page 816 Universal synchronous asynchronous receiver transmitter (USART) RM0390 Table 155. Error calculation for programmed baud rates at f = 42 MHz or f = 84 Hz, PCLK PCLK (1)(2) oversampling by 16 (continued) Oversampling by 16 (OVER8=0) Baud rate = 42 MHz = 84 MHz PCLK PCLK...
Page 817: Usart Receiver Tolerance To Clock Deviation
RM0390 Universal synchronous asynchronous receiver transmitter (USART) Table 156. Error calculation for programmed baud rates at f = 42 MHz or f = 84 MHz, PCLK PCLK (1)(2) oversampling by 8 (continued) Oversampling by 8 (OVER8=1) Baud rate = 42 MHz = 84 MHz PCLK PCLK...
Page 818: Multiprocessor Communication
Universal synchronous asynchronous receiver transmitter (USART) RM0390 Table 158. USART receiver tolerance when DIV_Fraction is different from 0 OVER8 bit = 0 OVER8 bit = 1 M bit ONEBIT=0 ONEBIT=1 ONEBIT=0 ONEBIT=1 3.33% 3.88% 3.03% 3.53% 1.82% 2.73% Note: The figures specified in Table 157 Table 158 may slightly differ in the special case when...
Page 819: Figure 286. Mute Mode Using Idle Line Detection
RM0390 Universal synchronous asynchronous receiver transmitter (USART) Figure 286. Mute mode using Idle line detection Address mark detection (WAKE=1) In this mode, bytes are recognized as addresses if their MSB is a ‘1 else they are considered as data. In an address byte, the address of the targeted receiver is put on the 4 LSB.
Page 820: Parity Control
Universal synchronous asynchronous receiver transmitter (USART) RM0390 25.4.7 Parity control Parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the PCE bit in the USART_CR1 register. Depending on the frame length defined by the M bit, the possible USART frame formats are as listed in Table 159.
Page 821: Lin (Local Interconnection Network) Mode
RM0390 Universal synchronous asynchronous receiver transmitter (USART) 25.4.8 LIN (local interconnection network) mode The LIN mode is selected by setting the LINEN bit in the USART_CR2 register. In LIN mode, the following bits must be kept cleared: • STOP[1:0] and CLKEN in the USART_CR2 register •...
Page 822: Figure 288. Break Detection In Lin Mode (11-Bit Break Length - Lbdl Bit Is Set)
Universal synchronous asynchronous receiver transmitter (USART) RM0390 Figure 288. Break detection in LIN mode (11-bit break length - LBDL bit is set) 822/1328 RM0390 Rev 4...
Page 823: Usart Synchronous Mode
RM0390 Universal synchronous asynchronous receiver transmitter (USART) Figure 289. Break detection in LIN mode vs. Framing error detection 25.4.9 USART synchronous mode The synchronous mode is selected by writing the CLKEN bit in the USART_CR2 register to 1. In synchronous mode, the following bits must be kept cleared: •...
Page 824: Figure 290. Usart Example Of Synchronous Transmission
Universal synchronous asynchronous receiver transmitter (USART) RM0390 has been written). This means that it is not possible to receive a synchronous data without transmitting data. The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly.
Page 825: Single-Wire Half-Duplex Communication
RM0390 Universal synchronous asynchronous receiver transmitter (USART) Figure 292. USART data clock timing diagram (M=1) Figure 293. RX data setup/hold time Note: The function of SCLK is different in Smartcard mode. Refer to the Smartcard mode chapter for more details. 25.4.10 Single-wire half-duplex communication The single-wire half-duplex mode is selected by setting the HDSEL bit in the USART_CR3...
Page 826: Smartcard
Universal synchronous asynchronous receiver transmitter (USART) RM0390 As soon as HDSEL is written to 1: • the TX and RX lines are internally connected • the RX pin is no longer used • the TX pin is always released when no data is transmitted. Thus, it acts as a standard I/O in idle or in reception.
Page 827: Figure 295. Parity Error Detection Using The 1.5 Stop Bits
RM0390 Universal synchronous asynchronous receiver transmitter (USART) shifting on the next baud clock edge. In Smartcard mode this transmission is further delayed by a guaranteed 1/2 baud clock. • If a parity error is detected during reception of a frame programmed with a 0.5 or 1.5 stop bit period, the transmit line is pulled low for a baud clock period after the completion of the receive frame.
Page 828: Irda Sir Endec Block
Universal synchronous asynchronous receiver transmitter (USART) RM0390 prescaler register USART_GTPR. SCLK frequency can be programmed from f /2 to /62, where f is the peripheral input clock. 25.4.12 IrDA SIR ENDEC block The IrDA mode is selected by setting the IREN bit in the USART_CR3 register. In IrDA mode, the following bits must be kept cleared: •...
Page 829: Figure 296. Irda Sir Endec- Block Diagram
RM0390 Universal synchronous asynchronous receiver transmitter (USART) IrDA low-power mode Transmitter: In low-power mode the pulse width is not maintained at 3/16 of the bit period. Instead, the width of the pulse is 3 times the low-power baud rate that can be a minimum of 1.42 MHz. Generally this value is 1.8432 MHz (1.42 MHz <...
Page 830: Continuous Communication Using Dma
Universal synchronous asynchronous receiver transmitter (USART) RM0390 25.4.13 Continuous communication using DMA The USART is capable of continuous communication using the DMA. The DMA requests for Rx buffer and Tx buffer are generated independently. Transmission using DMA DMA mode can be enabled for transmission by setting DMAT bit in the USART_CR3 register.
Page 831: Figure 298. Transmission Using Dma
RM0390 Universal synchronous asynchronous receiver transmitter (USART) Figure 298. Transmission using DMA Reception using DMA DMA mode can be enabled for reception by setting the DMAR bit in USART_CR3 register. Data is loaded from the USART_DR register to a SRAM area configured using the DMA peripheral (refer to the DMA specification) whenever a data byte is received.
Page 832: Hardware Flow Control
Universal synchronous asynchronous receiver transmitter (USART) RM0390 Figure 299. Reception using DMA Error flagging and interrupt generation in multibuffer communication In case of multibuffer communication if any error occurs during the transaction the error flag will be asserted after the current byte. An interrupt will be generated if the interrupt enable flag is set.
Page 833: Figure 301. Rts Flow Control
RM0390 Universal synchronous asynchronous receiver transmitter (USART) RTS flow control If the RTS flow control is enabled (RTSE=1), then nRTS is asserted (tied low) as long as the USART receiver is ready to receive a new data. When the receive register is full, nRTS is deasserted, indicating that the transmission is expected to stop at the end of the current frame.
Page 834: Usart Interrupts
Universal synchronous asynchronous receiver transmitter (USART) RM0390 Note: Special behavior of break frames: when the CTS flow is enabled, the transmitter does not check the nCTS input state to send a break. 25.5 USART interrupts Table 160. USART interrupt requests Interrupt event Event flag Enable control bit...
Page 835: Usart Registers
RM0390 Universal synchronous asynchronous receiver transmitter (USART) Figure 303. USART interrupt mapping diagram 25.6 USART registers Refer to for a list of abbreviations used in register descriptions. Section 1.1 on page 51 The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits). 25.6.1 Status register (USART_SR) Address offset: 0x00...
Page 836 Universal synchronous asynchronous receiver transmitter (USART) RM0390 Bits 31:10 Reserved, must be kept at reset value Bit 9 CTS: CTS flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software (by writing it to 0).
Page 837 RM0390 Universal synchronous asynchronous receiver transmitter (USART) Bit 3 ORE: Overrun error This bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the RDR register while RXNE=1. An interrupt is generated if RXNEIE=1 in the USART_CR1 register.
Page 838: Data Register (Usart_Dr)
Universal synchronous asynchronous receiver transmitter (USART) RM0390 25.6.2 Data register (USART_DR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 839: Control Register 1 (Usart_Cr1)
RM0390 Universal synchronous asynchronous receiver transmitter (USART) 25.6.4 Control register 1 (USART_CR1) Address offset: 0x0C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OVER8 Res. WAKE PEIE TXEIE TCIE RXNEIE IDLEIE Bits 31:16 Reserved, must be kept at reset value...
Page 840 Universal synchronous asynchronous receiver transmitter (USART) RM0390 Bit 8 PEIE: PE interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An USART interrupt is generated whenever PE=1 in the USART_SR register Bit 7 TXEIE: TXE interrupt enable This bit is set and cleared by software.
Page 841: Control Register 2 (Usart_Cr2)
RM0390 Universal synchronous asynchronous receiver transmitter (USART) 25.6.5 Control register 2 (USART_CR2) Address offset: 0x10 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LINEN STOP[1:0] CLKEN CPOL CPHA LBCL Res.
Page 842: Control Register 3 (Usart_Cr3)
Universal synchronous asynchronous receiver transmitter (USART) RM0390 Bit 8 LBCL: Last bit clock pulse This bit allows the user to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. 0: The clock pulse of the last data bit is not output to the SCLK pin 1: The clock pulse of the last data bit is output to the SCLK pin Note: 1: The last bit is the 8th or 9th data bit transmitted depending on the 8 or 9 bit format selected...
Page 843 RM0390 Universal synchronous asynchronous receiver transmitter (USART) Bit 9 CTSE: CTS enable 0: CTS hardware flow control disabled 1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while a data is being transmitted, then the transmission is completed before stopping.
Page 844: Guard Time And Prescaler Register (Usart_Gtpr)
Universal synchronous asynchronous receiver transmitter (USART) RM0390 Bit 0 EIE: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USART_SR register) in case of Multi Buffer Communication (DMAR=1 in the USART_CR3 register).
Page 845: Usart Register Map
RM0390 Universal synchronous asynchronous receiver transmitter (USART) 25.6.8 USART register map The table below gives the USART register map and reset values. Table 161. USART register map and reset values Offset Register USART_SR 0x00 Reset value USART_DR DR[8:0] 0x04 Reset value DIV_Fraction USART_BRR DIV_Mantissa[15:4]...
Page 846: Serial Peripheral Interface/ Inter-Ic Sound (Spi/I2S)
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0390 Serial peripheral interface/ inter-IC sound (SPI/I2S) 26.1 Introduction The SPI/I²S interface can be used to communicate with external devices using the SPI protocol or the I S audio protocol. SPI or I S mode is selectable by software. SPI mode is selected by default after a device reset.
Page 847: Spi Extended Features
RM0390 Serial peripheral interface/ inter-IC sound (SPI/I2S) 26.1.2 SPI extended features • SPI TI mode support 26.1.3 I2S features • Half-duplex communication (only transmitter or receiver) • Master or slave operations • 8-bit programmable linear prescaler to reach accurate audio sample frequencies (from 8 kHz to 192 kHz) •...
Page 848: Spi Functional Description
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0390 26.3 SPI functional description 26.3.1 General description The SPI allows synchronous, serial communication between the MCU and external devices. Application software can manage the communication by polling the status flag or using dedicated SPI interrupt. The main elements of SPI and their interactions are shown in the following block diagram Figure 304.
Page 849: Communications Between One Master And One Slave
RM0390 Serial peripheral interface/ inter-IC sound (SPI/I2S) 26.3.2 Communications between one master and one slave The SPI allows the MCU to communicate using different configurations, depending on the device targeted and the application requirements. These configurations use 2 or 3 wires (with software NSS management) or 3 or 4 wires (with hardware NSS management).
Page 850: Figure 306. Half-Duplex Single Master/ Single Slave Application
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0390 Figure 306. Half-duplex single master/ single slave application 1. The NSS pins can be used to provide a hardware control flow between master and slave. Optionally, the pins can be left unused by the peripheral. Then the flow has to be handled internally for both master and slave.
Page 851: Figure 307. Simplex Single Master/Single Slave Application
RM0390 Serial peripheral interface/ inter-IC sound (SPI/I2S) Figure 307. Simplex single master/single slave application (master in transmit-only/ slave in receive-only mode) 1. The NSS pins can be used to provide a hardware control flow between master and slave. Optionally, the pins can be left unused by the peripheral.
Page 852: Standard Multi-Slave Communication
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0390 26.3.3 Standard multi-slave communication In a configuration with two or more independent slaves, the master uses GPIO pins to manage the chip select lines for each slave (see Figure 308.). The master must select one of the slaves individually by pulling low the GPIO connected to the slave NSS input.
Page 853: Multi-Master Communication
RM0390 Serial peripheral interface/ inter-IC sound (SPI/I2S) 26.3.4 Multi-master communication Unless SPI bus is not designed for a multi-master capability primarily, the user can use build in feature which detects a potential conflict between two nodes trying to master the bus at the same time.
Page 854: Figure 310. Hardware/Software Slave Select Management
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0390 – NSS output enable (SSM=0,SSOE = 1): this configuration is only used when the MCU is set as master. The NSS pin is managed by the hardware. The NSS signal is driven low as soon as the SPI is enabled in master mode (SPE=1), and is kept low until the SPI is disabled (SPE =0).
Page 855: Communication Formats
RM0390 Serial peripheral interface/ inter-IC sound (SPI/I2S) 26.3.6 Communication formats During SPI communication, receive and transmit operations are performed simultaneously. The serial clock (SCK) synchronizes the shifting and sampling of the information on the data lines. The communication format depends on the clock phase, the clock polarity and the data frame format.
Page 856: Figure 311. Data Clock Timing Diagram
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0390 Figure 311. Data clock timing diagram Note: The order of data bits depends on LSBFIRST bit setting. Data frame format The SPI shift register can be set up to shift out MSB-first or LSB-first, depending on the value of the LSBFIRST bit.
Page 857: Spi Configuration
RM0390 Serial peripheral interface/ inter-IC sound (SPI/I2S) 26.3.7 SPI configuration The configuration procedure is almost the same for master and slave. For specific mode setups, follow the dedicated chapters. When a standard communication is to be initialized, perform these steps: Write proper GPIO registers: Configure GPIO for MOSI, MISO and SCK pins.
Page 858: Data Transmission And Reception Procedures
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0390 26.3.9 Data transmission and reception procedures Rx and Tx buffers In reception, data are received and then stored into an internal Rx buffer while in transmission, data are first stored into an internal Tx buffer before being transmitted. A read access to the SPI_DR register returns the Rx buffered value whereas a write access to the SPI_DR stores the written data into the Tx buffer.
Page 859: Figure 312. Txe/Rxne/Bsy Behavior In Master / Full-Duplex Mode (Bidimode=0, Rxonly=0) In The Case Of Continuous Transfers
RM0390 Serial peripheral interface/ inter-IC sound (SPI/I2S) underflow error signal for slave operating in SPI mode, and that data from the slave are always transacted and processed by the master even if the slave cannot not prepare them correctly in time. It is preferable for the slave to use DMA, especially when data frames are shorter and bus rate is high.
Page 860: Procedure For Disabling The Spi
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0390 Figure 313. TXE/RXNE/BSY behavior in slave / full-duplex mode (BIDIMODE=0, RXONLY=0) in the case of continuous transfers 26.3.10 Procedure for disabling the SPI When SPI is disabled, it is mandatory to follow the disable procedures described in this paragraph.
Page 861: Communication Using Dma (Direct Memory Addressing)
RM0390 Serial peripheral interface/ inter-IC sound (SPI/I2S) Note: During discontinuous communications, there is a 2 APB clock period delay between the write operation to the SPI_DR register and BSY bit setting. As a consequence it is mandatory to wait first until TXE is set and then until BSY is cleared after writing the last data.
Page 862: Figure 314. Transmission Using Dma
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0390 To close communication it is mandatory to follow these steps in order: Disable DMA streams for Tx and Rx in the DMA registers, if the streams are used. Disable the SPI by following the SPI disable procedure. Disable DMA Tx and Rx buffers by clearing the TXDMAEN and RXDMAEN bits in the SPI_CR2 register, if DMA Tx and/or DMA Rx are used.
Page 863: Spi Status Flags
RM0390 Serial peripheral interface/ inter-IC sound (SPI/I2S) Figure 315. Reception using DMA 26.3.12 SPI status flags Three status flags are provided for the application to completely monitor the state of the SPI bus. Tx buffer empty flag (TXE) When it is set, the TXE flag indicates that the Tx buffer is empty and that the next data to be transmitted can be loaded into the buffer.
Page 864: Spi Error Flags
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0390 The BSY flag is cleared under any one of the following conditions: • When the SPI is correctly disabled • When a fault is detected in Master mode (MODF bit set to 1) •...
Page 865: Spi Special Features
RM0390 Serial peripheral interface/ inter-IC sound (SPI/I2S) CRC error (CRCERR) This flag is used to verify the validity of the value received when the CRCEN bit in the SPIx_CR1 register is set. The CRCERR flag in the SPIx_SR register is set if the value received in the shift register does not match the receiver SPIx_RXCRC value.
Page 866: Crc Calculation
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0390 Note: To detect TI frame errors in slave transmitter only mode by using the Error interrupt (ERRIE=1), the SPI must be configured in 2-line unidirectional mode by setting BIDIMODE and BIDIOE to 1 in the SPI_CR1 register. When BIDIMODE is set to 0, OVR is set to 1 because the data register is never read and error interrupts are always generated, while when BIDIMODE is set to 1, data are not received and OVR is never set.
Page 867 RM0390 Serial peripheral interface/ inter-IC sound (SPI/I2S) The received CRC is stored in the Rx buffer like any other data frame. A CRC-format transaction takes one more data frame to communicate at the end of data sequence. When the last CRC data is received, an automatic check is performed comparing the received value and the value in the SPIx_RXCRC register.
Page 868: Spi Interrupts
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0390 has to be reset between sessions by the SPI disable sequence by re-enabling the CRCEN bit described above at both master and slave sides, else the CRC calculation can be corrupted at this specific mode. 26.5 SPI interrupts During SPI communication an interrupts can be generated by the following events:...
Page 869: I 2 S Functional Description
RM0390 Serial peripheral interface/ inter-IC sound (SPI/I2S) 26.6 S functional description 26.6.1 S general description The block diagram of the I S is shown in Figure 317. Figure 317. I S block diagram 1. MCK is mapped on the MISO pin. The SPI can function as an audio I S interface when the I S capability is enabled (by setting...
Page 870: I2S Full-Duplex
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0390 The I S shares three common pins with the SPI: • SD: Serial Data (mapped on the MOSI pin) to transmit or receive the two time- multiplexed data channels (in half-duplex mode only). •...
Page 871: Supported Audio Protocols
RM0390 Serial peripheral interface/ inter-IC sound (SPI/I2S) Figure 318. Full-duplex communication 26.6.3 Supported audio protocols The three-line bus has to handle only audio data generally time-multiplexed on two channels: the right channel and the left channel. However there is only one 16-bit register for transmission or reception.
Page 872: Figure 319. I 2 S Philips Protocol Waveforms (16/32-Bit Full Accuracy, Cpol = 0)
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0390 The I S interface supports four audio standards, configurable using the I2SSTD[1:0] and PCMSYNC bits in the SPIx_I2SCFGR register. S Philips standard For this standard, the WS signal is used to indicate which channel is being transmitted. It is activated one CK clock cycle before the first bit (MSB) is available.
Page 873: Figure 321. Transmitting 0X8Eaa33
RM0390 Serial peripheral interface/ inter-IC sound (SPI/I2S) • In transmission mode: If 0x8EAA33 has to be sent (24-bit): Figure 321. Transmitting 0x8EAA33 • In reception mode: If data 0x8EAA33 is received: Figure 322. Receiving 0x8EAA33 Figure 323. I S Philips standard (16-bit extended to 32-bit packet frame with CPOL = 0) When 16-bit data frame extended to 32-bit channel frame is selected during the I configuration phase, only one access to the SPIx_DR register is required.
Page 874: Figure 324. Example Of 16-Bit Data Frame Extended To 32-Bit Channel Frame
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0390 Figure 324. Example of 16-bit data frame extended to 32-bit channel frame For transmission, each time an MSB is written to SPIx_DR, the TXE flag is set and its interrupt, if allowed, is generated to load the SPIx_DR register with the new value to send. This takes place even if 0x0000 have not yet been sent because it is done by hardware.
Page 875: Figure 327. Msb Justified 16-Bit Extended To 32-Bit Packet Frame With Cpol = 0
RM0390 Serial peripheral interface/ inter-IC sound (SPI/I2S) Figure 327. MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 LSB justified standard This standard is similar to the MSB justified standard (no difference for the 16-bit and 32-bit full-accuracy frame formats).
Page 876: Figure 330. Operations Required To Transmit 0X3478Ae
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0390 • In transmission mode: If data 0x3478AE have to be transmitted, two write operations to the SPIx_DR register are required by software or by DMA. The operations are shown below. Figure 330. Operations required to transmit 0x3478AE •...
Page 877: Figure 333. Example Of 16-Bit Data Frame Extended To 32-Bit Channel Frame
RM0390 Serial peripheral interface/ inter-IC sound (SPI/I2S) Figure 333. Example of 16-bit data frame extended to 32-bit channel frame In transmission mode, when a TXE event occurs, the application has to write the data to be transmitted (in this case 0x76A3). The 0x000 field is transmitted first (extension on 32-bit). The TXE flag is set again as soon as the effective data (0x76A3) is sent on SD.
Page 878: Clock Generator
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0390 Note: For both modes (master and slave) and for both synchronizations (short and long), the number of bits between two consecutive pieces of data (and so two synchronization signals) needs to be specified (DATLEN and CHLEN bits in the SPIx_I2SCFGR register) even in slave mode.
Page 879: Table 164. Audio-Frequency Precision Using Standard 8 Mhz Hse
RM0390 Serial peripheral interface/ inter-IC sound (SPI/I2S) The audio sampling frequency may be 192 KHz, 96 kHz, 48 kHz, 44.1 kHz, 32 kHz, 22.05 kHz, 16 kHz, 11.025 kHz or 8 kHz (or any other value within this range). In order to reach the desired frequency, the linear divider needs to be programmed according to the formulas below: When the master clock is generated (MCKOE in the SPIx_I2SPR register is set):...
Page 880: I 2 S Master Mode
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0390 Table 164. Audio-frequency precision using standard 8 MHz HSE (continued) SYSCLK Data Target f I2SDIV I2SODD MCLK Real f (KHz) Error length (Hz) (MHz) 22050 20833.333 5.5178% 16000 15625 2.3438% 16000 15625 2.3438% 11025 11029.4118 0.0400%...
Page 881 RM0390 Serial peripheral interface/ inter-IC sound (SPI/I2S) indicates which channel is to be transmitted. It has a meaning when the TXE flag is set because the CHSIDE flag is updated when TXE goes high. A full frame has to be considered as a left channel data transmission followed by a right channel data transmission.
Page 882: I 2 S Slave Mode
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0390 Then wait 1 I S clock cycle (using a software loop) Disable the I S (I2SE = 0) • For all other combinations of DATLEN and CHLEN, whatever the audio mode selected through the I2SSTD bits, carry out the following sequence to switch off the I Wait for the second to last RXNE = 1 (n –...
Page 883: I 2 S Status Flags
RM0390 Serial peripheral interface/ inter-IC sound (SPI/I2S) Note that the TXE flag should be checked to be at 1 before attempting to write the Tx buffer. For more details about the write operations depending on the I S Standard-mode selected, refer to Section 26.6.3: Supported audio protocols.
Page 884: I 2 S Error Flags
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0390 The BSY flag is useful to detect the end of a transfer if the software needs to disable the I This avoids corrupting the last transfer. For this, the procedure described below must be strictly respected.
Page 885: I 2 S Interrupts
RM0390 Serial peripheral interface/ inter-IC sound (SPI/I2S) ERRIE bit in the SPIx_CR2 register is set. The UDR bit is cleared by a read operation on the SPIx_SR register. Overrun flag (OVR) This flag is set when data are received and the previous data have not yet been read from the SPIx_DR register.
Page 886: Spi And I 2 S Registers
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0390 26.7 SPI and I S registers The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). SPI_DR in addition by can be accessed by 8-bit access. Refer to Section 1.1 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16 bits) or words (32 bits).
Page 887 RM0390 Serial peripheral interface/ inter-IC sound (SPI/I2S) Bit 11 DFF: Data frame format 0: 8-bit data frame format is selected for transmission/reception 1: 16-bit data frame format is selected for transmission/reception Note: This bit should be written only when SPI is disabled (SPE = ‘0’) for correct operation. It is not used in I S mode.
Page 888: Spi Control Register 2 (Spi_Cr2)
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0390 Bit 2 MSTR: Master selection 0: Slave configuration 1: Master configuration Note: This bit should not be changed when communication is ongoing. It is not used in I S mode. Bit1 CPOL: Clock polarity 0: CK to 0 when idle 1: CK to 1 when idle Note: This bit should not be changed when communication is ongoing.
Page 889: Spi Status Register (Spi_Sr)
RM0390 Serial peripheral interface/ inter-IC sound (SPI/I2S) Bit 2 SSOE: SS output enable 0: SS output is disabled in master mode and the cell can work in multimaster configuration 1: SS output is enabled in master mode and when the cell is enabled. The cell cannot work in a multimaster environment.
Page 890 Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0390 Bit 5 MODF: Mode fault 0: No mode fault occurred 1: Mode fault occurred This flag is set by hardware and reset by a software sequence. Refer to Section 26.4 on page 865 for the software sequence.
Page 891: Spi Data Register (Spi_Dr)
RM0390 Serial peripheral interface/ inter-IC sound (SPI/I2S) 26.7.4 SPI data register (SPI_DR) Address offset: 0x0C Reset value: 0x0000 DR[15:0] Bits 15:0 DR[15:0]: Data register Data received or to be transmitted. The data register is split into 2 buffers - one for writing (Transmit Buffer) and another one for reading (Receive buffer).
Page 892: Spi Rx Crc Register (Spi_Rxcrcr) (Not Used In I 2 S Mode)
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0390 26.7.6 SPI RX CRC register (SPI_RXCRCR) (not used in I S mode) Address offset: 0x14 Reset value: 0x0000 RXCRC[15:0] Bits 15:0 RXCRC[15:0]: Rx CRC register When CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of the subsequently received bytes.
Page 893: Spi_I 2 S Configuration Register (Spi_I2Scfgr)
RM0390 Serial peripheral interface/ inter-IC sound (SPI/I2S) 26.7.8 SPI_I S configuration register (SPI_I2SCFGR) Address offset: 0x1C Reset value: 0x0000 ASTRE PCMSY Res. Res. Res. I2SMOD I2SE I2SCFG Res. I2SSTD CKPOL DATLEN CHLEN Bits 15:13 Reserved, must be kept at reset value. Bit 12 ASTREN: Asynchronous start enable.
Page 894: Spi_I 2 S Prescaler Register (Spi_I2Spr)
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0390 Bits 5:4 I2SSTD: I2S standard selection 00: I S Philips standard. 01: MSB justified standard (left justified) 10: LSB justified standard (right justified) 11: PCM standard For more details on I S standards, refer to Section 26.6.3 on page 871.
Page 895 RM0390 Serial peripheral interface/ inter-IC sound (SPI/I2S) Bit 9 MCKOE: Master clock output enable 0: Master clock output is disabled 1: Master clock output is enabled Note: This bit should be configured when the I S is disabled. It is used only when the I S is in master mode.
Page 896: Spi Register Map
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0390 26.7.10 SPI register map The table provides shows the SPI register map and reset values. Table 166. SPI register map and reset values Offset Register SPI_CR1 [2:0] 0x00 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI_CR2 0x04 Reset value...
Page 897: Spdif Receiver Interface (Spdifrx)
RM0390 SPDIF receiver interface (SPDIFRX) SPDIF receiver interface (SPDIFRX) 27.1 SPDIFRX interface introduction The SPDIFRX interface handles S/PDIF audio protocol. 27.2 SPDIFRX main features • Up to 4 inputs available • Automatic symbol rate detection • Maximum symbol rate: 12.288 MHz •...
Page 898: S/Pdif Protocol (Iec-60958)
SPDIF receiver interface (SPDIFRX) RM0390 Figure 338. SPDIFRX block diagram 1. ‘n’ is fixed to 4. 27.3.1 S/PDIF protocol (IEC-60958) S/PDIF block A S/PDIF frame is composed of two sub-frames (see Figure 340). Each sub-frame contains 32 bits (or time slots): •...
Page 899: Figure 340. S/Pdif Block Format
RM0390 SPDIF receiver interface (SPDIFRX) For linear coded audio applications, the first sub-frame (left or “A” channel in stereophonic operation and primary channel in monophonic operation) normally starts with preamble “M”. However, the preamble changes to preamble “B” once every 192 frames to identify the start of the block structure used to organize the channel status and user information.
Page 900: Spdifrx Decoder (Spdifrx_Dc)
SPDIF receiver interface (SPDIFRX) RM0390 Coding of information bits In order to minimize the DC component value on the transmission line, and to facilitate clock recovery from the data stream, bits 4 to 31 are encoded in biphase-mark. Each bit to be transmitted is represented by a symbol comprising two consecutive binary states.
Page 901: Figure 343. Spdifrx Decoder
RM0390 SPDIF receiver interface (SPDIFRX) Figure 343 gives a detailed view of the SPDIFRX decoder. Figure 343. SPDIFRX decoder Noise filtering & rising/falling edge detection The S/PDIF signal received on the selected SPDIFRX_IN is re-sampled using the SPDIFRX_CLK clock (acquisition clock). A simple filtering is applied in order cancel spurs. This is performed by the stage detecting the edge transitions.
Page 902 SPDIF receiver interface (SPDIFRX) RM0390 The search of the longest and shortest transition is stopped when the transition timer expires. The transition timer is like a watchdog timer that generates a trigger after 70 transitions of the incoming signal. Note that counting 70 transitions insures a delay a bit longer than a sub-frame.
Page 903: Table 167. Transition Sequence For Preamble
RM0390 SPDIF receiver interface (SPDIFRX) Figure 345. Thresholds The preamble detector checks four consecutive transitions of a specific sequence to determine if they form the part of preamble. Let us say TRANS0, TRANS1, TRANS2 and TRANS3 represent four consecutive transitions encoded as mentioned above. Table 167 shows the values of these four transitions to form a preamble.
Page 904: Spdifrx Tolerance To Clock Deviation
SPDIF receiver interface (SPDIFRX) RM0390 27.3.3 SPDIFRX tolerance to clock deviation The SPDIFRX tolerance to clock deviation depends on the number of sample clock cycles in one bit slot. The fastest SPDIFRX_CLK is, the more robust the reception will be. The ratio between SPDIFRX_CLK frequency and the symbol rate must be at least 11.
Page 905: Figure 346. Synchronization Flowchart
RM0390 SPDIF receiver interface (SPDIFRX) Figure 346. Synchronization flowchart Refer to Frame structure and synchronization error for additional information concerning TRCNT overflow. The FINE SYNC process is re-triggered every frame in order to update thresholds as shown Figure 347 in order to continuously track S/PDIF synchronization. RM0390 Rev 4 905/1328...
Page 906: Spdifrx Handling
SPDIF receiver interface (SPDIFRX) RM0390 Figure 347. Synchronization process scheduling 27.3.5 SPDIFRX handling The software can control the state of the SPDIFRX through SPDIFRXEN field. The SPDIFRX can be into one of the following states: • STATE_IDLE: The peripheral is disabled, the SPDIFRX_CLK domain is reset. The PCLK1 domain is functional.
Page 907: Figure 348. Spdifrx States
RM0390 SPDIF receiver interface (SPDIFRX) Figure 348. SPDIFRX States When SPDIFRX is in STATE_IDLE: • The software can transition to STATE_SYNC by setting SPDIFRXEN to 0b01 or 0b11 When SPDIFRX is in STATE_SYNC: • If the synchronization fails or if the received data are not properly decoded with no chance of recovery without a re-synchronization (FERR or SERR or TERR = 1), the SPDIFRX goes to STATE_STOP, and waits for software acknowledge.
Page 908: Data Reception Management
SPDIF receiver interface (SPDIFRX) RM0390 When SPDIFRXEN is set to 0, the IP is disabled, meaning that all the state machines are reset, and RX_BUF is flushed. Note as well that flags FERR, SERR and TERR are reset. 27.3.6 Data reception management The SPDIFRX offers a double buffer for the audio sample reception.
Page 909: Figure 349. Spdifrx_Dr Register Format
RM0390 SPDIF receiver interface (SPDIFRX) Figure 349. SPDIFRX_DR register format Setting DRFMT to 0b00 or 0b01, offers the possibility to have the data either right or left aligned into the SPDIFRX_DR register. The status information can be enabled or forced to zero according to the way the software wants to handle them.
Page 910: Dedicated Control Flow
SPDIF receiver interface (SPDIFRX) RM0390 27.3.7 Dedicated control flow The SPDIFRX offers the possibility to catch both user data and channel status information via a dedicated DMA channel. This feature allows the SPDIFRX to acquire continuously the channel status and user information. The acquisition will start at the beginning of a IEC 60958 block.
Page 911 RM0390 SPDIF receiver interface (SPDIFRX) The overflow occurs when no transition is detected during 8192 periods of SPDIFRX_CLK clock. It represents at most a time interval of 11.6 frames. When one of those flags goes to 1, the traffic on selected SPDIFRX_IN is then ignored, an interrupt is generated if the IFEIE bit of the SPDIFRX_CR register is set.
Page 912: Figure 351. S/Pdif Overrun Error When Rxsteo = 0
SPDIF receiver interface (SPDIFRX) RM0390 Figure 351. S/PDIF overrun error when RXSTEO = 0 If the RXSTEO bit is set to 1, it means that stereo data are transported, then the SPDIFRX has to avoid misalignment between left and right channels. So the peripheral has to drop a second sample even if there is room inside the RX_BUF in order to avoid misalignment.
Page 913: Clocking Strategy
RM0390 SPDIF receiver interface (SPDIFRX) Figure 352. S/PDIF overrun error when RXSTEO = 1 27.3.9 Clocking strategy The SPDIFRX block needs two different clocks: • The APB1 clock (PCLK1), which is used for the register interface, • The SPDIFRX_CLK which is mainly used by the SPDIFRX_DC part. Those clocks are not supposed to be phase locked, so all signals crossing those clock domains are re- synchronized (SYNC block on Figure...
Page 914: Interrupt Generation
SPDIF receiver interface (SPDIFRX) RM0390 SPDIFRX interface sends a transfer request to the DMA. The DMA reads the data received through the SPDIFRX_DR register without CPU intervention. For the use of DMA for the control data refer to Section 27.3.7: Dedicated control flow.
Page 915: Register Protection
RM0390 SPDIF receiver interface (SPDIFRX) The SBD flag behavior is not guaranteed when the sub-frame which contains the B preamble is lost due to an overrun. 27.3.12 Register protection The SPDIFRX block embeds some hardware protection avoid erroneous use of control registers.
Page 916: Initialization Phase
SPDIF receiver interface (SPDIFRX) RM0390 A simple way to check if valid data are available into the SPDIFRX_IN line is to switch the SPDIFRX into the STATE_SYNC, with bit WFA set to 1. The description hereafter will focus on detection. It is also possible to implement this function as follow: •...
Page 917: Handling Of Interrupts Coming From Spdifrx
RM0390 SPDIF receiver interface (SPDIFRX) 27.4.2 Handling of interrupts coming from SPDIFRX When an interrupt from the SPDIFRX is received, then the software has to check what is the source of the interrupt by reading the SPDIFRX_SR register. • If SYNCD is set to 1, then it means that the synchronization has been properly completed.
Page 918: Spdifrx Interface Registers
SPDIF receiver interface (SPDIFRX) RM0390 27.5 SPDIFRX interface registers 27.5.1 Control register (SPDIFRX_CR) Address offset: 0x00 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. INSEL[2:0] Res. Bits 31:19 Reserved, must be kept at reset value. Bits 18:16 INSEL[2:0]: SPDIFRX input selection 0b000: SPDIFRX_IN1 selected 0b001: SPDIFRX_IN2 selected...
Page 919 RM0390 SPDIF receiver interface (SPDIFRX) Bit 9 PTMSK: Mask of preamble type bits This bit is set/reset by software 1: The preamble type bits are not copied into the SPDIFRX_DR, zeros are written instead 0: The preamble type bits are copied into the SPDIFRX_DR Bit 8 CUMSK: Mask of channel status and user bits This bit is set/reset by software 1: The channel status and user bits are not copied into the SPDIFRX_DR, zeros are written instead...
Page 920: Interrupt Mask Register (Spdifrx_Imr)
SPDIF receiver interface (SPDIFRX) RM0390 27.5.2 Interrupt mask register (SPDIFRX_IMR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SYNCD SBLK PERR CSRNE RXNE Res. Res. Res.
Page 921: Status Register (Spdifrx_Sr)
RM0390 SPDIF receiver interface (SPDIFRX) 27.5.3 Status register (SPDIFRX_SR) Address offset: 0x08 Reset value: 0x0000 0000 Res. WIDTH5[14:0] Res. Res. Res. Res. Res. Res. Res. TERR SERR FERR SYNCD PERR CSRNE RXNE Bit 31 Reserved, must be kept at reset value. Bits 30:16 WIDTH5[14:0]: Duration of 5 symbols counted with SPDIFRX_CLK This value represents the amount of SPDIFRX_CLK clock periods contained on a length of 5 consecutive symbols.
Page 922 SPDIF receiver interface (SPDIFRX) RM0390 Bit 5 SYNCD: Synchronization Done This bit is set by hardware when the initial synchronization phase is properly completed. This flag is cleared by writing a 1 to its corresponding bit on SPDIFRX_CLR_SR register. An interrupt is generated if SYNCDIE = 1 in the SPDIFRX_IMR register 0: Synchronization is pending 1: Synchronization is completed Bit 4 SBD: Synchronization Block Detected...
Page 923: Interrupt Flag Clear Register (Spdifrx
RM0390 SPDIF receiver interface (SPDIFRX) 27.5.4 Interrupt flag clear register (SPDIFRX_IFCR) Address offset: 0x0C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SYNCD PERR Res. Res. Res. Res. Res.
Page 924: Data Input Register (Spdifrx_Dr)
SPDIF receiver interface (SPDIFRX) RM0390 27.5.5 Data input register (SPDIFRX_DR) Address offset: 0x10 Reset value: 0x0000 0000 This register can take 3 different formats according to DRFMT. Here is the format when DRFMT = 0b00: Res. Res. PT[1:0] DR[23:16] DR[15:0] Bits 31:30 Reserved, must be kept at reset value.
Page 925: Data Input Register (Spdifrx_Fmt1_Dr)
RM0390 SPDIF receiver interface (SPDIFRX) 27.5.6 Data input register (SPDIFRX_FMT1_DR) Address offset: 0x10 Reset value: 0x0000 0000 This register can take 3 different formats according to DRFMT. Here is the format when DRFMT = 0b01: DR[23:8] DR[7:0] Res. Res. PT[1:0] Bits 31:8 DR[23:0]: Data value Contains the 24 received data bits, aligned on D[23] Bits 7:6 Reserved, must be kept at reset value.
Page 926: Data Input Register (Spdifrx_Fmt2_Dr)
SPDIF receiver interface (SPDIFRX) RM0390 27.5.7 Data input register (SPDIFRX_FMT2_DR) Address offset: 0x10 Reset value: 0x0000 0000 This register can take 3 different formats according to DRFMT. The data format proposed when DRFMT = 0b10, is dedicated to non-linear mode, as only 16 bits are used (bits 23 to 8 from S/PDIF sub-frame).
Page 927: Channel Status Register (Spdifrx_Csr)
RM0390 SPDIF receiver interface (SPDIFRX) 27.5.8 Channel status register (SPDIFRX_CSR) Address offset: 0x14 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. CS[7:0] USR[15:0] Bits 31:25 Reserved, must be kept at reset value. Bit 24 SOB: Start Of Block This bit indicates if the bit CS[0] corresponds to the first bit of a new block 0: CS[0] is not the first bit of a new block 1: CS[0] is the first bit of a new block...
Page 928 SPDIF receiver interface (SPDIFRX) RM0390 Bits 28:16 TLO[12:0]: Threshold LOW (TLO = 1.5 x UI / T SPDIFRX_CLK This field contains the current threshold LOW estimation. This value can be used to estimate the sampling rate of the received stream. The accuracy of TLO is limited to a period of the SPDIFRX_CLK.
Page 929: Spdifrx Interface Register Map
RM0390 SPDIF receiver interface (SPDIFRX) 27.5.10 SPDIFRX interface register map Table 170 gives the SPDIFRX interface register map and reset values. Table 170. SPDIFRX interface register map and reset values Register Offset name SPDIFRX_CR 0x00 Reset value SPDIFRX_IMR 0x04 Reset value SPDIFRX_SR WIDTH5[14:0] 0x08...
Page 930: Serial Audio Interface (Sai)
Serial audio interface (SAI) RM0390 Serial audio interface (SAI) 28.1 Introduction The SAI interface (Serial Audio Interface) offers a wide set of audio protocols due to its flexibility and wide range of configurations. Many stereo or mono audio applications may be targeted.
Page 931: Sai Main Features
RM0390 Serial audio interface (SAI) 28.2 SAI main features • Two independent audio sub-blocks which can be transmitters or receivers with their respective FIFO. • 8-word integrated FIFOs for each audio sub-block. • Synchronous or asynchronous mode between the audio sub-blocks. •...
Page 932: Sai Functional Description
Serial audio interface (SAI) RM0390 28.3 SAI functional description 28.3.1 SAI block diagram Figure 354 shows the SAI block diagram while Table 171 Table 172 list SAI internal and external signals. Figure 354. SAI functional block diagram The SAI is mainly composed of two audio sub-blocks with their own clock generator. Each audio block integrates a 32-bit shift register controlled by their own functional state machine.
Page 933: Sai Pins And Internal Signals
RM0390 Serial audio interface (SAI) The audio sub-block can be a transmitter or receiver, in master or slave mode. The master mode means the SCK_x bit clock and the frame synchronization signal are generated from the SAI, whereas in slave mode, they come from another external or internal master. There is a particular case for which the FS signal direction is not directly linked to the master or slave mode definition.
Page 934: Sai Synchronization Mode
Serial audio interface (SAI) RM0390 Slave mode The SAI expects to receive timing signals from an external device. • If the SAI sub-block is configured in asynchronous mode, then SCK_x and FS_x pins are configured as inputs. • If the SAI sub-block is configured to operate synchronously with another SAI interface or with the second audio sub-block, the corresponding SCK_x and FS_x pins are left free to be used as general purpose I/Os.
Page 935: Audio Data Size
RM0390 Serial audio interface (SAI) Typically, the audio block in synchronous mode can be used to configure the SAI in full duplex mode. One of the two audio blocks can be configured as a master and the other as slave, or both as slaves with one asynchronous block (corresponding SYNCEN[1:0] bits set to 00 in SAI_xCR1) and one synchronous block (corresponding SYNCEN[1:0] bits set to 01 in the SAI_xCR1).
Page 936: Frame Synchronization
Serial audio interface (SAI) RM0390 28.3.6 Frame synchronization The FS signal acts as the Frame synchronization signal in the audio frame (start of frame). The shape of this signal is completely configurable in order to target the different audio protocols with their own specificities concerning this Frame synchronization behavior. This reconfigurability is done using register SAI_xFRCR.
Page 937 RM0390 Serial audio interface (SAI) Frame synchronization polarity FSPOL bit in the SAI_xFRCR register sets the active polarity of the FS pin from which a frame is started. The start of frame is edge sensitive. In slave mode, the audio block waits for a valid frame to start transmitting or receiving. Start of frame is synchronized to this signal.
Page 938: Figure 356. Fs Role Is Start Of Frame + Channel Side Identification (Fsdef = Tris = 1)
Serial audio interface (SAI) RM0390 Figure 356. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) 1. The frame length should be even. If FSDEF bit in SAI_xFRCR is kept clear, so FS signal is equivalent to a start of frame, and if the number of slots defined in NBSLOT[3:0] in SAI_xSLOTR multiplied by the number of bits by slot configured in SLOTSZ[1:0] in SAI_xSLOTR is less than the frame size (bit FRL[7:0] in the SAI_xFRCR register), then:...
Page 939: Slot Configuration
RM0390 Serial audio interface (SAI) Figure 357. FS role is start of frame (FSDEF = 0) The FS signal is not used when the audio block in transmitter mode is configured to get the SPDIF output on the SD line. The corresponding FS I/O will be released and left free for other purposes.
Page 940: Figure 358. Slot Size Configuration With Fboff = 0 In Sai_Xslotr
Serial audio interface (SAI) RM0390 Figure 358. Slot size configuration with FBOFF = 0 in SAI_xSLOTR It is possible to choose the position of the first data bit to transfer within the slots. This offset is configured by FBOFF[4:0] bits in the SAI_xSLOTR register. 0 values will be injected in transmitter mode from the beginning of the slot until this offset position is reached.
Page 941: Sai Clock Generator
RM0390 Serial audio interface (SAI) 28.3.8 SAI clock generator Each audio block has its own clock generator that makes these two blocks completely independent. There is no difference in terms of functionality between these two clock generators. When the audio block is configured as Master, the clock generator provides the communication clock (the bit clock) and the master clock for external decoders.
Page 942: Table 174. Example Of Possible Audio Frequency Sampling Range
Serial audio interface (SAI) RM0390 Table 174. Example of possible audio frequency sampling range Input sai_x_ker_ck Most usual audio frequency MCKDIV[3:0] clock frequency sampling achievable 192 kHz MCKDIV[3:0] = 0000 96 kHz MCKDIV[3:0] = 0001 192 kHz x 256 48 kHz MCKDIV[3:0] = 0010 16 kHz MCKDIV[3:0] = 0110...
Page 943: Internal Fifos
RM0390 Serial audio interface (SAI) 28.3.9 Internal FIFOs Each audio block in the SAI has its own FIFO. Depending if the block is defined to be a transmitter or a receiver, the FIFO can be written or read, respectively. There is therefore only one FIFO request linked to FREQ bit in the SAI_xSR register.
Page 944 Serial audio interface (SAI) RM0390 cleared by hardware when the FIFO becomes empty (FLVL[2:0] bits in SAI_xSR is equal to 000b) i.e no data are stored in FIFO. • When the FIFO threshold bits in SAI_xCR2 register are configured as FIFO quarter fully (FTH[2:0] set to 001b), an interrupt is generated (FREQ bit is set by hardware to 1 in SAI_xSR register) if at least one quarter of the FIFO data locations are available (FLVL[2:0] bits in SAI_xSR is higher or equal to 010b).
Page 945: Ac'97 Link Controller
RM0390 Serial audio interface (SAI) 28.3.10 AC’97 link controller The SAI is able to work as an AC’97 link controller. In this protocol: • The slot number and the slot size are fixed. • The frame synchronization signal is perfectly defined and has a fixed shape. To select this protocol, set PRTCFG[1:0] bits in the SAI_xCR1 register to 10.
Page 946: Figure 362. Example Of Typical Ac'97 Configuration On Devices Featuring At Least
Serial audio interface (SAI) RM0390 Figure 362. Example of typical AC’97 configuration on devices featuring at least 2 embedded SAIs (three external AC’97 decoders) In receiver mode, the SAI acting as an AC’97 link controller requires no FIFO request and so no data storage in the FIFO when the Codec ready bit in the slot 0 is decoded low.
Page 947: Spdif Output
RM0390 Serial audio interface (SAI) 28.3.11 SPDIF output The SPDIF interface is available in transmitter mode only. It supports the audio IEC60958. To select SPDIF mode, set PRTCFG[1:0] bit to 01 in the SAI_xCR1 register. For SPDIF protocol: • Only SD data line is enabled. •...
Page 948: Table 175. Sopd Pattern
Serial audio interface (SAI) RM0390 Table 175. SOPD pattern Preamble coding SOPD Description last bit is 0 last bit is 1 11101000 00010111 Channel A data at the start of block 11100100 00011011 Channel B data somewhere in the block 11100010 00011101 Channel A data...
Page 949: Table 177. Audio Sampling Frequency Versus Symbol Rates
RM0390 Serial audio interface (SAI) executed to recover from an underrun error detected via the underrun interrupt or the underrun status bit: Disable the DMA stream (via the DMA peripheral) if the DMA is used. Disable the SAI and check that the peripheral is physically disabled by polling the SAIEN bit in SAI_xCR1 register.
Page 950: Specific Features
Serial audio interface (SAI) RM0390 28.3.12 Specific features The SAI interface embeds specific features which can be useful depending on the audio protocol selected. These functions are accessible through specific bits of the SAI_xCR2 register. Mute mode The mute mode can be used when the audio sub-block is a transmitter or a receiver. Audio sub-block in transmission mode In transmitter mode, the mute mode can be selected at anytime.
Page 951: Figure 365. Data Companding Hardware In An Audio Block In The Sai
RM0390 Serial audio interface (SAI) In reception mode, the MONO bit can be set and is meaningful only if the number of slots is equal to 2 as in transmitter mode. When it is set, only slot 0 data will be stored in the FIFO. The data belonging to slot 1 will be discarded since, in this case, it is supposed to be the same as the previous slot.
Page 952 Serial audio interface (SAI) RM0390 Expansion and compression mode are automatically selected through the SAI_xCR2: • If the SAI audio block is configured to be a transmitter, and if the COMP[1] bit is set in the SAI_xCR2 register, the compression mode will be applied. •...
Page 953: Figure 366. Tristate Strategy On Sd Output Line On An Inactive Slot
RM0390 Serial audio interface (SAI) Figure 366. Tristate strategy on SD output line on an inactive slot When the selected audio protocol uses the FS signal as a start of frame and a channel side identification (bit FSDEF = 1 in the SAI_xFRCR register), the tristate mode is managed according to Figure 367 (where bit TRIS in the SAI_xCR1 register = 1, and FSDEF=1, and...
Page 954: Error Flags
Serial audio interface (SAI) RM0390 Figure 367. Tristate on output data line in a protocol like I2S If the TRIS bit in the SAI_xCR2 register is cleared, all the High impedance states on the SD output line on Figure 366 Figure 367 are replaced by a drive with a value of 0.
Page 955: Figure 368. Overrun Detection Error
RM0390 Serial audio interface (SAI) The OVRUDR flag is cleared when COVRUDR bit is set in the SAI_xCLRFR register. Figure 368. Overrun detection error Underrun An underrun may occur when the audio block in the SAI is a transmitter and the FIFO is empty when data need to be transmitted.
Page 956 Serial audio interface (SAI) RM0390 Anticipated frame synchronization detection (AFSDET) The AFSDET flag is used only in slave mode. It is never asserted in master mode. It indicates that a frame synchronization (FS) has been detected earlier than expected since the frame length, the frame polarity, the frame offset are defined and known.
Page 957: Disabling The Sai
RM0390 Serial audio interface (SAI) Codec not ready (CNRDY AC’97) The CNRDY flag in the SAI_xSR register is relevant only if the SAI audio block is configured to operate in AC’97 mode (PRTCFG[1:0] = 10 in the SAI_xCR1 register). If CNRDYIE bit is set in the SAI_xIM register, an interrupt is generated when the CNRDY flag is set.
Page 958: Sai Interrupts
Serial audio interface (SAI) RM0390 Follow the sequence below to configure the SAI interface in DMA mode: Configure SAI and FIFO threshold levels to specify when the DMA request will be launched. Configure SAI DMA channel. Enable the DMA. Enable the SAI interface. Note: Before configuring the SAI block, the SAI DMA channel must be disabled.
Page 959: Sai Registers
RM0390 Serial audio interface (SAI) 28.5 SAI registers 28.5.1 Global configuration register (SAI_GCR) Address offset: 0x00 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 960 Serial audio interface (SAI) RM0390 Bits 31:24 Reserved, must be kept at reset value. Bits 23:20 MCKDIV[3:0]: Master clock divider These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. 0000: Divides by 1 the master clock input.
Page 961 RM0390 Serial audio interface (SAI) Bits 11:10 SYNCEN[1:0]: Synchronization enable These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. 00: audio sub-block in asynchronous mode. 01: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode 10: audio sub-block is synchronous with an external SAI embedded peripheral.
Page 962: Configuration Register 2 (Sai_Acr2 / Sai_Bcr2)
Serial audio interface (SAI) RM0390 Bit 4 Reserved, must be kept at reset value. Bits 3:2 PRTCFG[1:0]: Protocol configuration These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. 00: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol (such as I2S, LSB/MSB justified, TDM, PCM/DSP...) by setting most of the configuration register bits as well as frame configuration register.
Page 963 RM0390 Serial audio interface (SAI) Bits 31:16 Reserved, must be kept at reset value. Bits 15:14 COMP[1:0]: Companding mode. These bits are set and cleared by software. The µ-Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0].
Page 964: Frame Configuration Register (Sai_Afrcr / Sai_Bfrcr)
Serial audio interface (SAI) RM0390 Bit 4 TRIS: Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled.
Page 965 RM0390 Serial audio interface (SAI) Bits 31:19 Reserved, must be kept at reset value. Bit 18 FSOFF: Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC’97 or SPDIF audio block configuration.
Page 966: Slot Register (Sai_Aslotr / Sai_Bslotr)
Serial audio interface (SAI) RM0390 28.5.5 Slot register (SAI_ASLOTR / SAI_BSLOTR) Address offset: Block A: 0x010 Address offset: Block B: 0x030 Reset value: 0x0000 0000 Note: This register has no meaning in AC’97 and SPDIF audio protocol SLOTEN[15:0] Res. Res. Res.
Page 967: Interrupt Mask Register 2 (Sai_Aim / Sai_Bim)
RM0390 Serial audio interface (SAI) Bits 7:6 SLOTSZ[1:0]: Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section : Output data line management on an inactive slot for information on how to drive...
Page 968: Status Register (Sai_Asr / Sai_Bsr)
Serial audio interface (SAI) RM0390 Bit 4 CNRDYIE: Codec not ready interrupt enable (AC’97). This bit is set and cleared by software. 0: Interrupt is disabled 1: Interrupt is enabled When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC’97 frame if the Codec connected to this line is ready or not.
Page 969 RM0390 Serial audio interface (SAI) Bits 31:19 Reserved, must be kept at reset value. Bits 18:16 FLVL[2:0]: FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: 000: FIFO empty 001: FIFO <= ¼...
Page 970: Clear Flag Register (Sai_Aclrfr / Sai_Bclrfr)
Serial audio interface (SAI) RM0390 Bit 3 FREQ: FIFO request. This bit is read only. 0: No FIFO request. 1: FIFO request to read or to write the SAI_xDR. The request depends on the audio block configuration: – If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR.
Page 971: Data Register (Sai_Adr / Sai_Bdr)
RM0390 Serial audio interface (SAI) Bits 31:7 Reserved, must be kept at reset value. Bit 6 CLFSDET: Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC’97or SPDIF mode Reading this bit always returns the value 0.
Page 972 Serial audio interface (SAI) RM0390 Bits 31:0 DATA[31:0]: Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty. 972/1328 RM0390 Rev 4...
Page 973: Sai Register Map
RM0390 Serial audio interface (SAI) 28.5.10 SAI register map The following table summarizes the SAI registers. Table 179. SAI register map and reset values Register Offset name SAI_GCR 0x0000 Reset value 0x0004 SAI_xCR1 0x0024 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 SAI_xCR2...
Page 974: Secure Digital Input/Output Interface (Sdio)
Secure digital input/output interface (SDIO) RM0390 Secure digital input/output interface (SDIO) 29.1 SDIO main features The SD/SDIO MMC card host interface (SDIO) provides an interface between the APB2 peripheral bus and MultiMediaCards (MMCs), SD memory cards and SDIO cards. The MultiMediaCard system specifications are available through the MultiMediaCard Association website, published by the MMCA technical committee.
Page 975: Figure 370. "No Response" And "No Data" Operations
RM0390 Secure digital input/output interface (SDIO) Figure 370. “No response” and “no data” operations Figure 371. (Multiple) block read operation Figure 372. (Multiple) block write operation Note: The SDIO will not send any data as long as the Busy signal is asserted (SDIO_D0 pulled low).
Page 976: Sdio Functional Description
Secure digital input/output interface (SDIO) RM0390 Figure 373. Sequential read operation Figure 374. Sequential write operation 29.3 SDIO functional description The SDIO consists of two parts: • The SDIO adapter block provides all functions specific to the MMC/SD/SD I/O card such as the clock generation unit, command and data transfer.
Page 977: Table 180. Sdio I/O Definitions
RM0390 Secure digital input/output interface (SDIO) By default SDIO_D0 is used for data transfer. After initialization, the host can change the databus width. If a MultiMediaCard is connected to the bus, SDIO_D0, SDIO_D[3:0] or SDIO_D[7:0] can be used for data transfer. MMC V3.31 or previous, supports only 1 bit of data so only SDIO_D0 can be used.
Page 978: Sdio Adapter
Secure digital input/output interface (SDIO) RM0390 29.3.1 SDIO adapter Figure 376 shows a simplified block diagram of an SDIO adapter. Figure 376. SDIO adapter The SDIO adapter is a multimedia/secure digital memory card bus master that provides an interface to a multimedia card stack or to a secure digital memory card. It consists of five subunits: •...
Page 979: Figure 377. Control Unit
RM0390 Secure digital input/output interface (SDIO) Figure 377. Control unit The control unit is illustrated in Figure 377. It consists of a power management subunit and a clock management subunit. The power management subunit disables the card bus output signals during the power-off and power-up phases.
Page 980: Figure 379. Sdio Adapter Command Path
Secure digital input/output interface (SDIO) RM0390 Command path The command path unit sends commands to and receives responses from the cards. Figure 379. SDIO adapter command path • Command path state machine (CPSM) – When the command register is written to and the enable bit is set, command transfer starts.
Page 981: Figure 380. Command Path State Machine (Sdio)
RM0390 Secure digital input/output interface (SDIO) Figure 380. Command path state machine (SDIO) When the Wait state is entered, the command timer starts running. If the timeout is reached before the CPSM moves to the Receive state, the timeout flag is set and the Idle state is entered.
Page 982: Table 181. Command Format
Secure digital input/output interface (SDIO) RM0390 Figure 381. SDIO command transfer • Command format – Command: a command is a token that starts an operation. Command are sent from the host either to a single card (addressed command) or to all connected cards (broadcast command are available for MMC V3.31 or previous).
Page 983: Table 182. Short Response Format
RM0390 Secure digital input/output interface (SDIO) Table 182. Short response format Bit position Width Value Description Start bit Transmission bit [45:40] Command index [39:8] Argument [7:1] CRC7(or 1111111) End bit Table 183. Long response format Bit position Width Value Description Start bit Transmission bit [133:128]...
Page 984: Figure 382. Data Path
Secure digital input/output interface (SDIO) RM0390 Data path The data path subunit transfers data to and from cards. Figure 382 shows a block diagram of the data path. Figure 382. Data path The card databus width can be programmed using the clock control register. If the 4-bit wide bus mode is enabled, data is transferred at four bits per clock cycle over all four data signals (SDIO_D[3:0]).
Page 985: Figure 383. Data Path State Machine (Dpsm)
RM0390 Secure digital input/output interface (SDIO) Figure 383. Data path state machine (DPSM) • Idle: the data path is inactive, and the SDIO_D[7:0] outputs are in Hi-Z. When the data control register is written and the enable bit is set, the DPSM loads the data counter with a new value and, depending on the data direction bit, moves to either the Wait_S or the Wait_R state.
Page 986: Table 185. Data Token Format
Secure digital input/output interface (SDIO) RM0390 Note: The DPSM remains in the Wait_S state for at least two clock periods to meet the N timing requirements, where N is the number of clock cycles between the reception of the card response and the start of the data transfer from the host.
Page 987: Table 186. Dpsm Flags
RM0390 Secure digital input/output interface (SDIO) DPSM Flags The status of the data path subunit transfer is reported by several status flags Table 186. DPSM flags Flag Description Set to high when data block send/receive CRC check is passed. DBCKEND In SDIO multibyte transfer mode this flag is set at the end of the transfer (a multibyte transfer is considered as a single block transfer by the host).
Page 988: Table 187. Transmit Fifo Status Flags
Secure digital input/output interface (SDIO) RM0390 Table 187. Transmit FIFO status flags Flag Description TXFIFOF Set to high when all 32 transmit FIFO words contain valid data. TXFIFOE Set to high when the transmit FIFO does not contain valid data. Set to high when 8 or more transmit FIFO words are empty.
Page 989: Sdio Apb2 Interface
RM0390 Secure digital input/output interface (SDIO) 29.3.2 SDIO APB2 interface The APB2 interface generates the interrupt and DMA requests, and accesses the SDIO adapter registers and the data FIFO. It consists of a data path, register decoder, and interrupt/DMA logic. SDIO interrupts The interrupt logic generates an interrupt request signal that is asserted when at least one of the selected status flags is high.
Page 990: Card Functional Description
Secure digital input/output interface (SDIO) RM0390 Example of write procedure using DMA Send CMD24 (WRITE_BLOCK) as follows: Program the SDIO data length register (SDIO data timer register should be already programmed before the card identification process) Program DMA channel (refer to DMA configuration for SDIO controller) Program the SDIO argument register with the address location of the card from...
Page 991: Card Reset
RM0390 Secure digital input/output interface (SDIO) 29.4.2 Card reset The GO_IDLE_STATE command (CMD0) is the software reset command and it puts the MultiMediaCard and SD memory in the Idle state. The IO_RW_DIRECT command (CMD52) resets the SD I/O card. After power-up or CMD0, all cards output bus drivers are in the high- impedance state and the cards are initialized with a default relative card address (RCA=0x0001) and with a default driver stage register setting (lowest speed, highest driving current capability).
Page 992: Block Write
Secure digital input/output interface (SDIO) RM0390 addresses the card. The assigned card changes to the Standby state, it does not react to further identification cycles, and its output switches from open-drain to push-pull. The SDIO card host repeats steps 5 through 7 until it receives a timeout condition. For the SD card, the identification process starts at clock rate F , and the SDIO_CMD line output drives are push-pull drivers instead of open-drain.
Page 993: Block Read
RM0390 Secure digital input/output interface (SDIO) Some cards may require long and unpredictable times to write a block of data. After receiving a block of data and completing the CRC check, the card begins writing and holds the SDIO_D line low if its write buffer is full and unable to accept new data from a new WRITE_BLOCK command.
Page 994 Secure digital input/output interface (SDIO) RM0390 The maximum clock frequency for a stream write operation is given by the following equation fields of the card-specific data register: 2 writebllen × ) NSAC – ( Maximumspeed MIN TRANSPEED ------------------------------------------------------------------------- TAAC × R2WFACTOR •...
Page 995: Erase: Group Erase And Sector Erase
RM0390 Secure digital input/output interface (SDIO) 29.4.8 Erase: group erase and sector erase The erasable unit of the MultiMediaCard is the erase group. The erase group is measured in write blocks, which are the basic writable units of the card. The size of the erase group is a card-specific parameter and defined in the CSD.
Page 996 Secure digital input/output interface (SDIO) RM0390 at the specified address) followed by 16 CRC bits. The address field in the write protect commands is a group address in byte units. The card ignores all LSBs below the group size. Mechanical write protect switch A mechanical sliding tab on the side of the card allows the user to set or clear the write protection on a card.
Page 997 RM0390 Secure digital input/output interface (SDIO) When a password replacement is done, the block size must take into account that both the old and the new passwords are sent with the command. Send LOCK/UNLOCK (CMD42) with the appropriate data block size on the data line including the 16-bit CRC.
Page 998 Secure digital input/output interface (SDIO) RM0390 When the password is previously set (PWD_LEN is not 0), the card is locked automatically after power on reset. An attempt to lock a locked card or to lock a card that does not have a password fails and the LOCK_UNLOCK_FAILED error bit is set in the card status register.
Page 999: Card Status Register
RM0390 Secure digital input/output interface (SDIO) 29.4.11 Card status register The response format R1 contains a 32-bit field named card status. This field is intended to transmit the card status information (which may be stored in a local status register) to the host.
Page 1000 Secure digital input/output interface (SDIO) RM0390 Table 189. Card status (continued) Clear Bits Identifier Type Value Description condition ’0’= no error An error in the sequence of erase ERASE_SEQ_ERROR ’1’= error commands occurred. ’0’= no error An invalid selection of erase groups for ERASE_PARAM ’1’= error erase occurred.

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