Reset and clock control (RCC)
Bit 4 TIM6EN: TIM6 timer clock enable
Set and cleared by software.
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 TIM2EN: TIM2 timer clock enable
Set and cleared by software.
116/874
0: TIM6 clock disabled
1: TIM6 clock enabled
0: TIM2 clock disabled
1: TIM2 clock enabled
RM0366 Rev 5
RM0366
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