ST STM32F301 6 Series Reference Manual page 704

Inter-integrated circuit interface (I2C)
25.9.5 I2C timing register (I2C_TIMINGR)
Address offset: 0x10
Reset value: 0x0000 0000
Access: no wait states
31 30 29
PRESC[3:0]
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15 14 13
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Bits 31:28 PRESC[3:0]: Timing prescaler
Bits 27:24 Reserved, must be kept at reset value.
Bits 23:20 SCLDEL[3:0]: Data setup time
Note: t
Bits 19:16 SDADEL[3:0]: Data hold time
Note: SDADEL is used to generate t
Bits 15:8 SCLH[7:0]: SCL high period (controller mode)
Note: SCLH is also used to generate t
Bits 7:0 SCLL[7:0]: SCL low period (controller mode)
Note: SCLL is also used to generate t
Note: This register must be configured when the I2C peripheral is disabled (PE = 0).
Note: The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C
Configuration window.
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28 27 26 25
Res. Res. Res.
rw
12 11 10 9
SCLH[7:0]
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This field is used to prescale I2CCLK to generate the clock period t
and hold counters (refer to section
(refer to section I2C controller
t = (PRESC + 1) x t
PRESC
This field is used to generate a delay t
and SCL rising edge. In controller and in target modes with NOSTRETCH = 0, the SCL line is
stretched low during t
SCLDEL
is used to generate t
SCLDEL
This field is used to generate the delay t
controller and in target modes with NOSTRETCH = 0, the SCL line is stretched low during
t .
SDADEL
t = SDADEL x t
SDADEL PRESC
This field is used to generate the SCL high period in controller mode.
t = (SCLH + 1) x t
SCLH PRESC
This field is used to generate the SCL low period in controller mode.
t = (SCLL + 1) x t
SCLL PRESC
24 23 22
Res. SCLDEL[3:0]
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8 7 6
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I2C timings), and for SCL high and low level counters
initialization).
I2CCLK
= (SCLDEL + 1) x t
SCLDEL
.
timing.
SU:DAT
between SCL falling edge and SDA edge. In
SDADEL
timing.
HD:DAT
and t
SU:STO HD:STA
and t
BUF SU:STA
RM0366 Rev 5
21 20 19 18
SDADEL[3:0]
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5 4 3 2
SCLL[7:0]
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used for data setup
PRESC
between SDA edge
PRESC
timing.
timings.
RM0366
17 16
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1 0
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