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RM0366
12.6.2
ADC common control register (ADCx_CCR, x=1)
Address offset: 0x08 (this offset address is relative to the master ADC base address +
0x300)
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:25 Reserved, must be kept at reset value.
Bit 24 VBATEN: V
This bit is set and cleared by software to enable/disable the V
Note: Software is allowed to write this bit only when the ADCs are disabled (ADCAL=0,
Bit 23 TSEN: Temperature sensor enable
This bit is set and cleared by software to enable/disable the temperature sensor channel.
Note: Software is allowed to write this bit only when the ADCs are disabled (ADCAL=0,
Bit 22 VREFEN: V
This bit is set and cleared by software to enable/disable the V
Note: Software is allowed to write this bit only when the ADCs are disabled (ADCAL=0,
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
Res.
enable
BAT
0: V
channel disabled
BAT
1: V
channel enabled
BAT
JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
0: Temperature sensor channel disabled
1: Temperature sensor channel enabled
JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
enable
REFINT
0: V
channel disabled
REFINT
1: V
channel enabled
REFINT
JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
24
23
22
VBAT
TS
VREF
EN
EN
EN
rw
rw
rw
8
7
6
Res.
Res.
Res.
RM0366 Rev 5
Analog-to-digital converters (ADC)
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
channel.
BAT
channel.
REFINT
17
16
CKMODE[1:0]
rw
rw
1
0
Res.
Res.
273/874
277
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