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RM0366
Bits 31:1 Reserved, must be kept at reset value.
11.3.12
Pending register (EXTI_PR2)
Address offset: 0x34
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:1 Reserved, must be kept at reset value.
11.3.13
EXTI register map
Table 29. External interrupt/event controller register map and reset values
Offset
Register
EXTI_IMR1
0x00
Reset value
EXTI_EMR1
0x04
Reset value
EXTI_RTSR1
0x08
Reset value
Bit 0 SWIERx: Software interrupt on line x (x = 32)
If the interrupt is enabled on this line in the EXTI_IMR, writing a '1' to this bit when
it is at '0' sets the corresponding pending bit in EXTI_PR resulting in an interrupt
request generation.
This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a '1' to
the bit).
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Bit 0 PRx: Pending bit on line x (x = 32)
0: No trigger request occurred
1: Selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt line.
This bit is cleared by writing a '1' into the bit.
MR[25:22]
0
1
1
1
1
MR[25:22]
0
0
0
0
0
0
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RM0366 Rev 5
Interrupts and events
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
MR[17:0]
0
0
0
0
0
0
0
0
MR[17:0]
0
0
0
0
0
0
0
0
TR[17:0]
0
0
0
0
0
0
0
0
17
16
Res.
Res.
1
0
Res.
PR32
rc_w1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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