ST STM32F301 6 Series Reference Manual page 665

RM0366
Figure 255. Transfer bus diagrams for I2C target transmitter (mandatory events only)
Example I2C
NOSTRETCH=0:
S Address
TXE
EV1: ADDR ISR: check ADDCODE and DIR, set TXE, set ADDRCF
EV2: TXIS ISR: wr data1
EV3: TXIS ISR: wr data2
EV4: TXIS ISR: wr data3
EV5: TXIS ISR: wr data4 (not sent)
Example I2C
NOSTRETCH=0:
S Address
TXE
EV1: ADDR ISR: check ADDCODE and DIR, set ADDRCF
EV2: TXIS ISR: wr data2
EV3: TXIS ISR: wr data3
EV4: TXIS ISR: wr data4 (not sent)
Example I2C
S
EV1
TXE
EV1: wr data1
EV2: TXIS ISR: wr data2
EV3: TXIS ISR: wr data3
EV4: TXIS ISR: wr data4 (not sent)
EV5: STOPF ISR: (optional: set TXE and TXIS), set STOPCF
target transmitter 3 bytes with 1st data flushed,
ADDR TXIS
TXIS
A
data1 A
EV2
EV1 EV3
transmitter 3 bytes without 1st data flush,
target
TXIS TXIS
ADDR
A data1 A
EV2
EV1
transmitter 3 bytes, NOSTRETCH=1:
target
TXIS TXIS
Address data1 A
A
EV2 EV3
Inter-integrated circuit interface (I2C)
TXIS TXIS
data3
data2 A
EV4 EV5
TXIS
data2 A data3 NA
EV3 EV4
TXIS
data2 A data3 NA P
EV4
RM0366 Rev 5
legend:
transmission
reception
SCL stretch
NA P
legend :
transmission
reception
SCL stretch
P
legend:
transmission
STOPF
reception
SCL stretch
EV5
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