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RM0366
Bit 7 WDGA: Activation bit
Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB)
22.5.2
WWDG configuration register (WWDG_CFR)
Address offset: 0x004
Reset value: 0x0000 007F
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:10 Reserved, must be kept at reset value.
Bit 9 EWI: Early wake-up interrupt enable
Bits 8:7 WDGTB[1:0]: Timer base
Bits 6:0 W[6:0]: 7-bit window value
22.5.3
WWDG status register (WWDG_SR)
Address offset: 0x008
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
These bits contain the value of the watchdog counter, decremented every
[1:0]
WDGTB
(4096 x 2
) PCLK cycles. A reset is produced when it is decremented from 0x40 to
0x3F (T6 becomes cleared).
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
EWI
rs
Set by software and cleared by hardware after a reset. When set, an interrupt occurs
whenever the counter reaches the value 0x40.
The time base of the prescaler can be modified as follows:
00: CK counter clock (PCLK div 4096) div 1
01: CK counter clock (PCLK div 4096) div 2
10: CK counter clock (PCLK div 4096) div 4
11: CK counter clock (PCLK div 4096) div 8
These bits contain the window value to be compared with the down-counter.
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
Res.
System window watchdog (WWDG)
24
23
22
Res.
Res.
Res.
Res.
8
7
6
WDGTB[1:0]
rw
rw
rw
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
Res.
RM0366 Rev 5
21
20
19
18
Res.
Res.
Res.
5
4
3
2
W[6:0]
rw
rw
rw
rw
21
20
19
18
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
17
16
Res.
Res.
1
0
rw
rw
17
16
Res.
Res.
1
0
Res.
EWIF
rc_w0
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