ST STM32F301 6 Series Reference Manual page 818

Serial peripheral interface / integrated interchip sound (SPI/I2S)
Figure 338
by the reset and clock controller (RCC) of the product. The I2SxCLK clock can be
asynchronous with respect to the SPI/I2S APB clock.
Warning:
To achieve high-quality audio performance, the I2SxCLK clock source can be an external
clock (mapped to the I2S_CKIN pin). Refer to
(RCC_CFGR).
The audio sampling frequency may be 192 KHz, 96 kHz or 48 kHz.
In order to reach the desired frequency, the linear divider needs to be programmed
according to the formulas below:
2
For I S modes:
When the master clock is generated (MCKOE in the SPIx_I2SPR register is set):
When the master clock is disabled (MCKOE bit cleared):
CHLEN = 0 when the channel frame is 16-bit wide and,
CHLEN = 1 when the channel frame is 32-bit wide.
For PCM modes:
When the master clock is generated (MCKOE in the SPIx_I2SPR register is set):
When the master clock is disabled (MCKOE bit cleared):
CHLEN = 0 when the channel frame is 16-bit wide and,
CHLEN = 1 when the channel frame is 32-bit wide.
818/874
presents the communication clock architecture. The I2SxCLK clock is provided
In addition, it is mandatory to keep the I2SxCLK frequency
higher or equal to the APB clock used by the SPI/I2S block. If
this condition is not respected the SPI/I2S does not work
properly.
Fs
= ---------------------------------------------------------------------------------------------------------- -
256
Fs
= ----------------------------------------------------------------------------------------------------------------------------------------------------------------- -
× (
32 CHLEN
Fs
= ---------------------------------------------------------------------------------------------------------- -
128
Fs
= ----------------------------------------------------------------------------------------------------------------------------------------------------------------- -
× (
16 CHLEN
RM0366 Rev 5
Section 7.4.2: Clock configuration register
F
I2SxCLK
× ( 2 ( × I2SDIV )
+
F
I2SxCLK
1 ) × ( 2 ( × I2SDIV )
+
F
I2SxCLK
× ( 2 ( × I2SDIV )
+
F
I2SxCLK
1 ) × ( 2 ( × I2SDIV )
+
ODD )
ODD )
+
ODD )
ODD )
+
RM0366