ST STM32F301 6 Series Reference Manual page 469

RM0366
1. Configure TIM1 master mode to send its Update Event (UEV) as trigger output
(MMS=010 in the TIM1_CR2 register).
2. Configure the TIM1 period (TIM1_ARR registers).
3. Configure TIM2 to get the input trigger from TIM1 (TS=000 in the TIM2_SMCR
register).
4. Configure TIM2 in trigger mode (SMS=110 in TIM2_SMCR register).
5. Start TIM1 by writing '1 in the CEN bit (TIM1_CR1 register).
TIM2-CEN=CNT_EN
As in the previous example, both counters can be initialized before starting counting.
Figure 197
mode instead of gated mode (SMS=110 in the TIM2_SMCR register).
TIM1-CEN=CNT_EN
Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2
signals must be enabled prior to receive events from the master timer, and the clock
frequency (prescaler) must not be changed on-the-fly while triggers are received from the
master timer.
Figure 196. Triggering TIM2 with update of TIM1
CK_INT
TIM1-UEV
TIM1-CNT
TIM2-CNT
TIM2-TIF
shows the behavior with the same configuration as in
Figure 197. Triggering TIM2 with Enable of TIM1
CK_INT
TIM1-CNT_INIT
75
TIM1-CNT
TIM2-CNT
TIM2-CNT_INIT
TIM2
write CNT
TIM2-TIF
FD FE FF
45
Write TIF = 0
00
CD 00 E7
Write TIF = 0
RM0366 Rev 5
General-purpose timer (TIM2)
00 01 02
46 47 48
Figure 196
01 02
E8 E9 EA
MS32697V1
but in trigger
MS32698V1
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