ST STM32F301 6 Series Reference Manual page 467

RM0366
1. Configure TIM1 in master mode so that it outputs a periodic trigger signal on each
update event UEV. If MMS=010 is written in the TIM1_CR2 register, a rising edge is
output on TRGO each time an update event is generated.
2. To connect the TRGO output of TIM1 to TIM2, TIM2 must be configured in slave mode
using ITR0 as internal trigger. This is selected through the TS bits in the TIM2_SMCR
register (writing TS=000).
3. Then the slave mode controller must be put in external clock mode 1 (write SMS=111 in
the TIM2_SMCR register). This causes TIM2 to be clocked by the rising edge of the
periodic TIM1 trigger signal (which correspond to the TIM1 counter overflow).
4. Finally both timers must be enabled by setting their respective CEN bits (TIMx_CR1
register).
Note: If OCx is selected on TIM1 as the trigger output (MMS=1xx), its rising edge is used to clock
the counter of TIM2.
Using one timer to enable another timer
In this example, we control the enable of TIM2 with the output compare 1 of Timer 1. Refer
to Figure 192
of TIM1 is high. Both counter clock frequencies are divided by 3 by the prescaler compared
to CK_INT (f
1. Configure TIM1 master mode to send its Output Compare 1 Reference (OC1REF)
signal as trigger output (MMS=100 in the TIM1_CR2 register).
2. Configure the TIM1 OC1REF waveform (TIM1_CCMR1 register).
3. Configure TIM2 to get the input trigger from TIM1 (TS=000 in the TIM2_SMCR
register).
4. Configure TIM2 in gated mode (SMS=101 in TIM2_SMCR register).
5. Enable TIM2 by writing '1 in the CEN bit (TIM2_CR1 register).
6. Start TIM1 by writing '1 in the CEN bit (TIM1_CR1 register).
Note: The counter 2 clock is not synchronized with counter 1, this mode only affects the TIM2
counter enable signal.
TIM1-OC1REF
In the example in
started. So they start counting from their current value. It is possible to start from a given
value by resetting both timers before starting TIM1. Then any value can be written in the
timer counters. The timers can easily be reset by software using the UG bit in the
TIMx_EGR registers.
for connections. TIM2 counts on the divided internal clock only when OC1REF
= f /3).
CK_CNT CK_INT
Figure 194. Gating TIM2 with OC1REF of TIM1
CK_INT
TIM1-CNT
FC
TIM2-CNT
3045
TIM2-TIF
Write TIF = 0
Figure 194, the TIM2 counter and prescaler are not initialized before being
RM0366 Rev 5
FD FE FF
3046 3047
General-purpose timer (TIM2)
00 01
3048
MS32695V2
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